CN111627928A - Flexible display panel, preparation method of flexible display panel and flexible display - Google Patents
Flexible display panel, preparation method of flexible display panel and flexible display Download PDFInfo
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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Abstract
The application relates to a flexible display panel, a preparation method of the flexible display panel and a flexible display; the flexible display panel comprises an etching barrier layer, and the etching barrier layer is arranged between an interlayer dielectric layer and a planarization layer of the flexible display panel; the etching barrier layer in the display area of the flexible display panel is provided with a through hole; the through hole is used for being communicated with the contact hole of the flexible display panel and enabling a source drain metal layer of the flexible display panel to penetrate through the through hole, the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel, and the etching barrier effect of the etching barrier layer is utilized to ensure that the depth and the width of the contact hole manufactured under the photomask process are uniform, so that the performance of the flexible display panel is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a flexible display panel, a preparation method of the flexible display panel and a flexible display.
Background
With the continuous development of display technology, the OLED (organic light-Emitting Diode) display technology gradually becomes the mainstream technology in the display field with its unique advantages of low power consumption, high saturation, fast response time, wide viewing angle, etc., and has a wide application prospect in vehicle-mounted, mobile phone, tablet, computer and television products in the future, especially a flexible display panel in the OLED display technology.
In the manufacturing Process of the flexible display panel, a Deep Hole (DH) design is adopted in the Bending region, and a normal Process Flow (Process Flow, PF) is performed by using a 2-pass mask Process (Photo), but in order to save the cost in the manufacturing Process, the Contact hole and the Deep hole are completed by a 1-pass mask Process, which is abbreviated as CDH (CNT & DH) Process, in the CDH Process, the Contact hole and the Deep hole region need to be etched through by a Dry etching Process (Dry etch, DE) at one time, but as shown in fig. 1, the photoresist thickness on the interlayer dielectric layer is not uniform, and the depth and width of the hole manufactured by the time are not uniform, so that in the implementation Process, the inventor finds that at least the following problems exist in the conventional technology: the depth and width of the holes in conventional flexible display panels are not uniform, resulting in poor performance of the flexible display panel.
Disclosure of Invention
Based on this, it is necessary to provide a flexible display panel, a method for manufacturing the flexible display panel, and a flexible display, aiming at the problem of non-uniformity of depth and width of holes in the conventional flexible display panel.
In order to achieve the above object, in one aspect, an embodiment of the present application provides a flexible display panel, including an etching barrier layer;
the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel; the etching barrier layer in the display area of the flexible display panel is provided with a through hole; the through hole is used for being communicated with the contact hole of the flexible display panel and enabling the source drain metal layer of the flexible display panel to penetrate through the through hole.
In one embodiment, the material of the etching barrier layer is one or any combination of the following materials: aluminum oxide, hafnium oxide, and indium tin oxide.
On the other hand, the embodiment of the application also provides a preparation method of the flexible display panel, which comprises the following steps:
providing a flexible substrate, wherein a multiple barrier layer, a buffer layer, an active layer, a grid insulating layer, a grid layer and an interlayer dielectric layer are formed on the flexible substrate;
forming an etching barrier layer on the interlayer dielectric layer, and forming a photoresist layer on the etching barrier layer;
forming a contact hole penetrating through the etching barrier layer, the interlayer dielectric layer and the grid insulation layer in the display area by adopting a photomask process based on the photoresist layer, and forming deep holes penetrating through the etching barrier layer, the interlayer dielectric layer, the grid insulation layer, the buffer layer and the multiple barrier layers in the bending area; the sidewall of one end of the contact hole is in contact with the active layer.
In one embodiment, the step of forming a contact hole penetrating through an etching stop layer, an interlayer dielectric layer and a gate insulating layer in a display region by using a photomask process based on a photoresist layer, and forming a deep hole penetrating through the etching stop layer, the interlayer dielectric layer, the gate insulating layer, a buffer layer and a multiple barrier layer in a bending region includes the steps of:
etching the etching barrier layer which is not covered by the photoresist layer in the bending area until the interlayer dielectric layer is exposed;
dry etching the exposed interlayer dielectric layer and the exposed grid insulation layer until part of the grid insulation layer is etched to form a transition hole;
and etching the barrier layer, the interlayer dielectric layer and the grid insulating layer by a dry method to form a contact hole, and expanding the transition hole to obtain a deep hole.
In one embodiment, the step of forming a multiple barrier layer, a buffer layer, an active layer, a gate insulating layer, a gate layer and an interlayer dielectric layer on a flexible substrate includes:
sequentially forming a multiple barrier layer, a buffer layer and an active layer on a flexible substrate;
forming a gate insulating layer covering the active layer on the buffer layer, and forming a gate electrode layer on the gate insulating layer; the grid layer is opposite to the active layer;
an interlayer dielectric layer is formed on the gate insulating layer to cover the gate layer.
In one embodiment, the gate insulating layer includes a first gate insulating layer and a second gate insulating layer; the gate layers comprise a first gate layer and a second gate layer;
the step of forming a gate insulating layer covering the active layer on the buffer layer and forming a gate electrode layer on the gate insulating layer includes:
forming a first gate insulating layer covering the active layer on the buffer layer, and forming a first gate layer on the first gate insulating layer; the first grid layer is opposite to the active layer;
forming a second gate insulating layer on the first gate insulating layer to cover the first gate layer, and forming a second gate layer on the second gate insulating layer; the second gate layer and the first gate layer.
In one embodiment, in the step of sequentially forming the multiple barrier layers, the buffer layer and the active layer on the flexible substrate:
and carrying out polycrystallization treatment on the initial material of the active layer by adopting an excimer laser crystallization technology to obtain the active layer.
In one embodiment, the method further includes, after the step of forming deep holes penetrating through the etch stop layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer, and the multiple barrier layer in the bending region based on the photoresist layer by using a photo-masking process to form contact holes penetrating through the etch stop layer, the interlayer dielectric layer, and the gate insulating layer in the display region, the step of forming deep holes penetrating through the etch stop layer, the interlayer dielectric layer, the gate insulating layer:
forming a first source drain metal layer in the contact hole; one end of the first source drain metal layer extends to the etching barrier layer;
depositing an organic material in the deep hole to form an organic hole layer, and forming a second source-drain metal layer on the organic hole layer.
In one embodiment, after the steps of depositing an organic material in the deep hole, forming an organic hole layer, and forming a second source-drain metal layer on the organic hole layer, the method further includes the steps of:
forming a planarization layer covering the first source drain metal layer and the second source drain metal layer on the gate insulating layer and the organic pore layer;
a pixel anode, a pixel defining layer and an organic supporting layer are sequentially formed on the planarization layer.
In another aspect, an embodiment of the present application further provides a flexible display, including the flexible display panel described above.
One of the above technical solutions has the following advantages and beneficial effects:
the flexible display panel provided by each embodiment of the application comprises an etching barrier layer; the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel; the etching barrier layer in the display area of the flexible display panel is provided with a through hole; the through hole is used for being communicated with the contact hole of the flexible display panel and enabling a source drain metal layer of the flexible display panel to penetrate through the through hole, the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel, and the etching barrier effect of the etching barrier layer is utilized to ensure that the depth and the width of the contact hole manufactured under the photomask process are uniform, so that the performance of the flexible display panel is improved.
Drawings
FIG. 1 is a schematic diagram illustrating a non-uniform photoresist thickness in a conventional technique;
FIG. 2 is a schematic diagram of a flexible display panel according to an embodiment;
FIG. 3 is a schematic structural diagram of a flexible display panel according to another embodiment;
FIG. 4 is a schematic flow chart illustrating a method for fabricating a flexible display panel according to one embodiment;
FIG. 5 is a schematic flow chart illustrating the steps of forming multiple barrier layers, buffer layers, active layers, gate insulating layers, gate layers and interlayer dielectric layers in one embodiment;
FIG. 6 is a schematic structural diagram of a flexible display panel in yet another embodiment;
FIG. 7 is a schematic flow chart of the step of forming the transition hole and the deep hole in one embodiment;
FIG. 8 is a schematic flow chart illustrating a step of forming a source drain metal layer in one embodiment;
FIG. 9 is a flowchart illustrating the steps of forming a planarization layer, a pixel anode, a pixel definition layer, and an organic support layer, in one embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "in contact with" another element, it can be directly connected to the other element or intervening elements may also be present. The terms "disposed," "end," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In order to solve the problem of poor performance of the flexible display panel due to non-uniform depth and width of the holes in the conventional flexible display panel, in one embodiment, as shown in fig. 2, a flexible display panel is provided, which includes an etch barrier layer 21;
the etching barrier layer 21 is disposed between the interlayer dielectric layer 23 and the planarization layer 25 of the flexible display panel; the etching barrier layer 21 in the display area of the flexible display panel is provided with a through hole 211; the through hole 211 is used to communicate with the contact hole 27 of the flexible display panel and to pass through the source-drain metal layer 29 of the flexible display panel.
It should be noted that the etching stop layer is used to prevent the flexible display panel from abnormal phenomena such as over-etching in the photo-mask process, and is beneficial to ensuring the uniform depth and thickness of the hole made by the photo-mask process, specifically, the contact hole of the display area of the flexible display panel.
The protective process of the etching barrier layer in the photomask process is as follows: a mask process is adopted in a photomask process to form a photoresist layer on an etching barrier layer, the thickness of the photoresist layer is uneven due to technical reasons, for example, photoresist still remains at the position of a pattern on the photoresist layer, redundant photoresist is removed firstly (the interlayer dielectric layer of the flexible display panel cannot be etched when the redundant photoresist is removed due to the action of the etching barrier layer), then etching is carried out based on the complete pattern on the photoresist layer, a through hole is formed on the etching barrier layer in the display area of the flexible display panel, a contact hole is formed on the interlayer dielectric layer and the grid insulation layer of the flexible display panel by continuous etching, and the contact hole is communicated with the through hole and used for placing a source drain metal layer of the flexible display panel.
The material for forming the etching barrier layer can be determined according to actual requirements, and the selected principle is that a material with higher etching selection ratio (etching selection ratio is more than 50) of silicon oxide (SiO)/silicon nitride (SiN) to the interlayer dielectric layer is selected in the etching process. In one example, the material of the etching barrier layer is one or any combination of the following materials: aluminum oxide, hafnium oxide, and indium tin oxide.
Further, as shown in fig. 3, the flexible display panel further includes a multiple barrier layer 31, a buffer layer 33, an active layer 35, a gate insulating layer 37, a gate electrode layer 39, a pixel anode 41, a pixel defining layer 43, and an organic support layer 45.
In each embodiment of the flexible display panel, the flexible display panel comprises an etching barrier layer; the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel; the etching barrier layer in the display area of the flexible display panel is provided with a through hole; the through hole is used for being communicated with the contact hole of the flexible display panel and enabling a source drain metal layer of the flexible display panel to penetrate through the through hole, the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel, and the etching barrier effect of the etching barrier layer is utilized to ensure that the depth and the width of the contact hole manufactured under the photomask process are uniform, so that the performance of the flexible display panel is improved.
In one embodiment, as shown in fig. 4, there is also provided a method for manufacturing a flexible display panel, including the steps of:
in step S41, a flexible substrate is provided, and a multiple barrier layer, a buffer layer, an active layer, a gate insulating layer, a gate electrode layer, and an interlayer dielectric layer are formed on the flexible substrate.
Note that the Multi-Barrier layer (MB) is formed of an inorganic material. The Buffer layer (Buffer) is formed of an inorganic material (e.g., gan or aln, etc.), and plays a role of buffering and protection together with the multiple barrier layers. The active (Poly) layer is formed of a polysilicon material and serves as a source. A Gate Insulator (GI) layer is formed of an inorganic material, such as silicon nitride or silicon oxide, for isolating the active layer and the Gate layer. The Gate (GE) layer is formed of a conductive material, such as tantalum, tungsten, tantalum nitride, or titanium nitride. The interlayer dielectric (ILD) layer is formed of a dielectric material, such as a fluoropolymer matrix or inorganic titanate surface-modified with fluorosilane.
In one example, as shown in fig. 5, the step of forming a multiple barrier layer, a buffer layer, an active layer, a gate insulating layer, a gate electrode layer, and an interlayer dielectric layer on a flexible substrate includes:
in step S411, a multiple barrier layer, a buffer layer, and an active layer are sequentially formed on a flexible substrate.
It should be noted that, by using a deposition process, the multiple barrier layers, the buffer layer, and the active layer are sequentially formed on the flexible substrate. Further, the multiple barrier layers, buffer layers and active layers may be formed using, but not limited to, the following methods: chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).
In one example, the formation process of the active layer is: and depositing the material of the active layer on the buffer layer, and patterning the material by adopting a photoetching process to obtain the active layer.
Since the active layer is composed of polycrystalline silicon, which needs to be polycide after depositing the single crystalline silicon, in one example, in the step of sequentially forming the multiple barrier layers, the buffer layer, and the active layer on the flexible substrate:
and carrying out polycrystallization treatment on the initial material of the active layer by adopting an excimer laser crystallization technology to obtain the active layer.
Step S413 of forming a gate insulating layer covering the active layer on the buffer layer, and forming a gate electrode layer on the gate insulating layer; the gate layer is opposite to the active layer.
It should be noted that, by using a deposition process, a gate insulating layer is formed on the buffer layer, the active layer is buried in the gate insulating layer, and then a gate layer is deposited on the gate insulating layer, where the gate layer is formed at a position opposite to the active layer, that is, the gate layer is stacked on the active layer with the gate insulating layer therebetween. Further, the gate insulating layer and the gate electrode layer may be formed by, but not limited to, the following methods: chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).
In one example, as shown in fig. 6, the gate insulating layer 23 includes a first gate insulating layer 231 and a second gate insulating layer 233; the gate layer 39 includes a first gate layer 391 and a second gate layer 393;
the step of forming a gate insulating layer covering the active layer on the buffer layer and forming a gate electrode layer on the gate insulating layer includes:
forming a first gate insulating layer covering the active layer on the buffer layer, and forming a first gate layer on the first gate insulating layer; the first grid layer is opposite to the active layer;
forming a second gate insulating layer on the first gate insulating layer to cover the first gate layer, and forming a second gate layer on the second gate insulating layer; the second gate layer and the first gate layer.
In step S415, an interlayer dielectric layer covering the gate electrode layer is formed on the gate insulating layer.
It should be noted that, by using a deposition process to form an interlayer dielectric layer on the gate insulating layer and bury the gate layer in the interlayer dielectric layer, further, the interlayer dielectric layer can be formed by, but is not limited to, the following methods: chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).
Step S43, an etch stop layer is formed on the interlayer dielectric layer, and a photoresist layer is formed on the etch stop layer.
It should be noted that, by using a deposition process, an etch stop layer is formed on the interlayer dielectric layer, and then a photoresist layer is formed on the etch stop layer. The photoresist layer is used for providing an etching pattern, and due to the process for forming the photoresist layer, the quality difference, the proportion and the thickness of the photoresist layer are uneven, and a small amount of photoresist is filled in the pattern, so that the depth and the width of the hole formed by the traditional structure through the photomask process are uneven. The present application eliminates this situation by etching the barrier layer.
Step S45, forming a contact hole penetrating through the etching barrier layer, the interlayer dielectric layer and the grid insulation layer in the display area by adopting a photomask process based on the photoresist layer, and forming a deep hole penetrating through the etching barrier layer, the interlayer dielectric layer, the grid insulation layer, the buffer layer and the multiple barrier layers in the bending area; the sidewall of one end of the contact hole is in contact with the active layer.
It should be noted that, at first, the excess photoresist in the pattern on the photoresist layer is removed to expose the etching stop layer at the pattern position of the photoresist layer, the etching stop layer, the interlayer dielectric layer and the gate insulating layer in the display region are etched to form a contact hole penetrating through the etching stop layer, the interlayer dielectric layer and the gate insulating layer, and at the same time, the etching stop layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer and the multiple barrier layer in the bending region are etched to form a deep hole penetrating through the etching stop layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer and the multiple barrier layer (e.g., 47 in fig. 6.
Specifically, as shown in fig. 7, the step of forming a contact hole penetrating through the etching stop layer, the interlayer dielectric layer, and the gate insulating layer in the display region by using a photomask process based on the photoresist layer, and forming a deep hole penetrating through the etching stop layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer, and the multiple stop layers in the bending region includes the steps of:
step S451, etching the etching barrier layer which is not covered by the photoresist layer in the bending area until the interlayer dielectric layer is exposed;
step S453, dry etching the exposed interlayer dielectric layer and the exposed gate insulating layer until part of the gate insulating layer is etched to form a transition hole;
and step S455, etching the barrier layer, the interlayer dielectric layer and the gate insulating layer by a dry method to form a contact hole, and expanding the transition hole to obtain a deep hole.
It should be noted that, in the bending region of the flexible display panel, a part of the etching barrier layer is not covered by the photoresist layer, the etching barrier layer at the position is removed by using an etching process (which may be, but is not limited to, dry etching or wet etching), the interlayer dielectric layer at the position is exposed, and the interlayer dielectric layer and the gate insulating layer at the position are continuously etched by using the dry etching process until a part of the gate insulating layer is etched to form a transition hole, so as to prepare for forming a deep hole subsequently.
After the transition hole is finished, a dry etching process is adopted, the barrier layer, the interlayer dielectric layer and the grid electrode insulating layer of the display area are etched at the same time to form a contact hole, and the transition hole is expanded to form a deep hole of the bending area.
In one example, as shown in fig. 8, after the steps of forming a contact hole penetrating through the etch stop layer, the interlayer dielectric layer, and the gate insulating layer in the display region based on the photoresist layer by using a photo-masking process, and forming a deep hole penetrating through the etch stop layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer, and the multiple barrier layer in the bending region, the method further includes the steps of:
step S87, forming a first source-drain metal layer (291 in fig. 6) in the contact hole; one end of the first source drain metal layer extends to the etching barrier layer;
step S89, depositing an organic material in the deep hole to form an organic hole layer, and forming a second source/drain metal layer (293 in fig. 6) on the organic hole layer.
It should be noted that, a deposition process is adopted to manufacture a source drain metal layer for connecting a source electrode and a drain electrode, specifically, a first source drain metal layer is formed in the contact hole, and after filling an organic material in the deep hole, two source drain metal layers are formed on the organic material.
In one embodiment, as shown in fig. 9, after the steps of depositing an organic material in the deep hole, forming an organic hole layer, and forming a second source-drain metal layer on the organic hole layer, the method further includes the steps of:
step S911, forming a planarization layer covering the first source drain metal layer and the second source drain metal layer on the gate insulating layer and the organic hole layer;
in step S913, a pixel anode, a pixel defining layer, and an organic supporting layer are sequentially formed on the planarization layer.
It should be noted that, after the first source-drain metal layer and the second source-drain metal layer are formed, a deposition process is adopted to fabricate a planarization layer for providing a flat surface for a subsequent process, the planarization layer covers the gate insulating layer and the organic hole layer, and the first source-drain metal layer and the second source-drain metal layer are buried therein.
After the planarization layer is formed, a deposition process is adopted, and a pixel anode, a pixel definition layer and an organic supporting layer are sequentially formed, wherein the pixel anode is used for supplying power to the pixel unit, the pixel definition layer is used for defining the shape of the pixel, and the organic supporting layer is used for providing support for the pixel unit.
In each embodiment of the preparation method of the flexible display panel, the etching barrier layer is formed on the interlayer dielectric layer, and the problem of uneven photoresist is solved by utilizing the etching barrier layer to block the etching function, so that the depth and the width of the contact hole of the display area supported in the photomask process are uniform, the quality of the flexible display panel is improved, the mask process can be saved, and the production cost is reduced.
It should be understood that although the various steps in the flowcharts of fig. 4, 5, 7-9 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 4, 5, 7-9 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, a flexible display is also provided, which includes the flexible display panel according to the embodiments of the present application.
It should be noted that the flexible display panel in this embodiment is the same as the flexible display panel described in the embodiments of the flexible display panel of the present application, and for the specific description, reference is made to the description of the embodiments of the flexible display panel of the present application, and details are not repeated here.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A flexible display panel is characterized by comprising an etching barrier layer;
the etching barrier layer is arranged between the interlayer dielectric layer and the planarization layer of the flexible display panel; the etching barrier layer in the display area of the flexible display panel is provided with a through hole; the through hole is used for being communicated with the contact hole of the flexible display panel and enabling the source drain metal layer of the flexible display panel to penetrate through the through hole.
2. The flexible display panel according to claim 1, wherein the material of the etching barrier layer is one or any combination of the following materials: aluminum oxide, hafnium oxide, and indium tin oxide.
3. A preparation method of a flexible display panel is characterized by comprising the following steps:
providing a flexible substrate, wherein a multiple barrier layer, a buffer layer, an active layer, a grid insulating layer, a grid layer and an interlayer dielectric layer are formed on the flexible substrate;
forming an etching barrier layer on the interlayer dielectric layer, and forming a photoresist layer on the etching barrier layer;
forming a contact hole penetrating through the etching barrier layer, the interlayer dielectric layer and the gate insulating layer in a display region by adopting a photomask process based on the photoresist layer, and forming a deep hole penetrating through the etching barrier layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer and the multiple barrier layers in a bending region; the side wall of one end of the contact hole is in contact with the active layer.
4. The method for manufacturing a flexible display panel according to claim 3, wherein the step of forming a contact hole penetrating through the etching stopper layer, the interlayer dielectric layer, and the gate insulating layer in the display region by using a photo-masking process based on the photoresist layer, and forming a deep hole penetrating through the etching stopper layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer, and the multiple stopper layer in the bending region comprises the steps of:
etching the etching barrier layer which is not covered by the photoresist layer in the bending area until the interlayer dielectric layer is exposed;
dry etching the exposed interlayer dielectric layer and the exposed grid insulation layer until part of the grid insulation layer is etched to form a transition hole;
and etching the etching barrier layer, the interlayer dielectric layer and the grid electrode insulating layer by a dry method to form the contact hole, and expanding the transition hole to obtain the deep hole.
5. The method of manufacturing a flexible display panel according to claim 3 or 4, wherein the step of forming the multiple barrier layer, the buffer layer, the active layer, the gate insulating layer, the gate layer, and the interlayer dielectric layer on the flexible substrate comprises:
sequentially forming the multiple barrier layers, the buffer layer and the active layer on the flexible substrate;
forming the gate insulating layer covering the active layer on the buffer layer, and forming the gate electrode layer on the gate insulating layer; the grid layer is opposite to the active layer;
forming the interlayer dielectric layer covering the gate electrode layer on the gate insulating layer.
6. The method for manufacturing a flexible display panel according to claim 5, wherein the gate insulating layer comprises a first gate insulating layer and a second gate insulating layer; the gate layers comprise a first gate layer and a second gate layer;
the step of forming the gate insulating layer on the buffer layer to cover the active layer and forming the gate electrode layer on the gate insulating layer includes:
forming the first gate insulating layer on the buffer layer to cover the active layer, and forming the first gate layer on the first gate insulating layer; the first gate layer is opposite to the active layer;
forming the second gate insulating layer covering the first gate layer on the first gate insulating layer, and forming the second gate layer on the second gate insulating layer; the second gate layer and the first gate layer.
7. The method for manufacturing a flexible display panel according to claim 5, wherein in the step of sequentially forming the multiple barrier layer, the buffer layer, and the active layer on the flexible substrate:
and carrying out polycrystalline silicification on the initial material of the active layer by adopting an excimer laser crystallization technology to obtain the active layer.
8. The method for manufacturing a flexible display panel according to claim 3 or 4, wherein a photomask process is used to form contact holes penetrating through the etch stop layer, the interlayer dielectric layer, and the gate insulating layer in a display region based on the photoresist layer, and after the step of forming deep holes penetrating through the etch stop layer, the interlayer dielectric layer, the gate insulating layer, the buffer layer, and the multiple barrier layers in a bending region, the method further comprises:
forming a first source drain metal layer in the contact hole; one end of the first source drain metal layer extends to the etching barrier layer;
and depositing an organic material in the deep hole to form an organic hole layer, and forming a second source-drain metal layer on the organic hole layer.
9. The method for manufacturing a flexible display panel according to claim 8, wherein after the steps of depositing an organic material in the deep hole to form an organic hole layer and forming a second source-drain metal layer on the organic hole layer, the method further comprises the steps of:
forming a planarization layer covering the first source drain metal layer and the second source drain metal layer on the gate insulating layer and the organic hole layer;
and sequentially forming a pixel anode, a pixel definition layer and an organic supporting layer on the planarization layer.
10. A flexible display comprising the flexible display panel of claims 1 and 2.
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107910335A (en) * | 2017-11-08 | 2018-04-13 | 武汉华星光电半导体显示技术有限公司 | Flexible display panels, flexible display panels production method and display device |
CN107910349A (en) * | 2017-10-27 | 2018-04-13 | 京东方科技集团股份有限公司 | A kind of flexible display panels and production method |
CN108288637A (en) * | 2018-01-24 | 2018-07-17 | 武汉华星光电半导体显示技术有限公司 | The production method and flexible display panels of flexible display panels |
CN109671761A (en) * | 2018-12-19 | 2019-04-23 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
CN110137186A (en) * | 2019-05-30 | 2019-08-16 | 京东方科技集团股份有限公司 | Flexible display substrates and its manufacturing method |
CN110349974A (en) * | 2019-06-25 | 2019-10-18 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof, display device |
CN111106149A (en) * | 2019-12-04 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
-
2020
- 2020-05-20 CN CN202010432755.4A patent/CN111627928B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107910349A (en) * | 2017-10-27 | 2018-04-13 | 京东方科技集团股份有限公司 | A kind of flexible display panels and production method |
CN107910335A (en) * | 2017-11-08 | 2018-04-13 | 武汉华星光电半导体显示技术有限公司 | Flexible display panels, flexible display panels production method and display device |
CN108288637A (en) * | 2018-01-24 | 2018-07-17 | 武汉华星光电半导体显示技术有限公司 | The production method and flexible display panels of flexible display panels |
CN109671761A (en) * | 2018-12-19 | 2019-04-23 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
CN110137186A (en) * | 2019-05-30 | 2019-08-16 | 京东方科技集团股份有限公司 | Flexible display substrates and its manufacturing method |
CN110349974A (en) * | 2019-06-25 | 2019-10-18 | 武汉华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof, display device |
CN111106149A (en) * | 2019-12-04 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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