CN111627484B - Nor flash erase disturbance correction method and device - Google Patents
Nor flash erase disturbance correction method and device Download PDFInfo
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- CN111627484B CN111627484B CN202010473665.XA CN202010473665A CN111627484B CN 111627484 B CN111627484 B CN 111627484B CN 202010473665 A CN202010473665 A CN 202010473665A CN 111627484 B CN111627484 B CN 111627484B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a method and a device for correcting Nor flash erase interference, which are characterized in that in the process of carrying out block erase operation on a selected Nor flash array block, interference confirmation and correction are carried out on all Nor flash array blocks in the same physical array only under the condition that the operation of setting the Nor flash array block is judged to meet interference confirmation conditions; or determining the Nor flash array block for interference confirmation and correction based on the cycle times corresponding to the cycle flow in the block erasing operation; or determining the Nor flash array block for interference confirmation and correction based on the counting result of a certain clock in the chip or system by the counter; or based on the block address of a certain Nor flash array block which is physically stored, only one Nor flash array block is subjected to interference confirmation and correction each time the block erasing operation is carried out. By adopting the mode, the interference confirmation and correction can be avoided being carried out on all the remaining Nor flash array blocks in the same physical array in each block erasing operation, so that the aims of reducing the time for confirming and correcting the erasing interference and reducing the power consumption are fulfilled.
Description
Technical Field
The present invention relates to the field of flash memory technologies, and in particular, to a method and an apparatus for correcting an erase disturbance of a non-volatile flash memory (Nor flash).
Background
With the rapid development of portable electronic products, particularly after the process characteristic size is smaller than 65nnm, the floating gate type flash memory chip memory area is generally placed in a physical concentration manner to save the chip area, so as to form a physical memory matrix, and each physical memory matrix is logically divided into a plurality of Nor flash array blocks constructed based on the floating gate technology. Since different Nor flash array blocks are located on the same P-type substrate (PWELL), when an erase operation is performed on one Nor flash array block in the same physical memory array, since the Nor flash array block is connected with the drain region, the source region and the P well of the surrounding Nor flash array block, the remaining Nor flash array blocks in the same physical memory array are disturbed by the drain terminal voltage and the P well voltage.
In order to avoid the above-mentioned influence, when an erase operation is performed on one Nor flash array block, an erase disturbance correction algorithm is used to detect all memory cells in the Nor flash array block which is not selected to be erased in the same physical memory array, determine whether each memory cell storing data "0" is disturbed, and if so, perform disturbance correction through programming refresh.
However, in the erase disturb correction method of the prior art, every memory cell in all the Nor flash array blocks that are not selected to be erased in the same physical memory array needs to be subjected to disturb detection verification and correction, which consumes a long time in erase disturb verification and correction, which is far more than the sum of time consumed by other operation processes in the Nor flash array block erase flow, thereby not only increasing the time consumption of the overall erase operation, but also increasing the power consumption of the overall erase operation.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method and an apparatus for correcting an erase disturb of a Nor flash array, so as to achieve the purpose of reducing time consumed for verifying and correcting an erase disturb and reducing power consumption of an overall erase operation in a block erase process of a selected Nor flash array block.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
the embodiment of the invention discloses a Nor flash erase interference correction method on one hand, which comprises the following steps:
judging whether the operation of setting a Nor flash array block meets a specific condition or not in the process of carrying out block erasing operation on the selected Nor flash array block of the nonvolatile flash memory in the physical storage array, if so, carrying out interference confirmation and correction on all the remaining Nor flash array blocks in the physical storage array, and if not, continuing the block erasing operation;
or, in the process of carrying out block erasing operation on the selected Nor flash array block in the physical storage array, determining the block address of the Nor flash array block to be processed based on the cycle times of each flow in the block erasing operation process recorded by a counter in the flash memory chip, or the number of clock signals generated by any oscillator in the flash memory chip or the number of clock signals provided by an application system of the flash memory chip;
based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address;
or acquiring block addresses of all Nor flash array blocks in a pre-recorded physical storage array;
when block erasing operation is carried out for multiple times, interference confirmation and correction are carried out on the Nor flash array block corresponding to one block address in each block erasing operation, wherein each Nor flash array block only carries out interference confirmation and correction once before interference confirmation and correction are carried out on all Nor flash array blocks.
Optionally, in the process of performing a block erase operation on a Nor flash array block of a nonvolatile flash memory selected in the physical memory array, determining whether an operation for setting the Nor flash array block satisfies a specific condition includes:
performing interference confirmation on one or more Nor flash array blocks in the rest Nor flash array blocks in the process of performing block erasing operation on the selected Nor flash array block of the nonvolatile flash memory in the physical storage array;
judging whether one or more data in one or more Nor flash array blocks in the rest Nor flash array blocks are rewritten;
if yes, determining that a specific condition is met;
if not, determining that the specific condition is not met.
Optionally, in the process of performing a block erase operation on a Nor flash array block of a non-volatile flash memory selected in a physical memory array, determining whether an operation for setting the Nor flash array block satisfies a specific condition includes:
recording the times of block erasing operation of a selected Nor flash array block of a nonvolatile flash memory in a physical storage array in the process of performing the block erasing operation on the selected Nor flash array block;
detecting whether the times are larger than a preset value or not, wherein the value range of the preset value comprises 1k to 100k;
if so, determining that a specific condition is met;
if not, determining that the specific condition is not satisfied.
Optionally, in the process of performing a block erase operation on the Nor flash array block selected in the physical storage array, determining a block address of the Nor flash array block to be processed based on the cycle times of each flow in the block erase operation process recorded by a counter inside the flash memory chip, including:
in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, recording cycle times corresponding to any flow in a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip;
and selecting the cycle number corresponding to any one of a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow as the block address of the Nor flash array block to be processed.
Optionally, in the process of performing a block erase operation on the Nor flash array block selected in the physical storage array, determining a block address of the Nor flash array block to be processed based on the cycle times of each flow in the block erase operation process recorded by a counter inside the flash memory chip, including:
in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, recording cycle times corresponding to any flow in a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip;
and calculating the sum of the cycle times corresponding to a plurality of or all of the procedures in the pre-programming procedure, the block erasing procedure, the over-erasing automatic correction procedure and the soft programming procedure to be used as the block address of the Nor flash array block to be processed.
Optionally, in the process of performing a block erase operation on a Nor flash array block selected in the physical storage array, determining a block address of the Nor flash array block to be processed based on the number of clock signals generated by any oscillator in the flash memory chip and recorded by a counter inside the flash memory chip or the number of clock signals provided by an application system of the flash memory chip, includes:
in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, a counter in a flash memory chip starts to record clock signals from power-on reset of the flash memory chip, and records the clock signals after the soft programming flow of the block erasing operation is finished to obtain the number of the clock signals; or, in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, a counter in the flash memory chip records clock signals from any flow of the block erasing operation, and records the clock signals at any flow of the block erasing operation to obtain the number of the clock signals;
taking the clock signal quantity as the block address of the Nor flash array block to be processed;
the clock signal includes any clock signal inside the flash memory chip, or a clock signal input outside the flash memory chip.
Optionally, the process of recording in advance the block address of the Nor flash array block in the physical storage array includes:
and acquiring and recording the block address of the selected Nor flash array block for interference confirmation and correction when the selected Nor flash array block is erased in the physical storage array each time.
Optionally, the pre-recording the block address of the Nor flash array block in the physical storage array includes:
acquiring the power-on times of a flash memory chip;
and determining and recording the block address of the Nor flash array block in the physical storage array based on the power-on times.
The embodiment of the invention also discloses a Nor flash erase interference correction device, which comprises:
the first correction module is used for judging whether the operation of setting the Nor flash array block meets an interference confirmation condition or not in the process of carrying out block erasing operation on the Nor flash array block of the nonvolatile flash memory selected in the physical storage array, if so, carrying out interference confirmation and correction on all the residual Nor flash array blocks in the physical storage array, and if not, continuing carrying out block erasing operation; and/or the presence of a gas in the atmosphere,
the second correction module is used for determining the block address of the Nor flash array block to be processed based on the cycle times of each flow path in the block erasing operation process recorded by a counter in the flash memory chip in the process of performing the block erasing operation on the Nor flash array block selected in the physical storage array, or determining the block address of the Nor flash array block to be processed based on the number of clock signals generated by any oscillator in the flash memory chip or provided by an application system of the flash memory chip, which is recorded by the counter in the flash memory chip; based on the block address, performing interference confirmation and correction on the to-be-processed Nor flash array block corresponding to the block address; and/or the presence of a gas in the atmosphere,
the third correction module is used for acquiring the block address of the Nor flash array block in the pre-recorded physical storage array; when multiple block erasing operations are carried out, interference confirmation and correction are carried out on the Nor flash array block corresponding to one block address in each block erasing operation, wherein each Nor flash array block only carries out interference confirmation and correction once before interference confirmation and correction are carried out on all the Nor flash array blocks.
Optionally, the second correcting module is specifically configured to record, based on a counter inside the flash memory chip, cycle times corresponding to any one of a pre-programming flow, a block erase flow, an over-erase automatic correction flow, and a soft programming flow in a process of performing a block erase operation on a Nor flash array block selected in the physical storage array; selecting the cycle number corresponding to any one of a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow as the block address of the Nor flash array block to be processed; based on the block address, performing interference confirmation and correction on the to-be-processed Nor flash array block corresponding to the block address;
or recording the cycle times corresponding to any flow in a pre-programming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip in the process of carrying out block erasing operation on the selected Nor flash array block in the physical storage array; calculating the sum of the cycle times corresponding to a plurality of or all of the procedures in the pre-programming procedure, the block erasing procedure, the over-erasing automatic correction procedure and the soft programming procedure to be used as the block address of the Nor flash array block to be processed; and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
Based on the method and the device for correcting the Nor flash erase interference provided by the embodiment of the invention, in the process of carrying out block erase operation on a selected Nor flash array block of a nonvolatile flash memory in a physical storage array, whether the operation for setting the Nor flash array block meets an interference confirmation condition is judged, if so, interference confirmation and correction are carried out on all the Nor flash array blocks in the physical storage array, and if not, the block erase operation is continued; or determining the block address of the Nor flash array block to be processed and performing corresponding interference confirmation and correction based on the cycle times of each flow in the block erasing operation process recorded by a counter in the flash chip, or based on the number of clock signals generated by any oscillator in the flash chip or the number of clock signals provided by an application system of the flash chip recorded by the counter in the flash chip; or based on the block address arrangement sequence of all the Nor flash array blocks in the predetermined physical storage array, when multiple block erasing operations are performed, interference confirmation and correction are performed on the Nor flash array block corresponding to one block address only in each block erasing operation. In the scheme, the Nor flash array blocks needing interference confirmation and correction are confirmed in different modes, so that interference confirmation and correction on all other remaining Nor flash array blocks in the physical storage array in each block erasing operation can be avoided, and the aims of reducing time consumed by erasing interference confirmation and correction and reducing the power consumption of the whole erasing operation are fulfilled.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a block erase operation;
FIG. 2 is a flowchart illustrating a method for correcting Nor flash erase disturb according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for correcting Nor flash erase disturb according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for correcting Nor flash erase disturb according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating another method for correcting interference caused by Nor flash erase according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating another method for correcting Nor flash erase disturb, according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating another method for correcting Nor flash erase disturb, according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating another method for correcting Nor flash erase disturb, according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating another method for correcting Nor flash erase disturb, according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a Nor flash erase disturb correction apparatus according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "...," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
At present, a Nor flash array block based on a floating gate technology mainly comprises a substrate, and a source end, a drain end, a gate end and a floating gate which are arranged on the substrate.
The programming operation of the Nor flash array block is based on the CHE principle: the source terminal and the substrate are biased by 0V voltage, the drain terminal is biased by 5V voltage, the control grid terminal is biased by 10V voltage, and the hot electron at the drain terminal is stored to the floating grid through the tunneling oxide layer. At this time, the threshold voltage of the memory cell increases, representing writing of "0" data.
The Nor flash array block erase operation is based on the FN tunneling principle: the source end and the drain end are suspended, the substrate biases to have high voltage of 10V, the control grid end biases to have negative voltage of-8V, electrons stored in the floating grid tunnel to the substrate based on an FN tunneling mechanism, and electrons in the floating grid are erased. At this point, the threshold voltage of the memory cell is reduced, representing the erasure back of "1" data.
Currently, a block erase operation on a Nor flash array block in a physical memory array in a flash memory chip is shown in fig. 1, and mainly includes the following steps:
s101: an erase command for the Nor flash array block is received.
S102: the selected Nor flash array block is pre-programmed.
S103: judging whether the pre-programming is finished or not, and if so, executing S104; if not, the process continues to step S102.
S102 is executed to program all memory cells of the selected Nor flash array block, and the state of the memory cells is judged in the preprogramming process, namely S103 is executed to judge whether the preprogramming is finished or not until all the memory cells are programmed to be in a 0 state.
S104: and carrying out a block erasing operation on the selected Nor flash array block.
S105: and (4) confirming whether the over-erasing is performed, if not, executing S106, and if so, executing S107.
S106: and executing the over-erasure automatic correction operation.
S107: confirming whether the block erasing operation is finished or not, and if so, executing S108; if not, the process continues to step S107.
S108: a soft programming operation is performed.
S109: determining whether the soft programming operation is completed, and if so, executing S110; if not, the process continues to step S109.
S110: an erasure interference correction operation is performed.
As can be seen from the background art, the existing erase operation for the Nor flash array block consumes a long time to verify and correct the erase disturb, which is far more than the sum of the time consumed by other operation processes in the Nor flash array block erase flow, and not only increases the time consumption of the overall erase operation, but also increases the power consumption of the overall erase operation.
Therefore, the embodiment of the application discloses a new Nor flash erase disturbance correcting method, so as to achieve the purposes of reducing the time consumed by erase disturbance confirmation and correction and reducing the overall erase operation power consumption in the process of carrying out block erase on a selected Nor flash array block. The specific implementation process is illustrated in detail by the following examples.
Fig. 2 is a flowchart illustrating a method for correcting a Nor flash erase disturb according to an embodiment of the invention. The Nor flash erase disturbance correction method mainly comprises the following steps:
s201: judging whether the operation of setting the Nor flash array block meets a specific condition or not in the process of carrying out block erasing operation on the Nor flash array block of the nonvolatile flash memory selected in the physical storage array, and if so, executing S202; if not, the block erase operation is continued.
S202: and performing interference confirmation and correction on all the remaining Nor flash array blocks in the physical storage array.
In the execution of S201 and S202, in order to avoid performing interference confirmation and correction on all Nor flash array blocks in the process of performing a block erase operation on a selected non-volatile flash Nor flash array block in the physical memory array, before performing a block erase operation on any selected Nor flash array block, one or more Nor flash array blocks are pre-designated as a reference Nor flash array block for determining whether or not to perform interference confirmation and correction on all remaining Nor flash array blocks, that is, the Nor flash array block is set.
Since erase disturb is an accumulation process, the data "0" in the memory cell being overwritten by the disturb needs to be accumulated through a number of block erases larger than 1k. Based on the method, interference confirmation and correction of all Nor flash array blocks remaining in the physical storage array are not needed every time block erasure is carried out. Thus, the specific condition includes two cases, and the interference confirmation and correction are performed on all Nor flash array blocks remaining in the physical memory array only if either of the two cases is satisfied.
In the first case: data "0" in the memory cell of the Nor flash array block that is designated as set is rewritten.
In the first case, the set Nor flash array block is one or more Nor flash array blocks in the unselected Nor flash array block.
As shown in fig. 3, a flowchart of a Nor flash erase disturb correction method according to an embodiment of the present invention mainly includes the following steps:
s301: and in the process of carrying out block erasing operation on the selected non-volatile flash Nor flash array block in the physical storage array, carrying out interference confirmation on one or more Nor flash array blocks in the rest Nor flash array blocks.
S302: judging whether one or more data in one or more Nor flash array blocks in the rest Nor flash array blocks are rewritten, if so, indicating that one or more data are rewritten, determining that a specific condition is met, and executing S303; if not, it indicates that one or more overwrite bits have not been achieved, and determines that the specific condition is not satisfied, the process proceeds to S302.
In S302, it is determined whether data "0" is rewritten, and if it is rewritten, it is determined that the first condition is satisfied, and it is necessary to perform interference confirmation and correction on all Nor flash array blocks remaining in the physical memory array. If not, the accumulated number of times of block erasing is not reached to the condition that interference confirmation and correction are needed to be carried out on all the Nor flash array blocks left in the physical storage array.
S303: and performing interference confirmation and correction on all the remaining Nor flash array blocks in the physical storage array.
It should be noted that, in the first case, one or more Nor flash array blocks may be set for any selected Nor flash array block. That is, the Nor flash array block can be set correspondingly when the block erase operation is performed on the selected Nor flash array block.
According to the embodiment of the invention, by judging whether the set Nor flash array block meets the specific condition, before the set Nor flash array block does not meet the specific condition, interference confirmation and correction are not carried out on all the remaining Nor flash array blocks, so that the time cost of block erasing can be effectively reduced, and the power consumption of the whole erasing operation can be reduced.
In the second case: the number of block erase operations of the selected Nor flash array block is greater than a preset value.
In the second case, the set Nor flash array block is the selected Nor flash array block.
As shown in fig. 4, a flowchart of a Nor flash erase disturb correction method according to an embodiment of the present invention mainly includes the following steps:
s401: in the process of carrying out block erasing operation on a selected non-volatile flash memory Nor flash array block in a physical storage array, recording the number of times of block erasing operation of the selected Nor flash array block.
S402: detecting whether the times are greater than a preset value, if so, determining that a specific condition is met, and executing S403; if not, determining that the specific condition is not satisfied, and continuing to execute S402.
In S402, the value range of the preset value includes 1k to 100k; when the number of times of block erasing operations of the selected Nor flash array block is detected to exceed any one of the number from 1k to 100k, the second condition is determined to be met, and interference confirmation and correction are required to be carried out on all the remaining Nor flash array blocks in the physical storage array. If not, the accumulated number of block erasures is not reached to the condition that interference confirmation and correction are needed to be carried out on all the Nor flash array blocks left in the physical storage array.
S403: and performing interference confirmation and correction on all the remaining Nor flash array blocks in the physical storage array.
According to the embodiment of the invention, by judging whether the set Nor flash array block meets the specific condition, before the selected Nor flash array block does not meet the specific condition, interference confirmation and correction are not carried out on all the remaining Nor flash array blocks, so that the time cost of block erasing can be effectively reduced, and the power consumption of the whole erasing operation can be reduced.
FIG. 5 is a flowchart illustrating another method for correcting a Nor flash erase disturb according to an embodiment of the present invention. The Nor flash erase disturbance correction method mainly comprises the following steps:
s501: and determining the block address of the Nor flash array block to be processed based on the cycle times of each flow in the block erasing operation process recorded by a counter in the flash memory chip in the process of performing the block erasing operation on the Nor flash array block selected in the physical storage array.
S502: and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
When executing S501 and S502, the cycle times of each flow in the block erasing operation process recorded by a counter in the flash memory chip are used as random numbers, the block address of the Nor flash array block consistent with the random numbers is determined based on the random numbers, the Nor flash array block corresponding to the block address is used as the Nor flash array block to be processed, and only the Nor flash array block to be processed is subjected to interference confirmation and correction in the process of carrying out the block erasing operation on the selected Nor flash array block.
In a specific implementation, as shown in fig. 1, the flows during the block erase operation include a pre-programming flow, a block erase flow, an over-erase auto-correction flow, and a soft programming flow. When each flow carries out block erasing operation on the selected Nor flash array block, the respective cycle times have randomness, so that the cycle times can be used as random numbers for determining the to-be-processed Nor flash array block for interference confirmation and correction.
In a specific implementation, the block address of the Nor flash array block to be processed can be determined in different ways as follows, and corresponding interference confirmation and correction can be performed.
As shown in fig. 6, a flowchart of another norflash erase disturb correction method according to an embodiment of the present invention mainly includes the following steps:
s601: in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, recording cycle times corresponding to any flow in a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip.
S602: and selecting the cycle number corresponding to any one of a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow as the block address of the Nor flash array block to be processed.
In S602, the cycle number corresponding to any one of the pre-programming flow, the block erasing flow, the over-erase automatic correction flow, and the soft programming flow involved in the block erasing operation may be arbitrarily selected as a random number, a block address of the Nor flash array block corresponding to the random number is determined based on the random number, and the Nor flash array block corresponding to the block address is used as the Nor flash array block to be processed.
In a specific implementation, the preferred choice is the number of cycles of a preprogrammed process.
S603: and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
In the embodiment of the invention, the cycle times of each flow in the block erasing operation process recorded by the existing counter in the flash memory chip are used as random numbers, and no extra peripheral equipment is needed to generate the random numbers, so that the cost of the block erasing operation can be reduced.
As shown in fig. 7, a flowchart of another norflash erase disturb correction method according to an embodiment of the present invention mainly includes the following steps:
s701: in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, recording cycle times corresponding to any flow in a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip.
S702: and calculating the sum of the cycle times corresponding to a plurality of or all of the procedures in the pre-programming procedure, the block erasing procedure, the over-erasing automatic correction procedure and the soft programming procedure to be used as the block address of the Nor flash array block to be processed.
S703: and based on the block address, performing interference confirmation and correction on the to-be-processed Nor flash array block corresponding to the block address.
In the embodiment of the invention, the cycle times of each flow in the block erasing operation process recorded by the existing counter in the flash memory chip are used as random numbers, and no extra peripheral equipment is needed to generate the random numbers, so that the cost of the block erasing operation can be reduced.
It should be noted that it is within the scope of the present application to perform erase disturb verification and correction on a Nor flash array block as long as the random block address is generated by counting through a counter.
FIG. 8 is a flowchart illustrating another method for correcting Nor flash erase disturb according to an embodiment of the present invention. The Nor flash erase disturbance correcting method mainly comprises the following steps:
s801: in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, determining the block address of the Nor flash array block to be processed based on the number of clock signals generated by any oscillator in a flash memory chip or the number of clock signals provided by an application system of the flash memory chip, which are recorded by a counter in the flash memory chip.
In S801, the clock signal includes any clock signal inside the flash memory chip, or a clock signal input outside the flash memory chip. Optionally, the clock signal may be an input clock of a charge pump inside the flash memory chip.
Because the counter inside the flash memory chip is usually triggered to count by the power-on reset signal of the flash memory chip, the counter generates the random block address only after the flash memory chip is powered on for the first time, therefore, the random block address is generated. When the flash memory chip is continuously erased without power failure, the address of the block for erasing interference confirmation and correction is added with 1 on the basis of the initial random address.
In the process of executing S801, optionally, in the process of performing a block erase operation on a Nor flash array block selected in a physical storage array, first, a counter inside the flash memory chip starts to record a clock signal from power-on reset of the flash memory chip, and finishes recording the clock signal in a soft programming flow of the block erase operation, so as to obtain a number of the clock signals; and then, taking the clock signal quantity as the block address of the Nor flash array block to be processed.
Optionally, in the process of performing a block erase operation on a Nor flash array block selected in a physical memory array, first, a counter inside the flash memory chip records a clock signal from any flow of the block erase operation, and records the clock signal at any flow of the block erase operation, so as to obtain the number of the clock signals; and then, taking the clock signal as the block address of the Nor flash array block to be processed.
It should be noted that, as long as the random block address is generated by counting through the counter, the erase disturb verification and correction are performed on a certain logic block, which is within the protection scope of the present application.
S802: and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
In the embodiment of the invention, the clock signal recorded by the counter in the flash memory chip is used as the reference, the block address of the Nor flash array block to be processed is confirmed according to the number of the clock signals, and the Nor flash array block corresponding to the block address is subjected to erasing interference confirmation and correction, so that the interference confirmation and correction of all the remaining Nor flash array blocks can be avoided, the time cost of block erasing is effectively reduced, and the power consumption of the whole erasing operation is reduced.
FIG. 9 is a flowchart illustrating another method for correcting Nor flash erase disturb according to an embodiment of the present invention. The Nor flash erase disturbance correction method mainly comprises the following steps:
s901: and acquiring the block address of the Nor flash array block in the pre-recorded physical storage array.
In S901, the process of recording block addresses of Nor flash array blocks in a physical storage array in advance includes the following two ways:
the first mode is as follows:
and acquiring and recording the block address of the selected Nor flash array block for interference confirmation and correction when the selected Nor flash array block is erased in the physical storage array each time.
The second mode is as follows:
first, the power-on times of the flash memory chip are acquired.
And then, determining and recording the block address of the Nor flash array block in the physical storage array based on the power-on times.
Note that the block address of the first or last Nor flash array block for performing the disturb determination and correction is recorded in the present application.
In the specific implementation, if the recorded block address of the first Nor flash array block is recorded, during subsequent erasing operation, after the block address of the first Nor flash array block is obtained, 1 is automatically added when the block address of the second Nor flash array block is obtained, and the like until the erasing operation is finished.
In the specific implementation, if the block address of the last Nor flash array block is recorded, when the subsequent erasing operation is performed, 1 is automatically added to obtain the block address of the first Nor flash array block required by the current erasing operation, and so on until the current erasing operation is finished, and the block address of the last Nor flash array block is continuously recorded.
S902: when block erasing operation is carried out for multiple times, each block erasing operation only carries out interference confirmation and correction on the Nor flash array block corresponding to one block address.
In S902, each Nor flash array block performs interference confirmation and correction only once before performing interference confirmation and correction on all Nor flash array blocks.
For example, the physical memory array includes 16 Nor flash array blocks, and when one of the Nor flash array blocks is subjected to a block erase operation, according to the arrangement order of the block addresses of the remaining Nor flash array blocks, if the Nor flash array block subjected to the interference confirmation and correction in the previous time is the 6 th one, the interference confirmation and correction are performed on the 7 th Nor flash array block under the condition that the selected Nor flash array block is not the 7 th Nor flash array block. And if the 7 th Nor flash array block is selected, sequentially carrying out interference confirmation and correction on the 8 th Nor flash array block. In this way, it can be ensured that 16 Nor flash array blocks in the physical memory array are verified and corrected at least once by disturb in 16 block erase cycles.
According to the Nor flash erase interference correction method provided by the embodiment of the invention, based on the block address arrangement sequence of all Nor flash array blocks in the predetermined physical storage array, when multiple block erase operations are carried out, interference confirmation and correction are only carried out on the Nor flash array block corresponding to one block address in each block erase operation. In the scheme, the Nor flash array blocks needing interference confirmation and correction are confirmed in different modes, so that interference confirmation and correction on all other remaining Nor flash array blocks in the physical storage array in each block erasing operation can be avoided, and the aims of reducing time consumed by erasing interference confirmation and correction and reducing the power consumption of the whole erasing operation are fulfilled.
Based on the method for correcting the interference of the Nor flash erase, the embodiment of the invention also correspondingly discloses a corresponding device for correcting the interference of the Nor flash erase.
As shown in fig. 10, the Nor flash erase disturb correction apparatus 100 mainly includes:
the first correcting module 1001 is configured to, during a block erase operation performed on a Nor flash array block of a non-volatile flash memory selected in a physical storage array, determine whether an operation for setting the Nor flash array block satisfies an interference confirmation condition, if so, perform interference confirmation and correction on all Nor flash array blocks in the physical storage array, and if not, continue the block erase operation.
And/or the presence of a gas in the gas,
a second correcting module 1002, configured to determine, during a block erase operation performed on a Nor flash array block selected in a physical storage array, a block address of the Nor flash array block to be processed based on cycle times of each flow in the block erase operation process recorded by a counter inside a flash memory chip, or determine the block address of the Nor flash array block to be processed based on a number of clock signals generated by any oscillator in the flash memory chip or a number of clock signals provided by an application system of the flash memory chip, which is recorded by the counter inside the flash memory chip; and based on the block address, performing interference confirmation and correction on the to-be-processed Nor flash array block corresponding to the block address.
And/or the presence of a gas in the gas,
the third correction module 1003 is used for acquiring block addresses of Nor flash array blocks in a pre-recorded physical storage array; when block erasing operation is carried out for multiple times, interference confirmation and correction are carried out on the Nor flash array block corresponding to one block address in each block erasing operation, wherein each Nor flash array block only carries out interference confirmation and correction once before interference confirmation and correction are carried out on all Nor flash array blocks.
The Nor flash erase disturbance correction device disclosed in the embodiment of the present invention may include the three correction modules at the same time, or may include any combination of the three correction modules.
If the Nor flash erase disturb correction apparatus includes the third correction module 1003, the apparatus may further include an arrangement module, where the arrangement module is configured to record block addresses of all Nor flash array blocks in the physical memory array in advance in sequence.
The arranging module is optionally specifically used for acquiring the block address of the selected Nor flash array block for interference confirmation and correction when the selected Nor flash array block is erased in the physical storage array each time; and sequentially arranging and recording the block addresses of the selected Nor flash array blocks for interference confirmation and correction according to the acquisition sequence.
The arrangement module is optional and is specifically used for acquiring the power-on times of the flash memory chip; and determining and recording the arrangement sequence of the block addresses of each Nor flash array block in the physical storage array based on the power-on times.
It should be noted that, the first correction module 1001 is optionally specifically configured to perform interference confirmation on one or more Nor flash array blocks in the remaining Nor flash array blocks in the process of performing a block erase operation on a selected non-volatile flash Nor flash array block in the physical storage array; judging whether one or more data in one or more Nor flash array blocks in the rest Nor flash array blocks are rewritten; if yes, indicating that one or more norflash array blocks are rewritten, determining that a specific condition is met, and performing interference confirmation and correction on all the remaining norflash array blocks in the physical storage array; if not, the result shows that one or more of the data blocks are not rewritten, the situation that the specific conditions are not met is determined, and the block erasing operation is continued.
The first correction module 1001 is specifically configured to, optionally, record the number of times of block erase operations on a selected Nor flash array block in a physical storage array in a process of performing the block erase operations on the selected Nor flash array block; detecting whether the times are larger than a preset value or not, wherein the value range of the preset value comprises 1k to 100k; if so, determining that a specific condition is met, and performing interference confirmation and correction on all the remaining Nor flash array blocks in the physical storage array; if the specific condition is not met, the block erasing operation is continued.
It should be noted that the second correcting module 1002 is optionally specifically configured to, in the process of performing a block erase operation on a Nor flash array block selected in a physical storage array, record cycle times corresponding to any one of a pre-programming flow, a block erase flow, an over-erase automatic correction flow, and a soft programming flow based on a counter inside a flash memory chip; selecting the cycle number corresponding to any one of a pre-programming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow as a block address of the Nor flash array block to be processed; and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
The second correcting module 1002 is specifically configured to, optionally, record cycle times corresponding to any one of a pre-programming flow, a block erasing flow, an over-erase automatic correcting flow, and a soft programming flow based on a counter inside a flash memory chip in a process of performing a block erasing operation on a Nor flash array block selected in a physical storage array; calculating the sum of the cycle times corresponding to a plurality of or all of the procedures in the preprogramming procedure, the block erasing procedure, the over-erasing automatic correction procedure and the soft programming procedure as the block address of the Nor flash array block to be processed; and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
In the Nor flash erase interference correction device provided by the embodiment of the invention, whether the operation of setting the Nor flash array block meets the interference confirmation condition is judged in the process of performing block erase operation on the selected non-volatile flash Nor flash array block in the physical storage array, if so, interference confirmation and correction are performed on all Nor flash array blocks in the physical storage array, and if not, block erase operation is continued; or determining the block address of the Nor flash array block to be processed and performing corresponding interference confirmation and correction based on the cycle times of each flow in the block erasing operation process recorded by a counter in the flash chip, or based on the number of clock signals generated by any oscillator in the flash chip or the number of clock signals provided by an application system of the flash chip recorded by the counter in the flash chip; or, based on the block address arrangement sequence of all Nor flash array blocks in the predetermined physical storage array, when performing multiple block erase operations, each block erase operation only performs interference confirmation and correction on a Nor flash array block corresponding to one block address. In the scheme, the Nor flash array blocks needing interference confirmation and correction are confirmed in different modes, so that interference confirmation and correction on all other remaining Nor flash array blocks in the physical storage array in each block erasing operation can be avoided, and the aims of reducing time consumed by erasing interference confirmation and correction and reducing the power consumption of the whole erasing operation are fulfilled.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A Nor flash erase disturb correction method, the method comprising:
in the process of carrying out block erasing operation on a selected non-volatile flash Nor flash array block in a physical storage array, judging whether the operation of setting the Nor flash array block meets specific conditions, if so, carrying out interference confirmation and correction on all the remaining Nor flash array blocks in the physical storage array, and if not, continuing to carry out block erasing operation;
or, in the process of carrying out block erasing operation on the selected Nor flash array block in the physical storage array, determining the block address of the Nor flash array block to be processed based on the cycle times of each flow in the block erasing operation process recorded by a counter in the flash memory chip, or the number of clock signals generated by any oscillator in the flash memory chip or the number of clock signals provided by an application system of the flash memory chip;
based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address;
or acquiring block addresses of all Nor flash array blocks in a pre-recorded physical storage array;
when block erasing operation is carried out for multiple times, interference confirmation and correction are carried out on the Nor flash array block corresponding to one block address in each block erasing operation, wherein each Nor flash array block only carries out interference confirmation and correction once before interference confirmation and correction are carried out on all Nor flash array blocks.
2. The method of claim 1, wherein determining whether the operation for setting the Nor flash array block satisfies a specific condition during a block erase operation on a selected Nor flash array block of the non-volatile flash memory in the physical memory array comprises:
performing interference confirmation on one or more Nor flash array blocks in the rest Nor flash array blocks in the process of performing block erasing operation on the selected Nor flash array block of the nonvolatile flash memory in the physical storage array;
judging whether one or more data in one or more Nor flash array blocks in the rest Nor flash array blocks are rewritten;
if yes, determining that a specific condition is met;
if not, determining that the specific condition is not met.
3. The method of claim 1, wherein determining whether the operation for setting the Nor flash array block satisfies a specific condition during a block erase operation on a selected Nor flash array block of the non-volatile flash memory in the physical memory array comprises:
recording the times of block erasing operation of a selected Nor flash array block of a nonvolatile flash memory in a physical storage array in the process of performing the block erasing operation on the selected Nor flash array block;
detecting whether the times are larger than a preset value or not, wherein the value range of the preset value comprises 1k to 100k;
if so, determining that a specific condition is met;
if not, determining that the specific condition is not satisfied.
4. The method as claimed in claim 1, wherein determining the block address of the Nor flash array block to be processed based on the number of cycles of each flow in the block erase operation process recorded by the counter inside the flash memory chip during the block erase operation of the Nor flash array block selected from the physical memory array comprises:
in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, recording cycle times corresponding to any flow in a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip;
and selecting the cycle number corresponding to any one of a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow as the block address of the Nor flash array block to be processed.
5. The method as claimed in claim 1, wherein determining the block address of the Nor flash array block to be processed based on the number of cycles of each flow in the block erase operation process recorded by the counter inside the flash memory chip during the block erase operation of the Nor flash array block selected from the physical memory array comprises:
in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, recording cycle times corresponding to any flow in a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip;
and calculating the sum of the cycle times corresponding to a plurality of or all of the preprogramming flow, the block erasing flow, the over-erasing automatic correction flow and the soft programming flow to be used as the block address of the Nor flash array block to be processed.
6. The method as claimed in claim 1, wherein during the block erase operation of the selected Nor flash array block in the physical storage array, determining the block address of the Nor flash array block to be processed based on the number of clock signals generated by any oscillator in the flash memory chip or the number of clock signals provided by the flash memory chip application system recorded by the counter inside the flash memory chip comprises:
in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, a counter in a flash memory chip starts to record clock signals from power-on reset of the flash memory chip, and records the clock signals after the soft programming flow of the block erasing operation is finished, so that the number of the clock signals is obtained; or in the process of carrying out block erasing operation on a selected Nor flash array block in a physical storage array, a counter in the flash memory chip records clock signals from any flow of the block erasing operation, and records the clock signals at any flow of the block erasing operation to obtain the number of the clock signals;
taking the clock signal quantity as the block address of the Nor flash array block to be processed;
the clock signal includes any clock signal inside the flash memory chip, or a clock signal input outside the flash memory chip.
7. The method of claim 1, wherein the pre-recording block addresses of Nor flash array blocks in the physical storage array comprises:
and acquiring and recording the block address of the selected Nor flash array block for interference confirmation and correction when the selected Nor flash array block is erased in the physical storage array each time.
8. The method of claim 1, wherein the pre-recording of block addresses of Nor flash array blocks in the physical memory array comprises:
acquiring the power-on times of a flash memory chip;
and determining and recording the block address of the Nor flash array block in the physical storage array based on the power-on times.
9. An Nor flash erase disturb correction apparatus, the Nor flash erase disturb correction apparatus comprising:
the first correction module is used for judging whether the operation of setting the Nor flash array block meets an interference confirmation condition or not in the process of carrying out block erasing operation on the Nor flash array block of the nonvolatile flash memory selected in the physical storage array, if so, carrying out interference confirmation and correction on all the residual Nor flash array blocks in the physical storage array, and if not, continuing carrying out block erasing operation; and/or the presence of a gas in the gas,
the second correction module is used for determining the block address of the Nor flash array block to be processed based on the cycle times of each flow path in the block erasing operation process recorded by a counter in the flash memory chip in the process of performing the block erasing operation on the Nor flash array block selected in the physical storage array, or determining the block address of the Nor flash array block to be processed based on the number of clock signals generated by any oscillator in the flash memory chip or the number of clock signals provided by an application system of the flash memory chip recorded by the counter in the flash memory chip; based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address; and/or the presence of a gas in the atmosphere,
the third correction module is used for acquiring the block address of the Nor flash array block in the pre-recorded physical storage array; when block erasing operation is carried out for multiple times, interference confirmation and correction are carried out on the Nor flash array block corresponding to one block address in each block erasing operation, wherein each Nor flash array block only carries out interference confirmation and correction once before interference confirmation and correction are carried out on all Nor flash array blocks.
10. The apparatus of claim 9, wherein the second correcting module is specifically configured to record, based on a counter inside the flash memory chip, a number of cycles corresponding to any one of a pre-programming flow, a block erase flow, an over-erase auto-correction flow, and a soft programming flow during a block erase operation performed on a selected Nor flash array block in the physical memory array; selecting the cycle number corresponding to any one of a preprogramming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow as the block address of the Nor flash array block to be processed; based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address;
or recording the cycle times corresponding to any flow in a pre-programming flow, a block erasing flow, an over-erasing automatic correction flow and a soft programming flow based on a counter in a flash memory chip in the process of carrying out block erasing operation on the selected Nor flash array block in the physical storage array; calculating the sum of the cycle times corresponding to a plurality of or all of the procedures in the pre-programming procedure, the block erasing procedure, the over-erasing automatic correction procedure and the soft programming procedure to be used as the block address of the Nor flash array block to be processed; and based on the block address, performing interference confirmation and correction on the Nor flash array block to be processed corresponding to the block address.
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