CN111627366B - Display panel and detection method thereof - Google Patents
Display panel and detection method thereof Download PDFInfo
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- CN111627366B CN111627366B CN202010461253.4A CN202010461253A CN111627366B CN 111627366 B CN111627366 B CN 111627366B CN 202010461253 A CN202010461253 A CN 202010461253A CN 111627366 B CN111627366 B CN 111627366B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
- H10K59/65—OLEDs integrated with inorganic image sensors
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Abstract
The invention provides a display panel, which can avoid waste caused by subsequent processes and improve the reliability of the panel by adding a detection circuit around a through hole region and connecting sub-pixels and judging whether cracks occur or not by observing the difference of the sub-pixels. When the control circuit inputs a control signal and turns on the detection thin film transistor. If the signals of the first metal wire and the second metal wire are not abnormal, the first data wire and the second data wire are in short circuit, the data signals of two rows of pixels are the same, and the same gray scale picture is displayed, the peripheral circuit of the through hole area is normal; if the signals of the first metal wire and the second metal wire are interrupted, the first data wire and the second data wire are not interfered with each other, the number of two rows of pixels and the signals are different, and different gray scale pictures are displayed, the peripheral circuit of the through hole area is abnormal, and the panel is scrapped.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a detection method of the display panel.
Background
The full-screen is one of the targets of OLED display technology development, and the camera technology under the screen can further improve the screen occupation ratio on the prior art level, reaches perfect full-screen design, and the camera technology is mainly through-hole, blind hole structure under the current screen. The through hole design needs to cut off all substrates in the camera area, and the risk that the cutting cracks extend to the wiring area in the panel to influence the reliability of the panel exists.
Disclosure of Invention
The invention aims to provide a display panel for detecting whether the periphery of a camera through hole area is broken or not and improving the reliability of the panel.
The invention provides a display panel, which comprises a display area and a through hole area surrounding the display area; the display area comprises a first data line and a second data line, and the first data line and the second data line are arranged on two sides of the through hole area; and arranging a detection thin film transistor at the edge of the through hole area, wherein the grid electrode of the detection thin film transistor is connected with a control circuit, and the source electrode and the drain electrode of the detection thin film transistor are respectively connected with the first data line and the second data line.
Furthermore, the grid electrode of the detection thin film transistor is connected with the control circuit through a peripheral wire.
Further, the control circuit is integrated in a driving IC or a singlechip.
Further, the source electrode is connected with the first data line through a first metal line; and the drain is connected with the second data line through a second metal line.
Further, the first metal line is arranged between the first data line and the through hole region; the second metal line is arranged between the second data line and the through hole area.
Furthermore, the first metal line and the second metal line are respectively arranged on two sides of the through hole region.
Further, the detection thin film transistor is arranged in a dielectric layer of the display panel.
Furthermore, the first metal wire is connected with the first data wire in one or more layers of a grid layer, a source drain layer or an anode layer of the display panel through wiring; the second metal wire is connected with the second data wire in one or more layers of a grid layer, a source drain layer or an anode layer of the display panel through wiring.
Furthermore, the peripheral wires are wired in one or more layers of a grid layer, a source drain layer or an anode layer of the display panel and connected with the control circuit.
The invention also provides a detection method of the display panel, which comprises the following steps: providing the display panel; inputting a control signal through the control circuit and turning on the detection thin film transistor; if the signals of the first metal wire and the second metal wire are not abnormal, the first data wire and the second data wire are in short circuit, the data signals of two rows of pixels are the same, and the same gray scale picture is displayed, the peripheral circuit of the through hole area is normal; if the signals of the first metal wire and the second metal wire are interrupted, the first data wire and the second data wire are not interfered with each other, the data signals of two rows of pixels are different, and different gray scale pictures are displayed, the peripheral circuit of the through hole area is abnormal.
The invention has the beneficial effects that: the invention provides a display panel, which can avoid waste caused by subsequent processes and improve the reliability of the panel by adding a circuit design around a through hole region and connecting sub-pixels and judging whether cracks occur or not by observing the difference of the sub-pixels.
Drawings
The invention is further described below with reference to the figures and examples.
FIG. 1 is a schematic plan view of a display panel according to the present invention;
FIG. 2 is a circuit diagram of a display panel detection circuit according to the present invention;
FIG. 3 is a schematic structural diagram of a display panel according to the present invention;
a display panel 100; a display area 110; a via region 120;
a first data line 101; a second data line 102; a detection thin film transistor 103;
a first metal line 104; a second metal line 105; a peripheral trace 106;
a substrate 201; a buffer layer 202; a dielectric layer 203;
an anode layer 204; a semiconductor layer 211; a first gate electrode 212;
a second gate 213; source drain layer 214.
Detailed Description
In order that the present invention may be better understood, the following examples are included to further illustrate the invention, but not to limit its scope.
The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms used in the present invention, such as "" up "" and "" down "" and "" front "" and "" back "", are used in the present invention,
The terms "left", "right", "top", "bottom", etc., refer to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.
As shown in fig. 1 and 2, the present invention provides a display panel 100, which includes a display area 110 and a through hole area 120, wherein the display area 110 surrounds the through hole area 120.
The display area 110 includes a first data line 101 and a second data line 102, and the first data line 101 and the second data line 102 are disposed on two sides of the through hole area 120.
When routing, the first data line 101 and the second data line 102 are semicircular on both sides of the through hole area 120, which is because the through hole area 120 is provided with a through hole, and the routing needs to avoid the through hole.
The first data line 101 and the second data line 102 are connected to corresponding sub-pixels, and the first data line 101 and the second data line 102 may be adjacent data lines or spaced data lines.
A detection thin film transistor 103 is disposed at the edge of the through hole region 120, a gate of the detection thin film transistor 103 is connected to a control circuit, and a source and a drain of the detection thin film transistor 103 are respectively connected to the first data line 101 and the second data line 102.
The gate of the detecting thin film transistor 103 is connected to the control circuit through a peripheral trace 106.
The control circuit is integrated in the drive IC or the singlechip.
The source is connected with the first data line 101 through a first metal line 104; the drain is connected to the second data line 102 through a second metal line 105.
The first metal line 104 is disposed between the first data line 101 and the via region 120; the second metal line 105 is disposed between the second data line 102 and the via region 120.
The first metal line 104 and the second metal line 105 are respectively disposed on two sides of the via region 120.
The invention arranges a detection circuit around the through hole area 120, when the control circuit inputs a control signal and turns on the detection thin film transistor 103. If the signals of the first metal line 104 and the second metal line 105 are not abnormal, the first data line 101 and the second data line 102 are short-circuited, the data signals of two columns of pixels are the same, and the same gray scale picture is displayed, then the peripheral circuit of the through hole area 120 is normal; if the signals of the first metal line 104 and the second metal line 105 are interrupted, the first data line 101 and the second data line 102 are not interfered with each other, the number of two rows of pixels and the signals are different, and different gray scale pictures are displayed, the peripheral circuit of the through hole area 120 is abnormal, and the panel is scrapped.
As shown in fig. 3, the cross-sectional layered structure of the display panel 100 includes: a substrate 201, a buffer layer 202, a dielectric layer 203, and an anode layer 204.
The buffer layer 202 is disposed on the substrate 201. The dielectric layer 203 is disposed on the buffer layer 202, and the anode layer 204 is disposed on the dielectric layer 203.
The detection thin film transistor 103 is disposed in a dielectric layer of the display panel 100. The cross-sectional structure of the detection thin film transistor 103 includes: a semiconductor layer 211, a first gate electrode 212, a second gate electrode 213, and a source/drain layer 214.
The dielectric layer 203 includes: a first gate insulating layer 2031, a second gate insulating layer 2032, an interlayer insulating layer 2033, and a planarization layer 2034.
The semiconductor layer 211 is arranged on one side of the buffer layer 202 far away from the substrate 201; the material of the semiconductor layer 211 is polysilicon or monocrystalline silicon.
The first gate insulating layer 2031 is disposed on the buffer layer 202 and the semiconductor layer 211; the first gate insulating layer 2031 mainly functions to insulate between adjacent metal layers.
The first gate electrode 212 is disposed on a side of the first gate insulating layer 2031 away from the buffer layer 202; the second gate insulating layer 2032 is disposed on the first gate electrode 212 and the first gate insulating layer 2031; the second gate 213 is disposed on a side of the second gate insulating layer 2032 away from the first gate insulating layer 2031.
The interlayer insulating layer 2033 is disposed on the second gate insulating layer 2032 and the second gate electrode 213; the source/drain layer 214 is disposed on a side of the interlayer insulating layer 2033 away from the second gate insulating layer 2032.
The planarization layer 2034 is disposed on the source/drain layer 214 and the interlayer insulating layer 2033.
The anode layer 204 is disposed on a side of the dielectric layer 203 away from the buffer layer 202 and connected to the dielectric layer 203.
The pixel defining layer 105 is disposed on the anode layer 204 and the dielectric layer 203, wherein the pixel defining layer 205 has an opening 206, and the anode layer 204 is exposed in the slot 206.
The first metal line 104 is connected to the first data line through one or more of a gate layer (the first gate 212 or the second gate 213), a source drain layer 214, or an anode layer 204 of the display panel 100.
Specifically, the first metal line 104 is routed through a gate layer of the display panel 100; or, the first metal line 104 is routed through the source drain layer 214 of the display panel 100; alternatively, the first metal line 104 is routed through the anode layer 204 of the display panel 100; or, the first metal line 104 is routed to the source drain layer 214 through a gate layer wire changing; or, the first metal line 104 is routed to the anode layer 204 through a gate layer wire change; or, the first metal line 104 is routed to the anode layer 204 through the source/drain layer 214; alternatively, the first metal line 104 is routed to the source/drain layer 214 through the gate layer and then to the anode layer 204.
The second metal line 105 is connected to the second data line 102 through wiring in one or more of the gate layer, the source/drain layer 214, or the anode layer 204 of the display panel.
Specifically, the second metal line 105 is routed through a gate layer of the display panel 100; or, the second metal line 105 is routed through the source drain layer 214 of the display panel 100; or, the second metal line 105 is routed through the anode layer 204 of the display panel 100; or, the second metal line 105 is routed to the source drain layer 214 through a gate layer wire changing; or, the second metal line 105 is routed to the anode layer 204 through a gate layer wire change; alternatively, the second metal line 105 is routed to the anode layer 204 through the source/drain layer 214. Alternatively, the second metal line 105 is routed to the source/drain layer 214 through the gate layer and then to the anode layer 204.
The peripheral trace 106 is connected to the control circuit by one or more traces of the gate layer, the source/drain layer 214, or the anode layer 204 of the display panel 100.
The peripheral trace 106 is connected to the control circuit by being wired in one or more of the gate layer, the source/drain layer 214, or the anode layer 204 of the display panel 100.
The peripheral wires 106 are routed through a gate layer of the display panel 100; or, the peripheral trace 106 is routed through the source drain layer 214 of the display panel 100; or, the peripheral trace 106 is routed through the anode layer 204 of the display panel 100; or, the peripheral trace 106 is routed to the source drain layer 214 through the gate layer; or, the peripheral trace 106 is routed to the anode layer 204 by a gate layer wire change; alternatively, the peripheral trace 106 is routed to the anode layer 204 by rerouting through the source/drain layer 214. Alternatively, the peripheral trace 106 is routed to the source/drain layer 214 through the gate layer and then routed to the anode layer 204.
The invention also provides a detection method of the display panel, which comprises the following steps:
s1, providing the display panel 100.
S2, inputting a control signal through the control circuit and turning on the detection thin film transistor 103.
If the signals of the first metal line 104 and the second metal line 105 are not abnormal, the first data line 101 and the second data line 102 are short-circuited, the data signals of two columns of pixels are the same, and the same gray scale picture is displayed, then the peripheral circuit of the through hole area 120 is normal; the step S3 is performed.
If the signals of the first metal line 104 and the second metal line 105 are interrupted, the first data line 101 and the second data line 102 are not interfered with each other, the data signals of two rows of pixels are different, and different gray-scale pictures are displayed, the peripheral circuit of the through hole area 120 is abnormal, and if cracks are determined around the through hole, the panel is scrapped.
S3, bending the panel and setting the cover plate.
S4, performing the operation of the step S2 to monitor the circuit, and if the circuit is normal, discharging the goods; if the circuit is abnormal, the panel is scrapped.
It should be noted that many variations and modifications of the embodiments of the present invention fully described are possible and are not to be considered as limited to the specific examples of the above embodiments. The above examples are given by way of illustration of the invention and are not intended to limit the invention. In conclusion, the scope of the present invention should include those changes or substitutions and modifications which are obvious to those of ordinary skill in the art.
Claims (8)
1. A display panel includes a display area and a via area surrounding the display area;
the display area comprises a first data line and a second data line, and the first data line and the second data line are arranged on two sides of the through hole area;
arranging a detection thin film transistor at the edge of the through hole area, wherein the grid electrode of the detection thin film transistor is connected with a control circuit, and the source electrode and the drain electrode of the detection thin film transistor are respectively connected with the first data line and the second data line;
the source electrode is connected with the first data line through a first metal line; the first metal wire is arranged between the first data wire and the through hole area;
the drain is connected with the second data line through a second metal line; the second metal line is arranged between the second data line and the through hole area.
2. The display panel according to claim 1,
and the grid electrode of the detection thin film transistor is connected with the control circuit through a peripheral wire.
3. The display panel according to claim 1,
the control circuit is integrated in the drive IC or the singlechip.
4. The display panel according to claim 1,
the first metal wire and the second metal wire are respectively arranged on two sides of the through hole area.
5. The display panel according to claim 1,
the detection thin film transistor is arranged in a dielectric layer of the display panel.
6. The display panel according to claim 4,
the first metal wire is connected with the first data wire in one or more layers of a grid layer, a source drain layer or an anode layer of the display panel through wiring;
the second metal wire is connected with the second data wire in one or more layers of a grid layer, a source drain layer or an anode layer of the display panel through wiring.
7. The display panel according to claim 2, further comprising:
the peripheral wires are wired in one or more layers of a grid layer, a source drain layer or an anode layer of the display panel and are connected with the control circuit.
8. A method for detecting a display panel, comprising:
providing a display panel according to any one of claims 1 to 7;
inputting a control signal through the control circuit and turning on the detection thin film transistor;
if the signals of the first metal wire and the second metal wire are not abnormal, the first data wire and the second data wire are in short circuit, the data signals of two rows of pixels are the same, and the same gray scale picture is displayed, the peripheral circuit of the through hole area is normal;
if the signals of the first metal wire and the second metal wire are interrupted, the first data wire and the second data wire are not interfered with each other, the data signals of two rows of pixels are different, and different gray scale pictures are displayed, the peripheral circuit of the through hole area is abnormal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010461253.4A CN111627366B (en) | 2020-05-27 | 2020-05-27 | Display panel and detection method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010461253.4A CN111627366B (en) | 2020-05-27 | 2020-05-27 | Display panel and detection method thereof |
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| CN111627366A CN111627366A (en) | 2020-09-04 |
| CN111627366B true CN111627366B (en) | 2022-07-12 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102601650B1 (en) * | 2016-07-26 | 2023-11-13 | 삼성디스플레이 주식회사 | Display device |
| CN110503907B (en) * | 2018-05-17 | 2024-04-05 | 京东方科技集团股份有限公司 | Display panel, crack detection method thereof and display device |
| KR102465374B1 (en) * | 2018-09-12 | 2022-11-10 | 삼성디스플레이 주식회사 | Display panel and display device including thereof |
| KR102583232B1 (en) * | 2018-11-02 | 2023-09-26 | 삼성디스플레이 주식회사 | Display device and inspecting method thereof |
| KR102572345B1 (en) * | 2018-11-15 | 2023-08-29 | 삼성디스플레이 주식회사 | Display device and inspecting method thereof |
| CN209216456U (en) * | 2019-01-31 | 2019-08-06 | 昆山国显光电有限公司 | Display panel |
| CN109901747B (en) * | 2019-02-26 | 2022-03-11 | 上海天马微电子有限公司 | Display panel and display device |
| CN110264891B (en) * | 2019-07-18 | 2022-02-01 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111106151B (en) * | 2019-12-09 | 2022-07-29 | 武汉华星光电半导体显示技术有限公司 | Electronic device with a detachable cover |
| CN111128064B (en) * | 2020-01-21 | 2023-05-26 | 京东方科技集团股份有限公司 | Detection circuit and display panel |
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