CN111626008B - Layered sequential testability modeling method for circuit system - Google Patents

Layered sequential testability modeling method for circuit system Download PDF

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CN111626008B
CN111626008B CN202010464342.4A CN202010464342A CN111626008B CN 111626008 B CN111626008 B CN 111626008B CN 202010464342 A CN202010464342 A CN 202010464342A CN 111626008 B CN111626008 B CN 111626008B
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陈岑
叶雪荣
杨赟
王浩南
胡义凡
翟国富
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Harbin Institute of Technology
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Abstract

The invention aims to provide a layered sequential testability modeling method for a circuit system, belonging to the field of testability analysis and design of electronic products. Firstly, determining a fault set and an available physical measurement point set of a circuit system, and determining a fault information propagation path in the circuit system by establishing a multi-signal flow diagram model; constructing a shortest path matrix from a fault to a measuring point by taking the fault information propagation path as a basis; then, determining the usability sequencing of the measuring points by taking the information entropy as a basis; simulating to obtain the waveform of the electric signal of the measuring point under each fault state; extracting the available characteristics of each measuring point according to the determined priority sequence, and sequentially supplementing to form a fault-test characteristic matrix; and verifying the sufficiency of the matrix after each supplement until the specified requirements are met, and giving a required testability model. The invention solves the problem of measuring point availability evaluation and judgment of the termination time of sequential augmentation modeling in testability modeling, and provides an effective means for testability modeling of a circuit system.

Description

Layered sequential testability modeling method for circuit system
Technical Field
The invention relates to a layered sequential testability modeling method for a circuit system, and belongs to the field of testability analysis and design of electronic products.
Background
With the increasing integration of circuit systems, the number of potential faults and the types of faults thereof also increase remarkably. For a complex circuit system, the fault feature mining analysis of the device level is carried out on each fault independently, so that a great deal of test expense and time cost are undoubtedly wasted. More importantly, the simple integration of the fault characteristics of each device does not take into account the potential similarity of the response of the characteristics to different faults. In this case, a fault occurrence is likely to cause response abnormality of corresponding features of other faults, so that a real fault cannot be located. Therefore, the comprehensive diagnosis technology of the system is developed, and the diagnosis problem is solved by combining a device fault model and the online monitoring technology on the premise of comprehensively considering factors such as research and test cost, fault diagnosis effect, reliability, maintainability and the like. The basis of the comprehensive diagnosis technology of the system is to establish a definite mapping relation between a fault set and each test characteristic, namely a testability modeling technology.
The testability model usually represents the mapping relationship between the fault and the test in a boolean Matrix (Dependency Matrix, also called D Matrix), and the currently common modeling methods can be summarized as graph theory-based modeling methods and simulation-based modeling methods. The testability modeling method based on the graph theory idea describes the physical connection and propagation path relation between a fault and a test in a directed graph mode, and the widely applied method at present comprises a correlation model proposed by R.De Paul; the information flow model proposed by shepard; the model of the multiple signal flow graph proposed by pattipiti. The models are mainly suitable for systems with clear function levels and modular structures. The quantitative modeling method based on the simulation technology has accurate fault simulation and feature mining capabilities and is beneficial to solving the difficult problem of testability modeling of a circuit system. However, the original data and test dimension explosion problems of the simulation-based modeling method are only suitable for small-scale integrated systems. For a circuit system with the characteristics of large scale, high integration and nonlinearity, the problem of testability modeling cannot be solved by singly using a graph theory or a simulation method. By combining the advantages of simple and visual form of a graph theory method and the advantage of quantitative mining of fault information facilitated by a simulation technology, the modeling efficiency is considered on the premise of ensuring model simplicity, and the problem of difficult testability modeling of a circuit system can be effectively solved.
Disclosure of Invention
The invention provides a layered sequential testability modeling method integrating graph theory and simulation technology, aiming at solving the problem of difficulty in testability modeling of a circuit system.
The invention relates to a layered sequential testability modeling method for a circuit system, which comprises the following steps:
the method comprises the following steps: according to the composition, the functional characteristics and the historical fault information of the circuit system, determining a fault set F with the dimension m, which is caused by component failure or faults, of the circuit system as F1,f2,…,fmAnd availability of capacity qTheory test point set ATP ═ { ATP1,atp2,…,atpqEstablishing a multi-signal flow graph model to determine an information propagation path of each fault;
step two: constructing a shortest path matrix SP from m faults to q measuring points based on the fault information propagation path established in the step one, wherein elements SP in the matrixijIndicating a fault fiTo measuring point atpjThe minimum number of directed edges that need to be experienced;
step three: calculating information entropy corresponding to each measuring point by adopting a fault information propagation attenuation model and combining the fault-measuring point shortest path matrix determined in the step two, wherein the information entropy is used for describing the complexity of fault information contained in each measuring point, and the availability priority sequence of the measuring points is determined in an ascending order of the information entropy;
step four: adopting circuit simulation software to establish a circuit system behavior model, and simulating and acquiring time domain voltage and current signal waveforms of each measuring point in the system under the fault state of each component;
step five: according to the priority ranking of the measuring points determined in the step three, the corresponding measuring points atp are sequentially rankedjThe waveform of the circuit system is subjected to time domain and frequency domain characteristic extraction according to the functional characteristics of the circuit system to obtain a corresponding characteristic set Featj＝{featj1,featj2,…,featjkChecking and determining whether the extracted k features can be used for detecting at least 1 type of faults in the m types of faults, reserving p features with detection capability, and enabling response modes of the p features to the various types of faults to be in an m multiplied by p matrix form DSupAdding to the failure-test feature matrix, test sets before and after addition being respectively TSubAnd [ TSub,TSup]The corresponding failure-test feature matrix is represented by DSubAnd [ D ]Sub,DSup]Each position element in the matrix represents whether a corresponding test (column) can detect a corresponding fault (row) by 1 and 0 respectively;
step six: after the operation of the step five is carried out on each measuring point, a Boolean fault-test characteristic matrix D obtained by supplementing the operationSubDetection sufficiency and isolation sufficiency index calculations are performed. If any of the above two indexes existsIf the index is smaller than the specified value, repeating the step five in sequence according to the priority sequence of the measuring points until the detected sufficiency index and the isolation sufficiency index are not smaller than the specified value, and obtaining a fault-test characteristic matrix D at the momentSubNamely a circuit system testability model meeting the requirements.
The invention has the advantages that: the invention provides a layered sequential testability modeling method for a circuit system, which has two characteristics of test point-characteristic layering and sequential augmentation compared with the prior art, wherein the testability modeling is layered into two layers of test point selection and test characteristic analysis, the priority ranking and the sensitive test characteristic analysis of the test points are respectively realized by utilizing the respective characteristics of a graph theory and a simulation technology, and the sequential modeling mode is adopted, so that the waste of high-dimensional modeling resources is avoided, and the efficiency and the effect of the testability modeling of the large-scale, high-integration and nonlinear circuit system are considered. The invention provides a measuring point priority ordering method adopting a fault information propagation attenuation model and an information entropy on the basis of the existing multi-signal flow graph modeling, and solves the problem of measuring point availability evaluation in testability modeling. Meanwhile, the invention provides two quantitative indexes of detection sufficiency and isolation sufficiency and a calculation method thereof aiming at the supplement testability model matrix, and the quantitative indexes can be used for evaluating the sufficiency level of the matrix, thereby solving the problem of judging the termination time of sequential supplement modeling.
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FIG. 1 is a flow chart of a method for hierarchical sequential testability modeling of a circuit system in accordance with the present invention.
Fig. 2 is a flow chart of the Floyd-Warshall algorithm for shortest path matrix construction according to the present invention.
FIG. 3 is a flow chart of an algorithm for testability model sufficiency calculation according to the present invention.
Fig. 4 is a block diagram of a switching power supply circuit system topology according to one embodiment of the present invention.
Fig. 5 is a multi-signal flow diagram model of a switching power supply circuit system of the present invention.
Detailed Description
The first embodiment is as follows:
the present embodiment is described below with reference to fig. 1 to 3, and the present embodiment describes a hierarchical sequential testability modeling method for a circuit system, which includes the following steps:
the method comprises the following steps: according to the composition, the functional characteristics and the historical fault information of the circuit system, determining a fault set F with the dimension m, which is caused by component failure or faults, of the circuit system as F1,f2,…,fmAnd the available physical measurement point set of capacity q ATP ═ ATP1,atp2,…,atpqEstablishing a multi-signal flow graph model to determine an information propagation path of each fault;
step two: based on the fault information propagation path established in the step one, a shortest path matrix SP from m faults to q measuring points is established by using a Floyd-Warshall algorithm, and elements SP in the matrixijIndicating a fault fiTo measuring point atpjThe minimum number of directed edges that need to be traversed, as shown in FIG. 2;
step three: and (4) calculating information entropy corresponding to each measuring point by adopting a fault information propagation attenuation model and combining the fault-measuring point shortest path matrix determined in the step two, wherein the information entropy is used for describing the complexity of fault information contained in each measuring point, and the availability priority sequence of the measuring points is determined in an ascending order of the information entropy. Measuring point atp of fault information propagation attenuation modeljInformation entropy S (atp)j) The calculation method comprises the following steps:
Figure GDA0003319401080000031
wherein m ispThe representation can be propagated to atpjNumber of fault classes of PFEqual probability fault rate, p, representing m types of faultsmaxFor the longest path among the circuit system fault information propagation paths established in step three, S (atp)j|fi) Denotes fiSpread to atpjEntropy of time-induced information, and shortest propagation path spijThe relationship is defined as follows:
S(atpj|fi)＝log2(spij+1) (2)
step four: adopting circuit simulation software to establish a circuit system behavior model, and simulating and acquiring time domain voltage and current signal waveforms of each measuring point in the system under the fault state of each component;
step five: according to the priority ranking of the measuring points determined in the step three, the corresponding measuring points atp are sequentially rankedjThe waveform of the circuit system is extracted according to the functional characteristics of the circuit system to obtain a corresponding characteristic set Featj＝{featj1,featj2,…,featjkChecking and determining whether the extracted k features can be used for detecting at least 1 type of faults in the m types of faults, reserving p features with detection capability, and enabling response modes of the p features to the various types of faults to be in an m multiplied by p matrix form DSupAdding to the failure-test feature matrix, test sets before and after addition being respectively TSubAnd [ TSub,TSup]The corresponding failure-test feature matrix is represented by DSubAnd [ D ]Sub,DSup]Each position element in the matrix respectively represents whether a corresponding test (column) can detect a corresponding fault (row) by 1 and 0, wherein 1 represents that the corresponding test can detect the corresponding fault, and 0 represents that the corresponding test cannot detect the corresponding fault;
step six: after the operation of the step five is carried out on each measuring point, a Boolean fault-test characteristic matrix D obtained by supplementing the operationSubDetection sufficiency and isolation sufficiency index calculations are performed. If any index in the two indexes is smaller than the specified value, repeating the step five in sequence according to the priority sequence of the measuring points until the detected sufficiency index and the isolation sufficiency index are not smaller than the specified value, and obtaining a fault-test feature matrix D at the momentSubNamely a circuit system testability model meeting the requirements. The flow is shown in fig. 3.
The detection sufficiency and isolation sufficiency in the above flow are defined as follows:
detection of sufficiency: for a given test set TSubTo fault fiCan utilize the detected sufficiency of the responsiveness fiQuantitative evaluation of test quantity of, TSubAdequacy of detection of global failure set IFDUsing detected sufficiency indicators corresponding to each faultThe minimum value is constrained.
Isolation sufficiency: fault fiFor fault fkIsolatability depends on a given test set TSubTest quantity with different response results, using iFI(Fik,TSub) And (4) showing. Then failure fiThe overall isolatability to the remaining faults can be determined byFI(Fik,TSub) Constraint of minimum value of (1), TSubIsolation sufficiency for Overall Fault set IFIAnd the minimum value of the overall isolability indexes corresponding to the faults can be used for constraint.
The calculation methods of the two indexes are respectively as follows:
IFD(TSub)＝min(Card({tj∈TSub,tij＝1}),i＝1,2,…,m) (3)
Figure GDA0003319401080000041
wherein, IFDAnd IFIThe Card function represents the number of elements in a given set that meet the requirements, for pick sufficiency and isolation sufficiency indices, respectively.
Constructing a matrix Suf store i of (m +1) × (m +1) dimensionsFI(Fik,TSub) As a result, Suf matrix row ith column jth corresponds to storage iFI(Fik,TSub) As a result, when the test set T is in the original test setSubSupplement test set T on the basisSupThen, all i can be calculated using the following formulaFI(Fik,TSup) As a result, and Suf (i, k) ═ Suf (i, k) + iFI(Fik,TSup) Suf matrix is updated. Using the Suf matrix, the pick sufficiency and isolate sufficiency test can be expressed as:
Figure GDA0003319401080000051
the specified values of the detection sufficiency index and the isolation sufficiency index in the flow are respectively represented by IFD_ThreAnd IFI_ThreAnd (4) showing.
The second embodiment is as follows:
this embodiment mode will be described below with reference to fig. 1 to 5, and the first embodiment mode will be further described in this embodiment mode. In the embodiment, a hierarchical sequential testability modeling is performed by taking a certain type of switching power supply circuit system as an object, and the method specifically comprises the following steps:
in step one, the failure set in the certain type of switching power supply circuit system is shown in table 1, and the corresponding available physical measuring point positions are shown as atp in fig. 41～atp17As shown.
TABLE 1 Fault set of switching power supply circuit system
Figure GDA0003319401080000052
In step two, for 14 types of faults and 17 available physical measurement points of a certain type of switching power supply circuit system, a shortest path matrix SP constructed by using the Floyd-Warshall algorithm according to the multi-signal flow graph model shown in fig. 5 is shown in table 2.
TABLE 2A certain type of switch power supply circuit system fault-measuring point shortest path matrix
Figure GDA0003319401080000053
Figure GDA0003319401080000061
In step three, P is selected according to historical fault conditions F1%, the 17 available physical measuring points atp are calculated in sequence from the formula (1)1～atp17The entropy of the information, the usable sequence of the measuring points determined by ascending sequence is shown in table 3.
TABLE 3 physical Point sequencing
Figure GDA0003319401080000062
In the fourth step to the sixth step, a simulation model of a certain type of switching power supply circuit system is established in Saber software, and the single-period lowest value V of the waveform of the periodic voltage signal is selected according to the self characteristics of the certain type of switching power supply circuit systemlMaximum value VhPeak to peak value VpkHigh-level duty ratio DutyH, low-level duty ratio DutyL, and amplitude Amp of frequency fp point after Fourier transform@fpAnd the test characteristics are used as corresponding test points. When the sufficiency test is performed in the sixth step, the index I is required to be specifiedFD_ThreAnd IFI_ThreThe numerical value of (c). In this step, IFD_ThreAnd IFI_ThreThe value of (1) is at least, a testability model meeting the requirements can be established by using the measuring points of the first 3 bits of the sequence under the specified condition, the model result, namely the fault-test characteristic matrix is shown in a table 4, and the test characteristics of the corresponding physical measuring points are shown in a table 5.
TABLE 4IFD_ThreAnd IFI_ThreFailure-test feature matrix with respective value of 1
Figure GDA0003319401080000063
Figure GDA0003319401080000071
TABLE 5IFD_ThreAnd IFI_ThreSelected physical measurement points and corresponding characteristics thereof when the values are 1 respectively
Figure GDA0003319401080000072

Claims (4)

1. A method for hierarchical sequential testability modeling of a circuit system, comprising the steps of:
the method comprises the following steps: according to the composition and work of the circuit systemEnergy characteristics and historical fault information, and determining a fault set F with the dimension m caused by component failure or fault1,f2,…,fmAnd the available physical measurement point set of capacity q ATP ═ ATP1,atp2,…,atpqEstablishing a multi-signal flow graph model to determine an information propagation path of each fault;
step two: constructing a shortest path matrix SP from m faults to q measuring points based on the fault information propagation path established in the step one, wherein the ith row and the jth column of elements SP in the matrixijIndicating a fault fiTo measuring point atpjThe minimum number of directed edges that need to be experienced;
step three: calculating information entropy corresponding to each measuring point by adopting a fault information propagation attenuation model and combining the fault-measuring point shortest path matrix determined in the step two, wherein the information entropy is used for describing the complexity of fault information contained in each measuring point, and the availability priority sequence of the measuring points is determined in an ascending order of the information entropy;
step four: adopting circuit simulation software to establish a circuit system behavior model, and simulating and acquiring time domain voltage and current signal waveforms of each measuring point in the system under the fault state of each component;
step five: according to the priority ranking of the measuring points determined in the step three, the corresponding measuring points atp are sequentially rankedjThe waveform of the circuit system is subjected to time domain and frequency domain characteristic extraction according to the functional characteristics of the circuit system to obtain a corresponding characteristic set Featj＝{featj1,featj2,…,featjkChecking and determining whether the extracted k features can be used for detecting at least 1 type of faults in the m types of faults, reserving p features with detection capability, and enabling response modes of the p features to the various types of faults to be in an m multiplied by p matrix form DSupAdding to the failure-test feature matrix, the test feature sets before and after the addition being respectively TSubAnd [ TSub,TSup]The corresponding failure-test feature matrix is represented by DSubAnd [ D ]Sub,DSup]Each position element in the matrix respectively represents whether the corresponding test can detect the corresponding fault by 1 and 0;
step six: the operation of the step five is carried out on each measuring pointThen, the obtained Boolean fault-testing characteristic matrix D is supplemented to the timeSubAnd calculating detection sufficiency and isolation sufficiency indexes, if any index in the two indexes is smaller than a specified value, sequentially repeating the step five according to the priority sequence of the measuring points until the detection sufficiency and the isolation sufficiency indexes are not smaller than the specified value, and obtaining a fault-test feature matrix D at the momentSubNamely a circuit system testability model meeting the requirements.
2. The method according to claim 1, wherein the shortest path matrix SP in the second step is constructed by using a Floyd-Warshall algorithm.
3. The method of claim 1, wherein the step three is based on the measured point atp of the fault information propagation attenuation modeljInformation entropy S (atp)j) The calculation method comprises the following steps:
Figure FDA0003319401070000011
wherein m ispThe representation can be propagated to atpjNumber of fault classes of PFEqual probability fault rate, p, representing m types of faultsmaxFor the longest path among the circuit system fault information propagation paths established in step three, S (atp)j|fi) Denotes fiSpread to atpjEntropy of time-induced information, and shortest propagation path spijThe relationship is defined as follows:
S(atpj|fi)＝log2(spij+1) (2)。
4. the method according to claim 1, wherein the detection sufficiency and isolation sufficiency indicators of the fault-test feature matrix in the sixth step are defined as:
detection of sufficiency: for a given test set TSubTo fault fiCan utilize the detected sufficiency of the responsiveness fiQuantitative evaluation of test quantity of, TSubAdequacy of detection of global failure set IFDThe minimum value in the detected sufficiency indexes corresponding to each fault can be used for carrying out constraint;
isolation sufficiency: fault fiFor fault fkIsolatability depends on a given test set TSubTest quantity with different response results, using iFI(Fik,TSub) Indicates, then fault fiThe overall isolatability to the remaining faults can be determined byFI(Fik,TSub) Constraint of minimum value of (1), TSubIsolation sufficiency for Overall Fault set IFIThe minimum value in the overall isolatable index corresponding to each fault can be used for constraint;
the calculation methods for detecting two indexes of sufficiency and isolation sufficiency are respectively shown as formula (3) and formula (4):
IFD(TSub)＝min(Card({tj∈TSub,tij＝1}),i＝1,2,…,m) (3)
Figure FDA0003319401070000021
wherein, IFDAnd IFIFor the detected sufficiency and isolated sufficiency indices, respectively, the Card function represents the number of elements in a given set that meet the requirements;
constructing a matrix Suf store i of (m +1) × (m +1) dimensionsFI(Fik,TSub) As a result, Suf matrix row jth column element corresponds to storage iFI(Fik,TSub) As a result, when the test set T is in the original test setSubSupplement test set T on the basisSupThen, all i can be calculated by the formula (4)FI(Fik,TSup) As a result, and Suf (i, k) ═ Suf (i, k) + iFI(Fik,TSup) Suf matrix is updated, and sufficiency is detected and isolated using Suf matrixThe performance index can be obtained by looking up the table in the way of equation (5):
Figure FDA0003319401070000022
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