CN111613577A - Array substrate preparation method and semi-transparent photomask - Google Patents
Array substrate preparation method and semi-transparent photomask Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
- G03F1/32—Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The embodiment of the application provides an array substrate preparation method and a semi-transparent photomask, wherein when the array substrate preparation method exposes a first light resistance layer, the semi-transparent photomask is adopted to expose the first light resistance layer, a first light resistance pattern can be remained in a channel region and a conductor region of an active layer, then the active layer is etched, and a second light resistance pattern can be continuously remained in the channel region of the active layer, so that the second light resistance pattern can protect the channel region of the active layer during subsequent film layer preparation, the channel region of the active layer is not damaged, the stability of a thin film transistor is improved, and the technical problem that the active layer is damaged in the existing liquid crystal display panel preparation method is solved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a method for manufacturing an array substrate and a semi-transparent mask.
Background
In the existing LCD (Liquid Crystal Display), the electrical stability of the tft may determine the Display quality of the Liquid Crystal Display panel, and in the tft, the existing manufacturing method is to form the tft by using back channel etching or etching barrier layer technology, but in the back channel etching technology, after the active layer is formed, the channel region of the active layer may be etched during the subsequent manufacturing of other film layers, so that the active layer may be incomplete, the stability of the tft may be affected, and the Display effect of the Liquid Crystal Display panel may be poor or the Liquid Crystal Display panel may not Display.
Therefore, the existing preparation method of the liquid crystal display panel has the technical problem of damaging the active layer.
Disclosure of Invention
The embodiment of the application provides an array substrate preparation method and a semi-transparent photomask, which are used for relieving the technical problem that an active layer is damaged in the existing liquid crystal display panel preparation method.
The embodiment of the application provides a preparation method of an array substrate, which comprises the following steps:
providing a substrate;
forming an active layer on the substrate;
coating a first photoresist layer on the active layer;
carrying out photoetching treatment on the first light resistance layer by adopting light to penetrate through a semi-transparent photomask to obtain a first light resistance pattern; the semi-transparent photomask comprises an opaque region, a semi-transparent region and a full-transparent region, wherein the light transmittance of the opaque region is less than that of the semi-transparent region, and the light transmittance of the semi-transparent region is less than that of the full-transparent region; the active layer comprises a channel region and a conductor region, the opaque region corresponds to the channel region, and the semi-transparent region corresponds to the conductor region; the first light resistance pattern comprises a first light resistance area corresponding to the light-tight area and a second light resistance area corresponding to the semi-light-permeable area, and the thickness of the first light resistance area is larger than that of the second light resistance area;
etching the active layer and the first photoresist pattern to obtain a second photoresist pattern and an active layer pattern; the second photoresist pattern is correspondingly arranged in the channel region;
forming a source drain layer on the active layer pattern and the second photoresist pattern;
coating a second light resistance layer on the source drain layer;
carrying out photoetching treatment on the second light resistance layer by adopting light to penetrate through a photomask to obtain a third light resistance pattern; the third light resistance pattern corresponds to the source drain electrode pattern of the source drain electrode layer;
and etching the source drain layer to obtain a source drain layer pattern.
In some embodiments, the step of performing a photolithography process on the first photoresist layer using a light-transmissive half-transmissive mask to obtain a first photoresist pattern includes:
aligning the semi-transparent photomask and the array substrate so that the opaque region corresponds to the channel region and the semi-transparent region corresponds to the conductor region;
and carrying out photoetching treatment on the first photoresist layer by adopting illumination to obtain a first photoresist pattern.
In some embodiments, a ratio of the thickness of the first photoresist region to the thickness of the second photoresist region ranges from one quarter to one half.
In some embodiments, the step of irradiating the first photoresist layer with light through a semi-transparent mask to obtain a first photoresist pattern includes: the first photoresist layer is irradiated by ultraviolet light through the semi-transparent mask.
In some embodiments, before the step of forming the active layer on the substrate, the method further includes:
forming a gate layer on the substrate, and etching the gate layer to obtain a gate layer pattern;
forming a gate insulating layer on the gate layer pattern;
and depositing amorphous silicon on the gate insulating layer to form an active layer.
In some embodiments, before the step of forming the active layer on the substrate, the method further includes:
forming a gate layer on the substrate, and etching the gate layer to obtain a gate layer pattern;
forming a gate insulating layer on the gate layer pattern;
and depositing indium zinc oxide on the gate insulating layer to form an active layer.
In some embodiments, the step of coating a second photoresist layer on the source drain layer includes:
providing the same material as the first photoresist layer;
and coating the material on the source drain layer to obtain a second photoresist layer.
In some embodiments, the step of irradiating the second photoresist layer with light through the mask to obtain a third photoresist pattern includes:
setting the middle area of the photomask as a full light-transmitting area;
setting the two sides of the full light-transmitting area as light-proof areas; the light transmittance of the full light-transmitting area is greater than that of the light-tight area;
setting the two sides of the light-tight area as full light-tight areas to obtain the photomask;
and irradiating the second photoresist layer through the photomask by adopting illumination to obtain a third photoresist pattern.
Meanwhile, an embodiment of the present invention provides a semi-transmissive mask for preparing an active layer prepared by the method for preparing an array substrate according to any of the above embodiments, the semi-transmissive mask including:
an opaque region corresponding to the channel region of the active layer;
semi-transparent regions arranged at two sides of the non-transparent region, wherein the semi-transparent regions correspond to the conductor regions of the active layer;
the full light-transmitting regions are arranged at two sides of the semi-light-transmitting region;
the light transmittance of the opaque region is smaller than that of the semi-transparent region, and the light transmittance of the semi-transparent region is smaller than that of the full-transparent region.
In one embodiment, the light transmittance of the opaque region ranges from 0 to 5%, the light transmittance of the semi-transparent region ranges from 50% to 80%, and the light transmittance of the fully transparent region ranges from 90% to 100%.
Has the advantages that: the embodiment of the application provides an array substrate preparation method and a semi-transparent photomask, wherein the array substrate preparation method comprises the steps of providing a substrate; forming an active layer on the substrate; coating a first photoresist layer on the active layer; carrying out photoetching treatment on the first light resistance layer by adopting light to penetrate through a semi-transparent photomask to obtain a first light resistance pattern; the semi-transparent photomask comprises an opaque region, a semi-transparent region and a full-transparent region, wherein the light transmittance of the opaque region is less than that of the semi-transparent region, and the light transmittance of the semi-transparent region is less than that of the full-transparent region; the active layer comprises a channel region and a conductor region, the opaque region corresponds to the channel region, and the semi-transparent region corresponds to the conductor region; the first light resistance pattern comprises a first light resistance area corresponding to the light-tight area and a second light resistance area corresponding to the semi-light-permeable area, and the thickness of the first light resistance area is larger than that of the second light resistance area; etching the active layer and the first photoresist pattern to obtain a second photoresist pattern and an active layer pattern; forming a source drain layer on the active layer pattern and the second photoresist pattern; coating a second light resistance layer on the source drain layer; carrying out photoetching treatment on the second light resistance layer by adopting light to penetrate through a photomask to obtain a third light resistance pattern; the third light resistance pattern corresponds to the source drain electrode pattern of the source drain electrode layer; etching the source drain layer to obtain a source drain layer pattern; when the first light resistance layer is exposed, the semi-transparent light cover is adopted to expose the first light resistance layer, so that a first light resistance pattern can be remained in a channel region and a conductor region of the active layer, then the active layer is etched, and a second light resistance pattern can be continuously remained in the channel region of the active layer, so that the second light resistance pattern can protect the channel region of the active layer during subsequent film preparation, the channel region of the active layer is not damaged, the stability of the thin film transistor is improved, and the technical problem that the active layer is damaged in the existing preparation method of the liquid crystal display panel is solved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of an array substrate corresponding to a conventional array substrate manufacturing method.
Fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Fig. 3 is a first schematic view of an array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.
Fig. 4 is a second schematic view of the array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.
Fig. 5 is a third schematic view of the array substrate corresponding to each step of the array substrate preparation method provided in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
The embodiment of the application aims at the technical problem that the active layer is damaged in the existing preparation method of the liquid crystal display panel, and is used for relieving the problem.
As shown in fig. 1, a method for manufacturing a thin film transistor in an existing liquid crystal display panel includes sequentially forming a substrate 111, a gate electrode layer 112, a gate insulating layer 113, and an active layer 114, as shown in (a) of fig. 1, after the active layer 114 is manufactured, as shown in (b) of fig. 1, a source/drain electrode layer 115 is directly formed on the active layer 114, and the source/drain electrode layer 115 is etched to obtain a source/drain electrode layer pattern, but when the source/drain electrode layer 115 is etched, the active layer 114 is etched, which may cause an incomplete active layer 114, which may cause damage to the active layer, affect the stability of the thin film transistor, and cause a poor display effect of the display panel, that is, the existing method for manufacturing a liquid crystal display panel has a technical problem of damaging the active layer.
As shown in fig. 2, 3, 4, and 5, an embodiment of the present application provides a method for manufacturing an array substrate, including:
s1, providing a substrate 211; the preparation results are shown in (a) of fig. 3;
s2, forming an active layer 214 on the substrate 211; the preparation results are shown in (a) of fig. 3;
s3, coating a first photoresist layer 215 on the active layer 214; the preparation results are shown in (b) of fig. 3;
s4, performing photolithography on the first photoresist layer 215 through the semi-transparent mask 31 using the light 32 to obtain a first photoresist pattern 2151; the semi-transparent mask 31 comprises an opaque region 313, a semi-transparent region 312 and a full-transparent region 311, wherein the light transmittance of the opaque region 313 is less than that of the semi-transparent region 312, and the light transmittance of the semi-transparent region 312 is less than that of the full-transparent region 311; the active layer comprises a channel region and a conductor region, the opaque region 313 corresponds to the channel region, the semi-transparent region 312 corresponds to the conductor region, the first photoresist pattern 2151 comprises a first photoresist region 2511 corresponding to the opaque region 313 and a second photoresist region 2512 corresponding to the semi-transparent region 312, and the thickness L2 of the first photoresist region 2511 is greater than the thickness L1 of the second photoresist region 2511; the preparation results are shown in (c) and (d) of FIG. 3;
s5, etching the active layer 214 and the first photoresist pattern 2151 to obtain a second photoresist pattern 2152 and an active layer pattern 2141; the preparation results are shown in (a) of fig. 4;
s6, forming a source drain layer 216 on the active layer pattern 2141 and the second photoresist pattern 2152; the second photoresist pattern 2152 is correspondingly disposed in the channel region; the preparation results are shown in fig. 4 (b);
s7, coating a second photoresist layer 217 on the source/drain layer 216; the preparation results are shown in (c) of fig. 4;
s8, irradiating the second photoresist layer 217 with light through the mask 33, the result of which is shown in fig. 5 (a), and obtaining a third photoresist pattern 2171, the result of which is shown in fig. 5 (b); the third light resistance pattern corresponds to the source drain electrode pattern of the source drain electrode layer;
s9, etching the source/drain layer 216 to obtain a source/drain layer pattern 2161; the preparation results are shown in fig. 5 (b).
The embodiment of the application provides a preparation method of an array substrate, which comprises the steps of providing a substrate; forming an active layer on the substrate; coating a first photoresist layer on the active layer; carrying out photoetching treatment on the first light resistance layer by adopting light to penetrate through a semi-transparent photomask to obtain a first light resistance pattern; the semi-transparent photomask comprises an opaque region, a semi-transparent region and a full-transparent region, wherein the light transmittance of the opaque region is less than that of the semi-transparent region, and the light transmittance of the semi-transparent region is less than that of the full-transparent region; the active layer comprises a channel region and a conductor region, the opaque region corresponds to the channel region, and the semi-transparent region corresponds to the conductor region; the first light resistance pattern comprises a first light resistance area corresponding to the light-tight area and a second light resistance area corresponding to the semi-light-permeable area, and the thickness of the first light resistance area is larger than that of the second light resistance area; etching the active layer and the first photoresist pattern to obtain a second photoresist pattern and an active layer pattern; forming a source drain layer on the active layer pattern and the second photoresist pattern; coating a second light resistance layer on the source drain layer; carrying out photoetching treatment on the second light resistance layer by adopting light to penetrate through a photomask to obtain a third light resistance pattern; the third light resistance pattern corresponds to the source drain electrode pattern of the source drain electrode layer; etching the source drain layer to obtain a source drain layer pattern; when the first light resistance layer is exposed, the semi-transparent light cover is adopted to expose the first light resistance layer, so that a first light resistance pattern can be remained in a channel region and a conductor region of the active layer, then the active layer is etched, and a second light resistance pattern can be continuously remained in the channel region of the active layer, so that the second light resistance pattern can protect the channel region of the active layer during subsequent film preparation, the channel region of the active layer is not damaged, the stability of the thin film transistor is improved, and the technical problem that the active layer is damaged in the existing preparation method of the liquid crystal display panel is solved.
It should be noted that the source and drain layer patterns include source patterns, drain patterns, and data line patterns, but the embodiment of the present application is not limited thereto, and the source and drain layer patterns include each electrode and trace formed by etching the source and drain.
In one embodiment, the source and drain layers comprise a titanium/aluminum/titanium stack.
In an embodiment, after the step of etching the source/drain layer to obtain the source/drain layer pattern, the method further includes:
stripping the second photoresist pattern 2152 and the third photoresist pattern 2171; the preparation results are shown in fig. 5 (c);
and forming a planarization layer on the source drain layer to obtain the array substrate.
In one embodiment, the step of performing a photolithography process on the first photoresist layer using a light-transmissive semi-transparent mask to obtain a first photoresist pattern includes:
aligning the semi-transparent photomask and the array substrate so that the opaque region corresponds to the channel region and the semi-transparent region corresponds to the conductor region;
irradiating the first light resistance layer by adopting illumination to obtain a first light resistance pattern; when the first photoresist layer is irradiated by light through the semi-transparent mask, the semi-transparent mask is first made to correspond to the array substrate, as shown in (c) of fig. 3, the semi-transparent mask 31 is set as an opaque region 313, semi-transparent regions 312 are set on two sides of the opaque region 313, full-transparent regions 311 are set on two sides of the semi-transparent regions 312, the opaque region corresponds to the channel region, and the semi-transparent regions correspond to the conductor regions, so that when light passes through the mask, the transmittance of the light is inconsistent, and the photoresist above the active layer pattern is retained.
In one embodiment, the ratio of the thickness of the first photoresist region to the thickness of the second photoresist region is in a range of one fourth to one half, and when the first photoresist pattern is formed, the thickness of the second photoresist region is kept in a certain range, so that the situation that the active layer cannot be protected due to the fact that the thickness of the second photoresist region is too small can be avoided, and the situation that the second photoresist pattern cannot be removed when the source and drain patterns are formed subsequently can be avoided due to the fact that the thickness of the second photoresist region is too large.
In one embodiment, the step of obtaining the first photoresist pattern by irradiating the first photoresist layer with light through a semi-transparent mask comprises: the first light resistance layer is irradiated by ultraviolet light through the semi-transparent light mask, and when the first light resistance layer is irradiated, the ultraviolet light can be irradiated by the semi-transparent light mask, so that the light resistance is exposed, developed and removed, the first light resistance layer is removed according to the semi-transparent light mask, and an active layer pattern can be formed by etching according to the first light resistance pattern in a corresponding follow-up process.
In one embodiment, before the step of forming the active layer on the substrate, the method further includes:
forming a gate layer on the substrate 211, and etching the gate layer to obtain a gate layer pattern 212; the preparation results are shown in (a) of fig. 3;
forming a gate insulating layer 213 on the gate layer pattern 212; the preparation results are shown in (a) of fig. 3;
depositing amorphous silicon on the gate insulating layer 213 to form an active layer; when the active layer is formed, the active layer can be formed by adopting amorphous silicon, namely, the preparation method of the array substrate adopted by the application is suitable for the amorphous silicon thin film transistor, so that the amorphous silicon thin film transistor normally works, and the array substrate with the amorphous silicon thin film transistor normally works.
It should be noted that the gate layer pattern includes a gate pattern and a scan line pattern, but the embodiment of the present application is not limited thereto, and the gate layer pattern includes various electrodes and traces formed by etching the gate layer.
In one embodiment, the material of the gate layer comprises a single layer of metal or a stack of any two or more metals of chromium, tungsten, titanium, molybdenum, aluminum, copper.
In one embodiment, before the step of forming the active layer on the substrate, the method further includes:
forming a gate layer on the substrate, and etching the gate layer to obtain a gate layer pattern;
forming a gate insulating layer on the gate layer pattern;
depositing indium zinc oxide on the grid insulating layer to form an active layer; when the active layer is formed, the indium zinc oxide can be adopted to form the grid insulation layer, so that the indium zinc oxide active layer can not be etched by subsequent processing procedures aiming at the indium zinc oxide thin film transistor, the indium zinc oxide thin film transistor can normally work, and the array substrate can normally work.
In one embodiment, the step of coating a second photoresist layer on the source drain layer includes:
providing the same material as the first photoresist layer;
coating the material on the source drain layer to obtain a second light resistance layer; when the second photoresist layer is formed, the second photoresist layer can be formed by adopting the same material as the first photoresist layer, so that the source drain layer is protected by the second photoresist layer, and the source drain layer pattern is correspondingly formed.
In one embodiment, the step of obtaining the third photoresist pattern by irradiating the second photoresist layer with light through the mask comprises:
setting the middle area of the photomask as a full light-transmitting area;
setting the two sides of the full light-transmitting area as light-proof areas; the light transmittance of the full light-transmitting area is greater than that of the light-tight area;
setting the two sides of the light-tight area as full light-tight areas to obtain the photomask;
irradiating the second photoresist layer through the photomask by adopting illumination to obtain a third photoresist pattern; as shown in fig. 5 (a), the photomask is configured to include the opaque region 332 and the fully transmissive region 331, specifically, the positional relationship between the opaque region 332 and the fully transmissive region 331 is as shown in fig. 5 (a), and by configuring the opaque region and the fully transmissive region to be alternated, after a third photoresist layer pattern is formed, a source/drain layer pattern can be formed by correspondingly etching the source/drain layer, so that a source/drain electrode pattern is formed by the photoresist layer, and due to the existence of the second photoresist pattern, when the source/drain layer is etched, a channel region of the active layer is not etched, so that the active layer is protected from being damaged.
In one embodiment, the step of obtaining the third photoresist pattern by irradiating the second photoresist layer through the mask with light comprises: irradiating the second photoresist layer through the photomask by using ultraviolet light to obtain a third photoresist pattern; when the second photoresist layer is exposed and developed, ultraviolet light can be adopted to etch the second photoresist layer through the photomask, so that the second photoresist layer is exposed, developed and removed, and a third photoresist pattern is correspondingly formed, so that when the source drain layer is subsequently etched, a source drain layer pattern is obtained according to the third photoresist pattern.
In an embodiment, the step of etching the active layer to obtain the second photoresist pattern and the active layer pattern includes: dry etching the active layer to obtain a second photoresist pattern and an active layer pattern; when the active layer is etched, dry etching or wet etching can be used.
As shown in fig. 3 (c), the present embodiment provides a semi-transparent mask for preparing an active layer prepared by the method for preparing an array substrate according to any one of the above embodiments, wherein the semi-transparent mask 31 includes:
an opaque region 313 corresponding to a channel region of the active layer 215;
a full light-transmitting region 311 provided on both sides of the semi-light-transmitting region 312;
the light transmittance of the opaque region 313 is less than that of the semi-transparent region 312, and the light transmittance of the semi-transparent region 312 is less than that of the fully transparent region 311.
The embodiment of the application provides a semi-transparent photomask, which is used for preparing an active layer prepared by the array substrate preparation method in any one of the embodiments, and the semi-transparent photomask comprises an opaque region, a semi-transparent region and a full-transparent region, wherein the opaque region corresponds to a channel region of the active layer, the semi-transparent region is arranged on two sides of the opaque region, the semi-transparent region corresponds to a conductor region of the active layer, and the full-transparent region is arranged on two sides of the semi-transparent region, wherein the light transmittance of the opaque region is smaller than that of the semi-transparent region, and the light transmittance of the semi-transparent region is smaller than that of the full-transparent region; the semi-transparent photomask is set to be the non-transparent area, the semi-transparent area and the full-transparent area, so that when the active layer is prepared, the channel area of the active layer corresponds to the non-transparent area, the conductor area of the active layer corresponds to the semi-transparent area, the light resistor is reserved above the channel area of the active layer, and part of the light resistor is reserved above the conductor area of the active layer, so that the light resistor protects the channel area of the active layer, the light resistor can be stripped in the subsequent process, the normal work of the display panel is not affected, and the technical problem that the active layer is damaged in the existing preparation method of the liquid crystal display panel is solved.
In one embodiment, the light transmittance of the opaque region ranges from 0 to 5%, the light transmittance of the semi-transparent region ranges from 50% to 80%, and the light transmittance of the fully transparent region ranges from 90% to 100%; when the light transmittance of the opaque region, the semi-transparent region and the full-transparent region is set, the light transmittance of the opaque region can be 0, the opaque region has no light transmittance, so that the light resistance of the channel region is kept, the channel region is protected, the opaque region also has low light transmittance, a part of the light resistance of the opaque region is etched, a part of the light resistance is kept, and the subsequent stripping is facilitated, the light transmittance of the semi-transparent region is greater than that of the opaque region, so that a part of the light resistance can be kept by the first light resistance layer corresponding to the semi-transparent region, and the active layer is protected, but the light resistance corresponding to the semi-transparent region is less and is easy to remove in the subsequent processing, so that when an active layer pattern is formed by etching, the light resistance of the semi-transparent region is removed, and the subsequent processing is performed; the light transmittance of the full light-transmitting region can be 100%, so that light is irradiated onto the photoresist, the photoresist corresponding to the full light-transmitting region is removed, and the active layer corresponding to the full light-transmitting region can be etched subsequently to form an active layer pattern.
The sizes of the opaque region, the semi-transmissive region, and the fully transmissive region are set according to the size of the channel region of the active layer and the size of the pattern of the active layer in actual design.
In an embodiment, an array substrate is provided in an embodiment of the present application, and the array substrate includes an array substrate prepared by the method for preparing an array substrate described in any of the above embodiments.
In one embodiment, the substrate comprises a glass substrate.
In one embodiment, the material of the gate insulating layer includes silicon oxide and silicon nitride.
In an embodiment, an embodiment of the present application provides a display panel, where the array substrate includes an array substrate prepared by the array substrate preparation method described in any one of the embodiments, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.
In one embodiment, the color film substrate includes a common electrode layer, a black matrix layer, and a color resist layer.
In one embodiment, the present application provides an array substrate manufacturing system, which manufactures an array substrate using the array substrate manufacturing method described in any one of the above embodiments.
According to the above embodiments:
the embodiment of the application provides an array substrate preparation method and a semi-transparent photomask, wherein the array substrate preparation method comprises the steps of providing a substrate; forming an active layer on the substrate; coating a first photoresist layer on the active layer; carrying out photoetching treatment on the first light resistance layer by adopting light to penetrate through a semi-transparent photomask to obtain a first light resistance pattern; the semi-transparent photomask comprises an opaque region, a semi-transparent region and a full-transparent region, wherein the light transmittance of the opaque region is less than that of the semi-transparent region, and the light transmittance of the semi-transparent region is less than that of the full-transparent region; the active layer comprises a channel region and a conductor region, the opaque region corresponds to the channel region, and the semi-transparent region corresponds to the conductor region; the first light resistance pattern comprises a first light resistance area corresponding to the light-tight area and a second light resistance area corresponding to the semi-light-permeable area, and the thickness of the first light resistance area is larger than that of the second light resistance area; etching the active layer and the first photoresist pattern to obtain a second photoresist pattern and an active layer pattern; forming a source drain layer on the active layer pattern and the second photoresist pattern; coating a second light resistance layer on the source drain layer; carrying out photoetching treatment on the second light resistance layer by adopting light to penetrate through a photomask to obtain a third light resistance pattern; the third light resistance pattern corresponds to the source drain electrode pattern of the source drain electrode layer; etching the source drain layer to obtain a source drain layer pattern; when the first light resistance layer is exposed, the semi-transparent light cover is adopted to expose the first light resistance layer, so that a first light resistance pattern can be remained in a channel region and a conductor region of the active layer, then the active layer is etched, and a second light resistance pattern can be continuously remained in the channel region of the active layer, so that the second light resistance pattern can protect the channel region of the active layer during subsequent film preparation, the channel region of the active layer is not damaged, the stability of the thin film transistor is improved, and the technical problem that the active layer is damaged in the existing preparation method of the liquid crystal display panel is solved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate manufacturing method and the semi-transparent mask provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming an active layer on the substrate;
coating a first photoresist layer on the active layer;
carrying out photoetching treatment on the first light resistance layer by adopting light to penetrate through a semi-transparent photomask to obtain a first light resistance pattern; the semi-transparent photomask comprises an opaque region, a semi-transparent region and a full-transparent region, wherein the light transmittance of the opaque region is less than that of the semi-transparent region, and the light transmittance of the semi-transparent region is less than that of the full-transparent region; the active layer comprises a channel region and a conductor region, the opaque region corresponds to the channel region, and the semi-transparent region corresponds to the conductor region; the first light resistance pattern comprises a first light resistance area corresponding to the light-tight area and a second light resistance area corresponding to the semi-light-permeable area, and the thickness of the first light resistance area is larger than that of the second light resistance area;
etching the active layer and the first photoresist pattern to obtain a second photoresist pattern and an active layer pattern; the second photoresist pattern is correspondingly arranged in the channel region;
forming a source drain layer on the active layer pattern and the second photoresist pattern;
coating a second light resistance layer on the source drain layer;
carrying out photoetching treatment on the second light resistance layer by adopting light to penetrate through a photomask to obtain a third light resistance pattern; the third light resistance pattern corresponds to the source drain electrode pattern of the source drain electrode layer;
and etching the source drain layer to obtain a source drain layer pattern.
2. The method for preparing the array substrate according to claim 1, wherein the step of performing the photolithography process on the first photoresist layer using a light-transmissive semi-transmissive mask to obtain a first photoresist pattern comprises:
aligning the semi-transparent photomask and the array substrate so that the opaque region corresponds to the channel region and the semi-transparent region corresponds to the conductor region;
and carrying out photoetching treatment on the first photoresist layer by adopting illumination to obtain a first photoresist pattern.
3. The method of claim 1, wherein the ratio of the thickness of the first photoresist region to the thickness of the second photoresist region is in the range of one-quarter to one-half.
4. The method for preparing the array substrate according to claim 1, wherein the step of performing the photolithography process on the first photoresist layer using a light-transmissive semi-transmissive mask to obtain a first photoresist pattern comprises: the first photoresist layer is irradiated by ultraviolet light through the semi-transparent mask.
5. The method for preparing an array substrate according to claim 1, wherein the step of forming the active layer on the substrate further comprises:
forming a gate layer on the substrate, and etching the gate layer to obtain a gate layer pattern;
forming a gate insulating layer on the gate layer pattern;
and depositing amorphous silicon on the gate insulating layer to form an active layer.
6. The method for preparing an array substrate according to claim 1, wherein the step of forming the active layer on the substrate further comprises:
forming a gate layer on the substrate, and etching the gate layer to obtain a gate layer pattern;
forming a gate insulating layer on the gate layer pattern;
and depositing indium zinc oxide on the gate insulating layer to form an active layer.
7. The method for preparing an array substrate according to claim 1, wherein the step of coating a second photoresist layer on the source and drain layers comprises:
providing the same material as the first photoresist layer;
and coating the material on the source drain layer to obtain a second photoresist layer.
8. The method for preparing an array substrate according to claim 1, wherein the step of irradiating the second photoresist layer with light through a mask to obtain a third photoresist pattern comprises:
setting the middle area of the photomask as a full light-transmitting area;
setting the two sides of the full light-transmitting area as light-proof areas; the light transmittance of the full light-transmitting area is greater than that of the light-tight area;
setting the two sides of the light-tight area as full light-tight areas to obtain the photomask;
and irradiating the second photoresist layer through the photomask by adopting illumination to obtain a third photoresist pattern.
9. A semi-transparent mask for preparing an active layer prepared by the method of preparing an array substrate according to any one of claims 1 to 8, the semi-transparent mask comprising:
an opaque region corresponding to the channel region of the active layer;
semi-transparent regions arranged at two sides of the non-transparent region, wherein the semi-transparent regions correspond to the conductor regions of the active layer;
the full light-transmitting regions are arranged at two sides of the semi-light-transmitting region;
the light transmittance of the opaque region is smaller than that of the semi-transparent region, and the light transmittance of the semi-transparent region is smaller than that of the full-transparent region.
10. The translucent mask of claim 9, wherein the light transmittance of the opaque region ranges from 0 to 5%, the light transmittance of the translucent region ranges from 50% to 80%, and the light transmittance of the fully transmissive region ranges from 90% to 100%.
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