CN111610960B - Divider module based on LMS and division method thereof - Google Patents

Divider module based on LMS and division method thereof Download PDF

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CN111610960B
CN111610960B CN201811005142.1A CN201811005142A CN111610960B CN 111610960 B CN111610960 B CN 111610960B CN 201811005142 A CN201811005142 A CN 201811005142A CN 111610960 B CN111610960 B CN 111610960B
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sign
module
lms
result
value
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CN111610960A (en
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尹勇生
闫辉
孟宇
邓红辉
陈红梅
孟煦
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Hefei University of Technology
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Hefei University of Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

Abstract

The invention discloses a divider module based on LMS and a division method thereof. The invention has the characteristics of low resource consumption, strong noise resistance and the like, and can be widely applied to various digital signal processing systems.

Description

Divider module based on LMS and division solving method thereof
Technical Field
The invention relates to a divider module in the technical field of electronic science, in particular to a digital circuit implementation of a divider.
Technical Field
In the technical field of electronic science, division operation is a basic operation, and in many complex mathematical calculations, division operation is one of indispensable implementation processes. Particularly, in many complicated mathematical simulation and numerical approximation processes, the adopted method is to iterate in units of step sizes, and each iteration needs to use a large number of multiplication and division operations. Among arithmetic operations, the divider is one of the most resource-consuming and process-complex components in the design. In each unit of the microprocessor, a divider plays a crucial role, and therefore, the performance, power consumption, and operation speed of the divider are also one of the key factors for improving the performance of the microprocessor. Therefore, in applications, especially hardware-implemented numerical calculations, there are considerable demands on the divider.
Since the third industrial revolution, researchers in various fields invest a lot of effort and time to quickly implement basic operations such as addition, subtraction, multiplication, division, modular multiplication, modular exponentiation and the like of data, and generally, a long way is needed for any algorithm from the theoretical description to the actual implementation, because the theory and the practice are two distinct concepts. Therefore, researchers pay great heart blood and sweat to complete the final realization of many algorithms. The same is true for the research of division, and researchers begin with the analysis of common division and gradually develop division algorithms with different principles by using the principle of the hand calculation division method. The invention develops a new method, replaces division operation with multiplication, completes the division operation with less hardware consumption and obtains better performance than the traditional divider.
Disclosure of Invention
The invention provides a divider module based on LMS and a division method thereof to overcome the defects in the prior art, so as to complete the division operation in a digital signal processing system with low hardware consumption, suppress the noise of an input signal and achieve the effects of high operation precision and stable output.
The invention adopts the following technical scheme for solving the technical problems:
the divider module based on the LMS of the invention is characterized by comprising the following components: absolute value module Abs, multiplier, subtracter, least mean square error module LMS, Sign value module Sign, Sign value module Mult;
the absolute value dereferencing module Abs receives and operates an externally input signal a to obtain an absolute value | a | of a and transmits the absolute value | a | to the multiplier;
the least mean square error module LMS outputs an initial value B after reset 1 To the multiplier;
the absolute value | a | and initial value B of the multiplier pair a 1 Performing operation to obtain initial multiplication result | a | × B 1 Then transmitting to a subtracter;
the subtractionThe device receives an externally input signal c and an initial multiplication result | a | × B 1 And performing operation to obtain an initial calculation result c- | a |. times B 1 As the nth input value of the least mean square error module LMS, where n is 1;
obtaining the (n + 1) th output value B by the least mean square error module LMS n+1 Then respectively transmitting the signals to the multiplier and a sign assignment module Mult;
the multiplier calculates the absolute value | a | of the a and the output value of the (n + 1) th time to obtain the multiplication result | a | xBb of the (n + 1) th time n+1 Then transmitting to a subtracter;
the subtracter receives an externally input signal c and an n +1 th multiplication result | a | × B n+1 And operating to obtain the calculation result c-a x B n+1 As the n +1 th input value of the least mean square error module LMS;
the Sign evaluation module Sign receives an externally input signal a and carries out operation to obtain an output result Sign (a), and then transmits the output result Sign (a) to the Sign evaluation module Mult;
the sign assignment module Mult assigns an output result sign (a) and an n +1 th output value B n+1 And performing operation to obtain the final result b of the divider module, which is c/a.
The invention relates to a method for solving the division of a divider module based on LMS, which is characterized by comprising the following steps:
step 1, receiving an externally input signal a by using an absolute value dereferencing module Abs and calculating to obtain an absolute value | a |;
step 2, defining the number of LMS iterations as n, initializing n to 1, and enabling the nth iteration result B n ＝0；
Step 3, utilizing a multiplier to pair the absolute value | a | and the initial value B of a n Performing operation to obtain initial multiplication result | a | × B n ；
Step 4, receiving an externally input signal c and an initial multiplication result | a | × B by using a subtracter n And performing operation to obtain the n-th calculation result c- | a | × B n As an input value for the nth iteration;
step 5, utilizing the minimum meanThe square error module LMS calculates the n-th calculation result c-a multiplied by B n Performing the n-th LMS iterative operation to obtain the n + 1-th iterative result B n+1 ；
Step 6, assigning n +1 to n, and returning to the step 3;
step 7, utilizing a Sign value taking module Sign to carry out Sign value taking operation on the signal a to obtain a Sign (a) of a;
step 8, according to the sign (a) of a, utilizing a sign assignment module Mult to carry out n +1 th iteration result B n+1 And carrying out sign assignment operation to obtain the final result b of division operation as c/a.
Compared with the prior art, the invention has the beneficial effects that:
1. compared with the traditional divider, the divider module realizes division operation with lower hardware consumption, saves hardware resources, has simple realization mode, and can replace the traditional divider in various digital signal processing systems;
2. the invention is realized based on an LMS system, can greatly reduce the influence of noise in an input signal on an operation result, and has the characteristics of strong anti-noise performance and stable output signal compared with the traditional divider.
Drawings
FIG. 1 is a schematic block diagram of an LMS-based divider module according to the present invention;
FIG. 2 is a schematic block diagram of an LMS module according to the present invention;
FIG. 3a is a waveform diagram of input signal a and signal c of the present invention;
FIG. 3b is a waveform diagram comparing the output of the divider according to the present invention and the conventional divider under the condition of the input signals a and c.
Detailed Description
In this embodiment, an LMS-based divider module, as shown in fig. 1, includes: absolute value module Abs, multiplier, subtracter, least mean square error module LMS, Sign value module Sign, Sign value module Mult; signals a and c of a digital signal processing system (such as a digital calibration system for calibrating gain errors between TIADC channels) enter the divider module, and a division operation result b is obtained after the signals a and c pass through the divider module; in particular, the present invention relates to a method for producing,
an absolute value dereferencing module Abs receives and operates an input signal a of the digital signal processing system to obtain an absolute value | a | of a, and then transmits the absolute value | a |, to a multiplier;
the LMS module outputs an initial value B after reset 1 To the multiplier;
the multiplier pair a absolute value | a | and an initial value B 1 Performing operation to obtain initial multiplication result | a | × B 1 Then transmitting to a subtracter;
the subtracter receives an input signal c of the digital signal processing system and an initial multiplication result | a | × B 1 And performing operation to obtain an initial calculation result c- | a |. times B 1 As the nth input value of the least mean square error module LMS, where n is 1;
the nth input value is processed by a least mean square error module LMS to obtain an n +1 th output value B n+1 Then respectively transmitting the signals to a multiplier and a plus-minus assignment module Mult;
the multiplier calculates the absolute value | a | of a and the output value of the (n + 1) th time to obtain the multiplication result | a | × B of the (n + 1) th time n+1 Then transmitting to a subtracter;
the subtracter receives an externally input signal c and the multiplication result | a | × B of the (n + 1) th time n+1 And performing operation to obtain the calculation result c-a multiplied by B n+1 As the n +1 th input value of the least mean square error module LMS; obtaining the n +2 th output value B again by the least mean square error module LMS n+2 Repeating the iteration in the same way; the structure of the least mean square error module LMS is shown in fig. 2, and the recursive formula of the LMS algorithm is: b is n+1 ＝B n +μ×(c n -B n ×a n )。
The Sign evaluation module Sign receives an externally input signal a and carries out operation to obtain an output result Sign (a), and then the output result Sign (a) is transmitted to the Sign evaluation module Mult;
the sign assignment module Mult assigns the output result sign (a) and the (n + 1) th output value B n+1 And performing operation to obtain the final result b of the divider module as c/a.
In this embodiment, a method for solving the division of the LMS-based divider module includes the following steps:
step 1, receiving an input signal a of a digital signal processing system by using an absolute value dereferencing module Abs and calculating to obtain an absolute value | a |;
step 2, defining the number of LMS iterations as n, initializing n to 1, and enabling the nth iteration result B n ＝0；
Step 3, utilizing a multiplier to pair the absolute value | a | and the initial value B of a n Performing operation to obtain initial multiplication result | a | × B n ；
Step 4, receiving an input signal c and an initial multiplication result | a | × B of the digital signal processing system by using a subtracter n And performing operation to obtain the nth calculation result c-a multiplied by B n As an input value for the nth iteration;
step 5, utilizing a least mean square error module LMS to calculate the result c- | a | × B for the nth time n Performing the n-th LMS iterative operation to obtain the n + 1-th iterative result B n+1 ；
Step 6, assigning n +1 to n, and returning to the step 3;
step 7, performing Sign value operation on an input signal a of the digital signal processing system by using a Sign value module Sign to obtain a Sign (a) of a;
step 8, according to the sign (a) of a, utilizing a sign assignment module Mult to carry out (n + 1) th iteration result B n+1 And carrying out sign assignment operation to obtain the final result b of division operation as c/a.
The divider realizes the divider with a complex structure by using a multiplier with a simple structure, estimates the division result by using an LMS algorithm, and respectively obtains the outputs as shown in figure 3b under the condition of the same signal input with noise as that shown in figure 3a in comparison with the traditional divider, so that the operation result of the divider is more stable after the divider reaches convergence, the noise suppression effect on the input signal is obvious, and the operation result is more accurate.

Claims (2)

1. An LMS-based divider module, comprising: absolute value dereferencing modules Abs, a multiplier, a subtracter, a minimum mean square error module LMS, a Sign dereferencing module Sign and a Sign assignment module Mult;
the absolute value dereferencing module Abs receives and operates an externally input signal a to obtain an absolute value | a | of a and transmits the absolute value | a | to the multiplier;
the least mean square error module LMS outputs an initial value B after reset 1 To the multiplier;
the multiplier pair's absolute value | a | and initial value B 1 Performing operation to obtain initial multiplication result | a | × B 1 Then transmitting to a subtracter;
the subtracter receives an externally input signal c and an initial multiplication result | a | × B 1 And performing operation to obtain an initial calculation result c- | a |. times B 1 As the nth input value of the least mean square error module LMS, where n is 1;
obtaining the n +1 th output value B by the least mean square error module LMS n+1 Then respectively transmitting the signals to the multiplier and a sign assignment module Mult;
the multiplier calculates the absolute value | a | of the a and the output value of the (n + 1) th time to obtain the multiplication result | a | xBb of the (n + 1) th time n+1 Then transmitting to a subtracter;
the subtracter receives an externally input signal c and the multiplication result | a | × B of the (n + 1) th time n+1 And operating to obtain the calculation result c-a x B n+1 As the n +1 th input value of the least mean square error module LMS; obtaining the n +2 th output value B again by the least mean square error module LMS n+2 And repeating iteration in such a way, wherein the recursion formula of the LMS algorithm is as follows: b is n+1 ＝B n +μ×(c n -B n ×a n )；
The Sign evaluation module Sign receives an externally input signal a and carries out operation to obtain an output result Sign (a), and then transmits the output result Sign (a) to the Sign evaluation module Mult;
the sign assignment module Mult assigns an output result sign (a) and an n +1 th output value B n+1 Operating to obtain the divider moduleThe final result of the block b is c/a.
2. The dividing method of the divider module based on the LMS is characterized by comprising the following steps of:
step 1, receiving an externally input signal a by using an absolute value dereferencing module Abs and calculating to obtain an absolute value | a |;
step 2, defining the number of LMS iterations as n, initializing n to 1, and enabling the nth iteration result B n ＝0；
Step 3, utilizing a multiplier to pair the absolute value | a | and the initial value B of a n Performing operation to obtain initial multiplication result | a | × B n ；
Step 4, receiving an externally input signal c and an initial multiplication result | a | × B by using a subtracter n And performing operation to obtain the n-th calculation result c- | a | × B n As an input value for the nth iteration;
step 5, utilizing a least mean square error module LMS to calculate the result c- | a | × B for the nth time n Performing the n-th LMS iterative operation to obtain the n + 1-th iterative result B n+1 (ii) a The recursive formula of the LMS algorithm is: b is n+1 ＝B n +μ×(c n -B n ×a n )；
Step 6, assigning n +1 to n, and returning to the step 3;
step 7, utilizing a Sign value taking module Sign to carry out Sign value taking operation on the signal a to obtain a Sign (a) of a;
step 8, according to the sign (a) of a, utilizing a sign assignment module Mult to carry out n +1 th iteration result B n+1 And carrying out sign assignment operation to obtain the final result b of division operation as c/a.
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