CN111610691B

CN111610691B - Optimization method and system of mask design pattern and electronic device thereof

Info

Publication number: CN111610691B
Application number: CN201910134676.2A
Authority: CN
Inventors: 张生睿
Original assignee: Shenzhen Jingyuan Information Technology Co Ltd
Current assignee: Shenzhen Jingyuan Information Technology Co Ltd
Priority date: 2019-02-23
Filing date: 2019-02-23
Publication date: 2023-05-16
Anticipated expiration: 2039-02-23
Also published as: CN111610691A

Abstract

The present invention relates to the field of photolithography in semiconductor manufacturing, and in particular, to a method and a system for optimizing a mask design pattern, and an electronic device thereof. The optimization method of the mask design pattern comprises the following steps: performing slicing treatment on the basic pattern, and performing pixel mask optimization on the basis of each slicing pattern to obtain a corresponding pixel mask pattern; extracting a polygonal mask, preprocessing to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result; based on the simulation verification result, performing the space occupation operation of polygonal mask optimization or performing the actual optimization operation of polygonal mask, outputting corresponding operation results, and summarizing the operation results to be used as the optimized mask design pattern. Compared with the prior art, the optimization method, the system and the electronic device of the mask design pattern provided by the invention shorten the optimization time of the mask design pattern and can be used for manufacturing a large-area layout.

Description

Optimization method and system of mask design pattern and electronic device thereof

[ field of technology ]

The present invention relates to the field of photolithography for semiconductor manufacturing, and more particularly, to optimization of mask design patterns, a system and an electronic device thereof.

[ background Art ]

Photolithography is the most important process in the existing large-scale integrated circuit manufacturing process, namely, an important means for transferring the design pattern of the integrated circuit on the mask to the silicon wafer through a photolithography machine. When the integrated circuit design pattern on the mask is imaged on a silicon wafer through a projection objective of a photoetching machine, the diffraction phenomenon of light is obvious due to the small feature size of the pattern on the mask. When some higher-order diffracted light cannot participate in imaging due to the aperture limitation of the projection objective optical system, the imaging on the silicon wafer generates deformation and the phenomenon that the pattern cannot be resolved. This phenomenon is called optical proximity effect OP E (Opti c al Pro ximity E ffe ct). To address the optical proximity effect, one can achieve an improvement in imaging quality by optimizing the pattern on the mask to produce a pattern quality. Current inverse lithography techniques can provide mask optimization solutions with superior robustness (Robus t). However, in the actual operation of the inversion lithography technology, the data operand is extremely large, so that the time cost of mask design is increased, and the manufacture of a large-area layout is not facilitated.

Therefore, there is a need to provide an efficient and fast optimization scheme for mask design patterns.

[ invention ]

In order to solve the technical problem of high optimization time cost in the optimization scheme of the existing mask design pattern, the invention provides an optimization method and system of the mask design pattern and electronic equipment thereof.

The invention provides the following technical scheme for solving the technical problems: a method for optimizing a mask design pattern, providing a base pattern, the method comprising the steps of: step S1: performing gridding slicing treatment on the basic pattern to obtain a plurality of slicing patterns; constructing an objective function, inputting the segmented patterns and the objective function into a numerical value optimizer, and performing pixel mask optimization based on pixels of each segmented pattern as variables to obtain corresponding pixel mask patterns; step S2: extracting a polygonal mask based on the segmented pixel mask pattern, preprocessing the polygonal mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result; step S3: based on the simulation verification result, performing the space occupying operation of the polygonal mask optimization or performing the actual optimization operation of the polygonal mask, and outputting a corresponding operation result; step S4: and summarizing the operation result to be used as the optimized mask design pattern.

Preferably, the optimizer adopts a numerical optimization method of one or two of Newton iteration method and conjugate gradient iteration method.

Preferably, the step S2 further includes: step S21: extracting a polygonal mask after binarization (B in ari z ati on Pro c e S S ing) based on the pixel mask pattern, wherein the polygonal mask comprises a main pattern (M ain F e feature) and a subsidiary pattern (S ub-Re S o luti o n A S S i S tant F e ature); step S22: performing primary treatment on the auxiliary graph; step S23:

fixing the auxiliary graph after preliminary treatment, performing optical proximity correction treatment on the main graph, and outputting the polygonal mask after treatment; step S24: and outputting a verification result after performing simulation verification on the processed polygonal mask.

Preferably, the step S3 further includes: step S31: obtaining a simulation verification result; step S32: judging whether the simulation verification result meets the expected photoetching performance requirement, if so, executing a step S33; if not, executing step S34; step S33: transmitting an S KIP (skip) signal to execute the space occupying operation of polygon mask optimization, and outputting a corresponding operation result; step S34: the actual optimization operation of the polygon mask is performed and the corresponding operation result is output.

Preferably, the actual operation of polygonal mask optimization specifically includes: and inputting the polygonal mask and the objective function into a numerical value optimizer, performing polygonal mask optimization by taking the geometric sides of each polygon in the polygonal mask as variables, and outputting a polygonal mask optimization operation result.

The invention provides the following technical scheme for solving the technical problems: an optimization system for a mask design pattern, comprising: a pixel mask pattern generation module: the method comprises the steps of configuring a base pattern for gridding and slicing to obtain a plurality of sliced patterns; constructing an objective function, inputting the segmented patterns and the objective function into a numerical value optimizer, and performing pixel mask optimization based on pixels of each segmented pattern as variables to obtain corresponding pixel mask patterns; and a simulation verification module: the method comprises the steps of configuring a polygon mask based on a segmented pixel mask pattern, preprocessing the polygon mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result; polygonal mask optimization module: the method comprises the steps of configuring occupation operation for executing polygon mask optimization or actual optimization operation for executing the polygon mask based on simulation verification results, and outputting corresponding operation results; mask design pattern generation module: is configured to aggregate the results of the operations as an optimized mask design pattern.

Preferably, the pixel mask pattern generating module includes: and a slicing module: the method comprises the steps of configuring a base pattern for gridding and slicing to obtain sliced patterns; and a numerical value optimization module: the method comprises the steps of configuring an objective function, inputting a slicing pattern and the objective function into a numerical optimizer, and optimizing a pixel mask by taking pixels of the slicing pattern as variables to obtain a corresponding pixel mask pattern.

Preferably, the simulation verification module further comprises: polygonal mask extraction module: the method comprises the steps of configuring a polygonal mask after binarization processing based on a pixel mask pattern, wherein the polygonal mask comprises a main pattern and an auxiliary pattern; an auxiliary graphics processing module: the configuration is used for carrying out preliminary processing on the auxiliary graph; the main graphics processing module: the method comprises the steps of configuring an auxiliary graph used for fixing the primary graph after preliminary processing, performing optical proximity correction processing on the main graph, and outputting a polygonal mask after processing; and a result output module: and the configuration is used for outputting a verification result after simulation verification of the processed polygonal mask.

The invention provides the following technical scheme for solving the technical problems: an electronic device comprising a storage unit and one or more processing units, the storage unit for storing one or more programs; when the one or more programs are executed by the one or more processing units, the one or more processing units implement the method of optimizing a mask design pattern as set forth in any one of the preceding claims.

Compared with the prior art, the optimization method of the mask design pattern provided by the invention has the advantages that the segmentation processing is carried out on the basis of the basic pattern to obtain a plurality of segmentation patterns, the pixel mask optimization and the binarization processing are carried out on the segmentation patterns, the simulation verification step is introduced after the polygonal mask pattern is obtained, the segmentation patterns which are required by photoetching performance in the optimization process can be screened in time, the subsequent polygonal mask optimization process is not needed, thus the number of segmentation for carrying out polygonal mask optimization is reduced, the optimization time of the mask design pattern is greatly shortened, and the optimization method can be used for manufacturing a large-area layout.

According to the optimization method of the mask design pattern, the basic pattern is subjected to gridding slicing treatment to obtain the slicing pattern which is convenient for optimizing the pixel mask, and subsequent operation is performed based on the slicing pattern, so that the method has flexibility and can solve the manufacturing of a large-area layout.

In the optimization method of the mask design pattern, the auxiliary pattern is subjected to preliminary treatment, so that the auxiliary pattern can be ensured to be printed on the mask plate and not printed on a silicon wafer, and the optimization accuracy of the mask design pattern is further improved.

The optimization method of the mask design pattern provided by the invention is used for fixing the auxiliary pattern after preliminary treatment and carrying out optical proximity correction treatment on the main pattern, wherein the time of each operation in the optical proximity correction operation is only about one tenth of the time of pixel mask optimization or polygonal mask optimization. The process can save a great deal of operation time and improve efficiency.

In the optimization method of the mask design pattern, the S KIP signal is sent to perform the space occupying operation of the segmented polygonal mask, so that the consistency of the operation of each segmented pattern is ensured when the processed segmented patterns are finally integrated together, and the result of each segmented pattern is finally integrated correctly.

The optimization system and the electronic device of the mask design pattern have the same beneficial effects as the optimization method of the mask design pattern, and are not repeated herein.

[ description of the drawings ]

FIG. 1 is a schematic flow chart of steps of a method for optimizing a mask design pattern according to a first embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for optimizing a pixel mask according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram showing the basic pattern gridding of a mask design optimization method according to the first embodiment of the present invention;

FIG. 4 is a schematic diagram of a method for optimizing a mask design pattern according to a first embodiment of the present invention;

FIG. 5 is a flowchart illustrating steps before simulation verification of a mask design pattern optimization method according to a first embodiment of the present invention;

FIG. 6 is a schematic diagram of a method for optimizing a mask design pattern according to a first embodiment of the present invention;

FIG. 7 is a flowchart illustrating steps of a method for optimizing a mask design pattern according to a first embodiment of the present invention;

FIG. 8 is a schematic diagram of a frame structure providing a mask design pattern optimization system provided in a second embodiment of the present invention;

FIG. 9 is a schematic diagram of a frame structure for providing a pixel mask generation of a mask design pattern optimization system according to a second embodiment of the present invention;

FIG. 10 is a schematic diagram of a frame structure of a simulation verification module providing a mask design pattern optimization system according to a second embodiment of the present invention;

FIG. 11 is a schematic diagram of a frame structure of a polygonal mask optimizing module providing a mask design pattern optimizing system according to a second embodiment of the present invention;

fig. 12 is a schematic diagram of a frame structure of an electronic device according to a third embodiment of the present invention.

The attached drawings are identified:

11. a tile pattern; 12. a pixel mask pattern; 13. a polygonal mask; 131. a primary pattern; 132. an auxiliary pattern;

20. an optimization system for the mask design pattern; 21. a pixel mask pattern generation module; 22. a simulation verification module; 23. a polygonal mask optimization module; 24. a mask design pattern generation module; 211. a slicing module; 212. a numerical value optimizing module; 221. a polygon mask extraction module; 222. an auxiliary graphics processing module; 223. a main graphic processing module; 224. a result output module; 231. the simulation result acquisition module; 232. a polygon mask optimizing operation module;

40. an electronic device; 41. a storage unit; 42. and a processing unit.

[ detailed description ] of the invention

For the purpose of making the technical solution and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The invention provides an optimization method of a mask design pattern, which aims to solve the technical problem of high optimization time cost in the existing optimization scheme of the mask design pattern.

Referring to fig. 1, a mask design pattern optimization method S10 of the present invention specifically includes the following steps:

step S1: performing slicing treatment on the basic pattern to obtain a plurality of slicing patterns, and performing pixel mask optimization on the basis of each slicing pattern to obtain a corresponding pixel mask pattern; step S2: extracting a polygonal mask based on the segmented pixel mask pattern, preprocessing the polygonal mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result;

step S3: based on the simulation verification result, performing the space occupying operation of the polygonal mask optimization or performing the actual optimization operation of the polygonal mask, and outputting a corresponding operation result; step S4: and summarizing the operation result to be used as the optimized mask design pattern.

The basic pattern is a pattern finally printed on the silicon wafer in the photoetching manufacturing process.

As shown in fig. 2, in some embodiments of the present invention, the step S1 is as follows: the base pattern is subjected to slicing treatment to obtain a plurality of slicing patterns, and pixel mask optimization is carried out on the basis of each slicing pattern to obtain a corresponding pixel mask pattern, and the method further comprises the following steps:

step S11: performing gridding slicing treatment on the basic pattern to obtain a sliced pattern; a kind of electronic device with high-pressure air-conditioning system

Step S12: constructing an objective function, inputting the segmentation pattern and the objective function into a numerical value optimizer, and performing pixel mask optimization by taking pixels of the segmentation pattern as variables to obtain a pixel mask pattern.

The gridding process is to divide the basic pattern into individual grid units, namely fragments, and to implement dynamic, independent and omnibearing optimization operation based on each grid, which is a digital division format.

The meshing rule is to determine the information such as the number of grids, the shapes of the grids, the sizes of the grids and the like based on the basic pattern information (the size of the basic pattern, the shape of the basic pattern and the complexity of the basic pattern), so that the generation of the segmented pattern is convenient for the operation of the subsequent steps.

The slicing comprises a slicing pattern and each evaluation point set based on the slicing pattern.

The objective function sets an independent objective function of each slice based on preset parameters, and each slice can perform distributed independent operation and is used for a function of errors of a slice pattern and a mask design pattern contained in the slice.

The optimizer adopts one or two numerical optimization methods of Newton iteration method or conjugate gradient iteration method.

The pixel mask optimization process in step S12 requires hundreds or even thousands of iterations before outputting the optimized pixel mask pattern. This process takes a relatively high time and cost.

The pixel mask pattern is typically a gray scale pattern or a so-called pixel based mask pattern.

As shown in fig. 3, a basic pattern is provided for illustration in order to better explain the protected contents of the present invention. And performing slicing treatment on the basic pattern through gridding to obtain slicing patterns 11, wherein the basic pattern comprises 5832 slicing patterns 11.

The patch pattern 11 and the objective function are input into a numerical optimizer, and pixel mask optimization is performed with the pixels of the patch pattern 11 as variables, resulting in a patch pixel mask pattern 12 as shown in fig. 4.

As shown in fig. 5, in some embodiments of the present invention, the step S2 is as follows: extracting a polygonal mask based on the segmented pixel mask pattern, preprocessing the polygonal mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result; the method further comprises the following steps:

step S21: extracting a polygonal mask after binarization processing based on the pixel mask pattern, wherein the polygonal mask comprises a main pattern and an auxiliary pattern;

step S22: performing primary treatment on the auxiliary graph;

step S23: fixing the auxiliary graph after preliminary treatment, performing optical proximity correction treatment on the main graph, and outputting the polygonal mask after treatment; a kind of electronic device with high-pressure air-conditioning system

Step S24: and outputting a verification result after performing simulation verification on the processed polygonal mask.

In the above step S21, the binarization processing means that the gradation value of the pixel point on the pixel mask pattern is set to 0 or 255, that is, the entire pixel mask pattern is rendered to exhibit a clear black-and-white effect.

The polygon extraction is to extract the outline of the image from the binarized image, so as to obtain a polygon mask with auxiliary graphics.

Specifically, the gray-scale value of the pixel mask pattern 12 shown in fig. 4 is set to 0 or 255 so that it exhibits a remarkable black-and-white effect, and the polygon mask 13 shown in fig. 6 is obtained after the polygon extraction. The polygonal mask 13 includes a main pattern 131 and an auxiliary pattern 132.

The main pattern 131 is a pattern to be printed on the silicon wafer, which remains in the sliced pattern after being sliced based on the basic pattern; the auxiliary pattern 132 is usually much smaller than the main pattern 131, and the auxiliary pattern 132 is other patterns of the non-main pattern 131 obtained through pixel mask optimization and binarization; the auxiliary pattern 132 is only present in the reticle, but is not printed on the silicon wafer, and only plays a role in enhancing the imaging of the main pattern 131.

The preliminary processing is performed on the auxiliary pattern 132 in the above-described step S22, and the preliminary processing includes the process of manufacturing and print-out prevention of the auxiliary pattern 132. The manufacturable process ensures that the auxiliary pattern 132 can be printed on the reticle; the anti-print process ensures that the auxiliary pattern 132 is not printed on the silicon wafer.

In the step S23, the preliminary processed auxiliary pattern is fixed, the main pattern is subjected to optical proximity correction, and the processed polygonal mask is output.

The optical proximity correction is a lithography enhancement technique, and aims to ensure that the edges of the design pattern are completely etched. Optical proximity correction corrects these errors by shifting the edges of the pattern on the reticle or adding additional polygons. A look-up table is pre-computed based on width and pitch constraints or by using the results of a compact model dynamic simulation, from which it is decided how to move the edges of the pattern, finding the best solution.

The time of each operation in the optical proximity correction operation is only about one tenth of the pixel mask optimization or polygon mask optimization time. The process can save a great deal of operation time and improve efficiency.

And (3) performing simulation verification on the polygonal mask obtained in the step S23 to check whether the polygonal mask meets the requirement of photoetching performance.

The simulation verification process comprises the following steps: and (3) establishing a corresponding detection rule according to the fragment pattern information contained in each fragment, and detecting the polygonal mask in the step S23 based on the detection rule so as to verify whether the polygonal mask meets the lithography performance requirement.

The lithography performance refers to the effect of generating a basic pattern on a silicon wafer after lithography by taking a mask design pattern as a template pattern in actual lithography work.

The description will be continued with reference to the basic pattern provided by the present invention. After simulation verification is performed on the polygonal mask shown in fig. 6, a verification result is obtained. The simulation verification results showed that only 1172 of the 5832 polygon masks tested did not meet the requirements of the expected lithographic performance, accounting for approximately 20%.

As shown in fig. 7, in some embodiments of the present invention, the step S3 is as follows: based on the simulation verification result, performing the space occupying operation of the polygonal mask optimization or performing the actual optimization operation of the polygonal mask, and outputting a corresponding operation result; specifically, the step S3 may include the following steps:

step S31: obtaining a simulation verification result;

step S32: judging whether the simulation verification result meets the expected photoetching performance requirement, if so, executing a step S33; if not, executing step S34;

step S33: transmitting an S KIP signal to execute the space occupying operation of polygon mask optimization, and outputting a corresponding operation result;

here, only the occupation operation of the polygon mask optimization is performed, and the same result as step S32, i.e., the polygon mask after the optical proximity correction processing is output without performing the operation of the polygon mask optimization.

Step S34: the actual optimization operation of the polygon mask is performed and the corresponding operation result is output.

The result of the processing here is: the design pattern of the segmented mask is obtained through the actual optimization operation of the polygonal mask.

Finally, summarizing the operation results of each slice to be used as the optimized mask design pattern.

In the step S33, the occupying operation specifically refers to a step of sending an S KI P signal to the polygon mask optimization when the processed polygon mask meets the requirement of lithography; the polygon mask optimization step starts to be executed after receiving the SKIP signal, but only one occupying operation does not perform actual operation.

The space occupying action is needed because all the segmented patterns processed by the steps are finally integrated together, so that the operation of each segmented pattern is required to be consistent, and the results of the segmented patterns can be accurately integrated finally.

In the above step S34, when the processed polygon mask does not meet the requirements of lithography, the S KI P signal is not transmitted, and the actual operation of polygon mask optimization is directly performed.

The practical operation of the polygon mask optimization specifically includes: and inputting the polygonal mask and the objective function into a numerical optimizer, performing polygonal mask optimization by taking the geometric edges of each polygon in the polygonal mask as variables, and outputting a polygonal mask optimization operation result, namely the segmented mask design pattern meeting the photoetching performance requirement.

And the summarizing operation results comprise summarizing the operation results of each piece, and integrating the operation results to obtain the mask design pattern optimized based on the basic pattern.

By the optimization method of the mask design pattern, the time cost of the mask design pattern can be effectively reduced by introducing the simulation verification method in the optimization operation process of the mask design pattern. The tile pattern optimization includes pixel mask optimization, binarization processing, and polygon mask optimization.

Referring to fig. 8, a second embodiment of the present invention provides an optimization system 20 for mask design pattern, comprising:

the pixel mask pattern generation module 21: the method comprises the steps of configuring a base pattern for carrying out slicing processing to obtain a plurality of slicing patterns, and carrying out pixel mask optimization based on each slicing pattern to obtain a corresponding pixel mask pattern;

simulation verification module 22: the method comprises the steps of configuring a polygon mask based on a segmented pixel mask pattern, preprocessing the polygon mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result;

polygonal mask optimization module 23: the method comprises the steps of configuring occupation operation for executing polygon mask optimization or actual optimization operation for executing the polygon mask based on simulation verification results, and outputting corresponding operation results; a kind of electronic device with high-pressure air-conditioning system

Mask design pattern generation module 24: is configured to aggregate the results of the operations as an optimized mask design pattern.

As shown in fig. 9, the pixel mask pattern generating module 21 includes:

the slicing module 211: the method comprises the steps of configuring a base pattern for gridding and slicing to obtain sliced patterns; a kind of electronic device with high-pressure air-conditioning system

The numerical optimization module 212: the method comprises the steps of configuring an objective function, inputting a slicing pattern and the objective function into a numerical optimizer, and optimizing a pixel mask by taking pixels of the slicing pattern as variables to obtain a corresponding pixel mask pattern.

As shown in fig. 10, the simulation verification module 22 further includes:

polygon mask extraction module 221: the method comprises the steps of configuring a polygonal mask after binarization processing based on a pixel mask pattern, wherein the polygonal mask comprises a main pattern and an auxiliary pattern;

auxiliary graphics processing module 222: the configuration is used for carrying out preliminary processing on the auxiliary graph;

the main graphics processing module 223: the method comprises the steps of configuring an auxiliary graph used for fixing the primary graph after preliminary processing, performing optical proximity correction processing on the main graph, and outputting a polygonal mask after processing; a kind of electronic device with high-pressure air-conditioning system

The result output module 224: and the configuration is used for outputting a verification result after simulation verification of the processed polygonal mask.

As shown in fig. 11, the polygon mask optimizing module 23 further includes:

simulation result acquisition module 231: the configuration is applied to obtaining a simulation verification result; a kind of electronic device with high-pressure air-conditioning system

Polygon mask optimization operation module 232: the simulation verification method is configured to judge whether the simulation verification result meets the expected photoetching performance requirement; if yes, sending an S KIP signal to execute the space occupying operation of polygon mask optimization, and outputting a corresponding operation result; if not, executing the actual optimization operation of the polygon mask, and outputting a corresponding operation result.

The optimization system 20 for mask design patterns provided by the invention has the same beneficial effects as the optimization method for mask design patterns, and therefore, the description thereof is omitted.

As shown in fig. 12, a third embodiment of the present invention provides an electronic device 40, including a storage unit 41 and one or more processing units 42, where the storage unit 41 is configured to store one or more programs; when the one or more programs are executed by the one or more processing units 42, the one or more processing units 42 are caused to implement the weight estimation method.

The electronic device 40 provided in this embodiment includes hardware or software. When the electronic device is hardware, it may be various electronic devices supporting optimization of the mask design pattern, including but not limited to mask manufacturing devices, lithographic devices. In some particular embodiments, the electronic device 40 may also be a smart lithographic apparatus.

When the electronic apparatus 40 is software, it can be installed in the above-listed electronic device. It may be implemented as a plurality of software or software modules (e.g., a plurality of software or software modules for providing distributed services) or as a single software or software module, without limitation.

In particular, according to the disclosed embodiments of the invention, the processes described above with reference to flowcharts may be implemented as computer software programs.

For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. It should be noted that, the computer readable medium described in the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two.

The server may be a server that provides various services, such as a background processing server that provides support for optimization of mask design patterns.

The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (C D-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing. Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Jav a, S m al ltalk, c++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.

In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).

It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. The modules involved in the embodiments described in the present application may be implemented by software, or may be implemented by hardware.

The described modules may also be provided in a processor, for example, as: a processor includes a pixel mask pattern generation module, a simulation verification module, and a mask design pattern generation module. The names of these modules are not limited to the module itself in some cases, and for example, the pixel mask pattern generation module may also be described as "a module for performing a slicing process on a base pattern to obtain a plurality of sliced patterns, performing pixel mask optimization based on each sliced pattern to obtain a corresponding sliced pixel mask pattern" or the like.

As another aspect, the present application also provides a computer-readable medium that may be embodied in the system or apparatus described in the above embodiments; or may exist alone without being assembled into the system or device.

The computer readable medium carries one or more programs which, when executed by the system or apparatus, cause the system or apparatus to: performing slicing treatment on the basic pattern to obtain a plurality of slicing patterns, and performing pixel mask optimization on the basis of each slicing pattern to obtain a corresponding pixel mask pattern; extracting a polygonal mask based on the pixel mask pattern, preprocessing the polygonal mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result; and based on the simulation verification result, performing the space occupation operation of the polygonal mask optimization or performing the actual optimization operation of the polygonal mask, outputting corresponding operation results, and summarizing the operation results to be used as the optimized mask design pattern.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the invention, but any modifications, equivalents, improvements, etc. within the principles of the present invention should be included in the scope of the present invention.

Claims

1. A method of optimizing a mask design pattern, characterized by: providing a basic pattern, wherein the optimization method of the mask design pattern comprises the following steps:

step S1: performing gridding slicing treatment on the basic pattern to obtain a plurality of slicing patterns; constructing an objective function, inputting the segmented patterns and the objective function into a numerical value optimizer, and performing pixel mask optimization based on pixels of each segmented pattern as variables to obtain corresponding pixel mask patterns;

step S2: extracting a polygonal mask based on the segmented pixel mask pattern, preprocessing the polygonal mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result;

step S3: based on the simulation verification result, performing the space occupying operation of the polygonal mask optimization or performing the actual optimization operation of the polygonal mask, and outputting a corresponding operation result; a kind of electronic device with high-pressure air-conditioning system

Step S4: and summarizing the operation result to be used as the optimized mask design pattern.

2. The method of optimizing a mask design pattern according to claim 1, wherein: the optimizer adopts one or two numerical optimization methods of Newton iteration method or conjugate gradient iteration method.

3. The method of optimizing a mask design pattern according to claim 1, wherein: the step S2 further includes:

step S22: performing primary treatment on the auxiliary graph;

4. The method of optimizing a mask design pattern according to claim 1, wherein: the step S3 further includes:

step S31: obtaining a simulation verification result;

step S33: transmitting an S KIP signal to execute the space occupying operation of polygon mask optimization, and outputting a corresponding operation result; a kind of electronic device with high-pressure air-conditioning system

5. The method of optimizing a mask design pattern according to claim 4, wherein: the actual operation of polygonal mask optimization specifically comprises the following steps: and inputting the polygonal mask and the objective function into a numerical value optimizer, performing polygonal mask optimization by taking the geometric sides of each polygon in the polygonal mask as variables, and outputting a polygonal mask optimization operation result.

6. A mask design pattern optimizing system for optimizing a mask design pattern by using the mask design pattern optimizing method according to any one of claims 1 to 5, characterized in that: comprising the following steps:

a pixel mask pattern generation module: the method comprises the steps of configuring a base pattern for gridding and slicing to obtain a plurality of sliced patterns; constructing an objective function, inputting the segmented patterns and the objective function into a numerical value optimizer, and performing pixel mask optimization based on pixels of each segmented pattern as variables to obtain corresponding pixel mask patterns;

and a simulation verification module: the method comprises the steps of configuring a polygon mask based on a segmented pixel mask pattern, preprocessing the polygon mask to obtain a processing result, performing simulation verification on the processing result, and outputting a simulation verification result;

polygonal mask optimization module: the method comprises the steps of configuring occupation operation for executing polygon mask optimization or actual optimization operation for executing the polygon mask based on simulation verification results, and outputting corresponding operation results; a kind of electronic device with high-pressure air-conditioning system

Mask design pattern generation module: is configured to aggregate the results of the operations as an optimized mask design pattern.

7. The mask design pattern optimization system of claim 6, wherein: the pixel mask pattern generation module includes:

and a slicing module: the method comprises the steps of configuring a base pattern for gridding and slicing to obtain sliced patterns; a kind of electronic device with high-pressure air-conditioning system

And a numerical value optimizing module: the method comprises the steps of configuring an objective function, inputting a slicing pattern and the objective function into a numerical optimizer, and optimizing a pixel mask by taking pixels of the slicing pattern as variables to obtain a corresponding pixel mask pattern.

8. The mask design pattern optimization system of claim 6, wherein: the simulation verification module further comprises:

polygonal mask extraction module: the method comprises the steps of configuring a polygonal mask after binarization processing based on a pixel mask pattern, wherein the polygonal mask comprises a main pattern and an auxiliary pattern;

an auxiliary graphics processing module: the configuration is used for carrying out preliminary processing on the auxiliary graph; the main graphics processing module: is configured for

Fixing the auxiliary graph after preliminary treatment, performing optical proximity correction treatment on the main graph, and outputting the polygonal mask after treatment; a kind of electronic device with high-pressure air-conditioning system

And a result output module: and the configuration is used for outputting a verification result after simulation verification of the processed polygonal mask.

9. An electronic device, characterized in that: the device comprises a storage unit and one or more processing units, wherein the storage unit is used for storing one or more programs; when the one or more programs are executed by the one or more processing units, the one or more processing units are caused to implement the mask design pattern optimization method of any one of claims 1-5.