CN111603676B - Flexible artificial retina stimulation chip - Google Patents
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- CN111603676B CN111603676B CN202010281706.5A CN202010281706A CN111603676B CN 111603676 B CN111603676 B CN 111603676B CN 202010281706 A CN202010281706 A CN 202010281706A CN 111603676 B CN111603676 B CN 111603676B
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- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
- A61N1/00—Electrotherapy; Circuits therefor
- A61N1/18—Applying electric currents by contact electrodes
- A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
- A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
- A61N1/36046—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation of the eye
Abstract
The invention belongs to the field of integrated circuits and biomedicine, and particularly relates to a flexible artificial retina stimulation chip. The chip can convert optical signals into electric signals and stimulate optic nerves to form vision, is made of flexible thin film materials, and is suitable for human bodies. The circuit is a retina stimulation unit array, and comprises m rows and n columns of stimulation units, 1 digital-to-analog converter and 2 constant bias circuits. Each stimulation unit adopts an analog Memory (ARAM) and a Time sequence Control circuit (Time Control) to perform Time division multiplexing on an output signal of the digital-to-analog converter so as to adjust the conduction state of a transistor in the stimulation unit and simulate the perception of human bodies on light signals. The digital-to-analog converter has 8-bit resolution and high control precision. The time sequence is provided among the stimulating units by adopting a time sequence control circuit. The chip can provide help for visually impaired people to recover vision.
Description
Technical Field
The invention belongs to the technical field of integrated circuits and biomedicine, and particularly relates to a flexible artificial retina stimulation chip.
Background
The retina is an important part of human body for generating vision, and optical signals form optic nerve excitation after being processed by photoreceptor cells and optic nerves of the retina and are transmitted to central optic nerves of brain for generating vision. If the retina is necrosed or pathological changes, the life of the patient is seriously influenced, most of the blind patients in China are diseases caused by outer layer retinal degeneration, such as Retinitis Pigmentosa (RP) and age-related macular degeneration (AMD), and the vision of the blind patients is difficult to recover through medication or surgical operations. And restoring the patient's vision by implanting microelectronic devices is a potential solution. In patients with retinitis pigmentosa and age-related macular degeneration, the inner core and the active layer cells have a high survival rate despite a near loss of photoreceptive function, and thus can be stimulated by electrical signals to produce effective vision. The artificial retina technology is a vision recovery technology that replaces outer retinal cells that lose visual function with a chip. The artificial retina chip is used for sensing external light signals and generating current signals to stimulate visual nerves so that partial vision of a patient is generated, and the artificial retina chip is one of hot researches in the field of biomedicine.
The current research ideas of the artificial retina chip implantation technology can be divided into two categories: subretinal implantation and retinal surface implantation. The subretinal implantation technology is that a chip is implanted between necrotic photoreceptor cells and inner nuclear layer cells, and a micro photodiode in the chip replaces the photoreceptor cells to sense light and generate an electric signal to stimulate visual nerve cells to generate vision. However, this implant technique has some disadvantages, such as the requirement for normal retinal neuroepithelium and optic nerve function, which results in a limited range of clinical applications, and in addition, the retinal nutrient supply is blocked, which causes atrophy of the outer layer of the retina. The retina surface implantation technology is that images obtained by a camera outside a retina are modulated into electric signals through a chip and are transmitted, the signals are received inside human eyes, the signals are processed through an artificial retina processing circuit, and finally the retina is electrically stimulated through a nerve electrical stimulation array to recover partial vision of a patient.
The first generation of retina chips stimulate optic nerves by using stimulation signals, so that the blind with damaged retina can see images, but the resolution is too small because the chip has the resolution of only 16 pixels, so that smaller objects cannot be distinguished. The resolution of the second generation retina chip is increased to 64 pixels, and the resolution is improved. When the number of pixels on a chip reaches thousands, the patient will have the ability to read newspapers. As the technology is more mature and the pixels of the chip are higher, the device brings great convenience to the visually impaired.
Disclosure of Invention
The invention aims to provide a high-precision flexible artificial retina stimulation chip which is suitable for a human body.
The flexible artificial retina stimulation chip provided by the invention is made of flexible thin film materials, is suitable for being used for a human body, is internally integrated with an 8-bit digital-to-analog converter, can generate 256 different outputs under different optical signals, and has high tuning precision.
The structure of the flexible artificial retina stimulation chip provided by the invention is shown in fig. 1, the circuit is a retina stimulation unit array, and the flexible artificial retina stimulation chip comprises m rows and n columns of stimulation units, m rows and n columns of time sequence control circuits, 1 digital-to-analog converter and 2 constant bias circuits; the output electric signals of the stimulation unit array stimulate the optic nerve of the human body through the electrodes to generate vision; each stimulation unit represents a pixel, and an output signal of the digital-to-analog converter is subjected to time division multiplexing by adopting an analog memory and a time sequence control circuit so as to adjust the conduction state of partial transistors in the stimulation units and simulate the perception of human bodies on light signals; the digital-to-analog converter has 8-bit resolution, can output 256 current control signals, has high control precision, and is provided with two tunable correction transistors for tuning the output current and improving the output precision of the digital-to-analog converter; 2 constant current bias circuits provide constant bias for the transistors of the stimulation unit part; and a time sequence control circuit is also adopted between each stimulation unit for time sequence control.
In the invention, the stimulating unit is formed by connecting two NMOS transistors M1 and M4 with fixed grid bias voltage and two NMOS transistors M2 and M3 with adjustable grid bias voltage; referring to FIG. 2, the drain of the transistor M1 is connected to the power supply VDD and the gate is connected to the fixed bias V bi The source electrode is connected with the drain electrode of the transistor M2; the grid electrode of the transistor M2 is connected with the output end of the analog memory ARAM1, and the source electrode is connected with the output electrode and the drain electrode of the transistor M3; the grid electrode of the transistor M3 is connected with the output end of the analog memory ARAM2, and the source electrode of the transistor M3 is connected with the drain electrode of the transistor M4; the gate of transistor M4 is connected to a fixed bias V bd The source electrode is grounded; the control signal of the analog memory ARAM1 is connected with the control signal VCA and is connected to the input end of the time sequence control circuit, the output end of the time sequence control circuit is connected with the control signal input end of the analog memory ARAM2, and the input ends of the analog memory ARAM1 and the ARAM2 are both connected to the control signal VC; the transistors M1 and M4 are light-sensitive transistors and have photosensitive characteristics, and the grid electrodes are respectively connected with fixed bias voltage and can convert optical signals including the intensity and wavelength of light into electric signals; the current of the transistor can change along with the change of the optical signal under the fixed bias voltage because the light can change the parameters such as the threshold voltage of the transistor; the transistors M2 and M3 are regulating transistors, the grid voltage of the regulating transistors is controlled by VC, the VC realizes time division multiplexing through analog memories ARAM1 and ARAM2, the grid voltage of the transistors M2 and M3 is controlled, and the stimulation intensity of the output electrode is regulated.
In the invention, the time sequence control circuit consists of 4 NMOS transistors M5, M6, M7 and M8; see alsoAs shown in FIG. 3, the drain of the transistor M5 is connected to the power supply VDD and the drain of the transistor M6, and the gate is connected to the control signal VC 1 The source electrode is connected with the drain electrode of the transistor M7 and the grid electrode of the transistor M8; gate connection control signal VC of transistor M6 2 The source is connected to the output end of the time sequence control circuit and the drain of the transistor M8; the grid electrode of the transistor M7 is connected to the input end of the time sequence control circuit, and the source electrode is grounded; the source of the transistor M8 is grounded; 4 transistors are connected into a two-stage inverting unit to form a delay circuit so as to control the working time sequence of the circuit; in the stimulation unit, two analog memories ARAM1 and ARAM2 are alternately conducted, and the conduction time sequence is the control point of the time sequence circuit; the conduction time sequence of each part of the chip can be controlled by adopting a plurality of time sequence control circuits; the working time sequence of the stimulating units of m rows and n columns is controlled by a plurality of time sequence circuits.
In the invention, the analog memory comprises an ARAM1 and an ARAM2, and is composed of an NMOS transistor M and a capacitor C; referring to fig. 4, the drain of the transistor M is connected to the input terminal of the analog memory, the gate is connected to the control signal VC, the source is connected to the output terminal of the analog memory and one end of the capacitor C, and the other end of the capacitor C is grounded; the analog memory is used for transmitting and adjusting the grid control voltage of the transistors M2 and M3 in the stimulation unit; according to the adjustment of the time sequence control circuit, when a control signal is high, namely the grid voltage of an NMOS transistor M of the analog memory is high, the transistor is turned on, a signal is transmitted from an input node to an output node, and a capacitor C is charged; when the control signal is low, namely the grid voltage of an NMOS transistor M of the analog memory is low, the transistor is closed, the charge quantity stored by the capacitor C is slowly changed, the voltage is basically kept unchanged, and the signal is latched at the output end; according to the time division multiplexing strategy, analog memories ARAM1 and ARAM2 of a transistor M2 and a transistor M3 in the stimulation unit, which are respectively connected in series, are alternately conducted, and a control signal VC is presented to the grids of the transistors M2 and M3 in a time division multiplexing mode so as to control the conduction states of the transistors M2 and M3, thereby adjusting an output signal and further controlling the stimulation of the electrode on the optic nerve.
In the invention, the digital-to-analog converter is composed of 2 NMOS transistors M for providing reference current b0 And M b1 8 provideNMOS transistors M9, M10, M11, M12, M13, M14, M15 and M16 of 8-bit output current, 2 tunable correction NMOS transistors M cal1 And M cal2 Forming; referring to FIG. 5, transistor M b0 Is connected to the gate and to the gates of M9, M10, M11, M12 and a reference current source I 0 One end of (A) is 0 The other end of the power supply is connected with a power supply VDD1; resistance R 1 One end of the SWITCH is connected with a power supply VDD2, and the other end is connected with a SWITCH 1 、SWITCH 2 、SWITCH 3 、SWITCH 4 And a transistor M cal1 Drain of (2), SWITCH 1 The other end of the first and second switches is connected with the drain of the transistor M9 and the SWITCH 2 The other end of the first and second switches is connected to the drain of the transistor M10 and the SWITCH 3 The other end of the first and second switches is connected to the drain of the transistor M11 and the SWITCH 4 The other end of the first transistor is connected to the drain of a transistor M12, transistors M9, M10, M11, M12, M cal1 Source of (3) is grounded, M cal1 Is connected with a tuning correction voltage V cal1 (ii) a Transistor M b1 Is connected to the gate and to the gates of M13, M14, M15, M16 and a reference current source I 1 One end of (A) is 1 The other end of the power supply is connected with a power supply VDD1; resistance R 2 One end of the SWITCH is connected with a power supply VDD2, and the other end of the SWITCH is connected with a SWITCH 5 、SWITCH 6 、SWITCH 7 、SWITCH 8 And a transistor M cal2 Drain of (2), SWITCH 5 The other end of the first SWITCH is connected to the drain of the transistor M13 and the SWITCH 6 The other end of the first and second switches is connected to the drain of the transistor M14, the SWITCH 7 The other end of the first and second switches is connected to the drain of the transistor M15 and the SWITCH 8 The other end of the first transistor is connected to the drain of a transistor M16, and transistors M13, M14, M15, M16, M cal2 Source of (3) is grounded, M cal2 Grid connection tuning correction voltage V cal2 (ii) a The transistor M b0 And M b1 Providing a reference current, and generating 8-bit output currents by 8 transistors M9, M10, M11, M12, M13, M14, M15 and M16; the 8-bit output current is respectively in direct proportion to the reference current, and the proportionality coefficient is related to the transistor size; two tunable rectifying transistors M cal1 And M cal2 The output current is tuned to improve the output accuracy of the digital-to-analog converter.
The chip can help the visually impaired to restore the vision.
Drawings
Fig. 1 is a schematic structural diagram of a flexible artificial retina stimulation chip.
Fig. 2 is a schematic circuit diagram of a stimulation chip Unit (Stimulus Unit) in a 100-module.
Fig. 3 is a schematic diagram of a timing Control circuit (Time Control) in the 100 blocks.
FIG. 4 is a schematic diagram of an analog memory circuit (ARAM) in the 200 block.
Fig. 5 is a schematic diagram of a digital-to-analog converter (DAC) circuit in the 100-module.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 1 shows a circuit topology diagram of the flexible artificial retina stimulation chip of the invention.
As shown in fig. 1, the circuit includes a stimulation unit 200, a timing control circuit 300, an 8-bit digital-to-analog converter 400, and a constant current bias circuit 500. The stimulation unit circuit 200 produces specific outputs that are connected to electrodes to stimulate the optic nerve. The adjustable bias voltage in the stimulation unit circuit 200 is generated by the 8-bit digital-to-analog converter 500, and 256 states are provided, and the two paths of analog memories 400 provide bias for the stimulation unit in the time division multiplexing status, and the timing control unit 300 provides timing for the time division multiplexing strategy. The constant bias portion of the circuit is provided by constant bias circuit 500,as shown in FIG. 1, the constant bias circuit 500 is composed of a transistor M biasi Structure of a transistor M biasi Is connected to the gate and to the output terminal, and is also connected to a constant current source I biasi A paragraph of (a), I biasi And the other end thereof is connected to a power supply VDD.
Fig. 2 shows a block diagram of a stimulation unit circuit 200.
As shown in fig. 2, the stimulation unit 200 is formed by connecting two NMOS transistors M1 and M4 with fixed gate bias voltage, and two NMOS transistors M2 and M3 with adjustable gate bias voltage; the drain of the transistor M1 is connected to a power supply VDD, and the gate is connected to a fixed bias V bi The source electrode is connected with the drain electrode of the transistor M2; the grid electrode of the transistor M2 is connected with the output end of the analog memory ARAM1, and the source electrode is connected with the output electrode and the drain electrode of the transistor M3; the grid electrode of the transistor M3 is connected with the output end of the analog memory ARAM2, and the source electrode of the transistor M3 is connected with the drain electrode of the transistor M4; the gate of transistor M4 is connected to a fixed bias V bd The source electrode is grounded; the control signal of the analog memory ARAM1 is connected with the control signal VCA and is connected to the input end of the time sequence control circuit 202, the output end of the time sequence control circuit 202 is connected with the control signal input end of the analog memory ARAM2, and the input ends of the analog memories ARAM1 and ARAM2 are both connected to the control signal VC; the transistors M1 and M4 are light-sensitive transistors and have photosensitive characteristics, and the grid electrodes are respectively connected with fixed bias voltage and can convert optical signals including the intensity and wavelength of light into electric signals; the current of the transistor can change along with the change of the optical signal under the fixed bias voltage because the light can change the parameters such as the threshold voltage of the transistor; the transistors M2 and M3 are regulating transistors, the grid voltage of the regulating transistors is controlled by VC, the VC realizes time division multiplexing through analog memories ARAM1 and ARAM2, the grid voltage of the transistors M2 and M3 is controlled, and the stimulation intensity of an output electrode is regulated; the circuit structures of the analog memory modules 201 and 203 are the same; the circuit configuration of the timing control circuit 202 is the same as that of the timing control circuit 300.
Fig. 3 shows a block diagram of the timing control circuit 300.
As shown in FIG. 3, the timing control circuit 300 is composed of 4NMOS transistors M5, M6, M7, M8; the drain of the transistor M5 is connected to the power supply VDD and the drain of the transistor M6, and the gate is connected to the control signal VC 1 The source electrode is connected with the drain electrode of the transistor M7 and the grid electrode of the transistor M8; gate connection control signal VC of transistor M6 2 The source electrode is connected to the output end of the time sequence control circuit and the drain electrode of the transistor M8; the grid electrode of the transistor M7 is connected to the input end of the sequential control circuit, and the source electrode is grounded; the source of the transistor M8 is grounded; the transistors M5, M6, M7 and M8 are connected into a two-stage inverting unit to form a delay circuit so as to control the working time sequence of the circuit; in the stimulation unit 200, the two analog memories ARAM1 and ARAM2 are switched on in a time division multiplexing manner, and the switching-on time sequence is the control point of the time sequence circuit; the conduction time sequence of each part of the chip can be controlled by adopting a plurality of time sequence control circuits; the working timing of the m rows and n columns of the stimulating units is controlled by a plurality of timing circuits.
Fig. 4 shows a block diagram of an analog memory cell 201.
As shown in fig. 4, the analog memory 201 includes an ARAM1 and an ARAM2, and is composed of an NMOS transistor M and a capacitor C; the drain electrode of the transistor M is connected to the input end of the analog memory 201, the grid electrode of the transistor M is connected with the control signal VC, the source electrode of the transistor M is connected to the output end of the analog memory 201 and one end of the capacitor C, and the other end of the capacitor C is grounded; the analog memory is used for transmitting and adjusting the grid control voltage of the transistors M2 and M3 in the stimulation unit; according to the adjustment of the time sequence control circuit, when a control signal is high, namely the grid voltage of an NMOS transistor M of the analog memory is high, the transistor is turned on, a signal is transmitted from an input node to an output node, and a capacitor C is charged; when the control signal is low, namely the grid voltage of an NMOS transistor M of the analog memory is low, the transistor is closed, the charge quantity stored by the capacitor C is slowly changed, the voltage is basically kept unchanged, and the signal is latched at the output end; according to the time division multiplexing strategy, analog memories ARAM1 and ARAM2 of a transistor M2 and a transistor M3 in the stimulation unit, which are respectively connected in series, are alternately conducted, and a control signal VC is presented to the grids of the transistors M2 and M3 in a time division multiplexing mode so as to control the conduction states of the transistors M2 and M3, thereby adjusting an output signal and further controlling the stimulation of the electrode on the optic nerve.
Fig. 5 shows a block diagram of an 8-bit digital-to-analog converter 400.
As shown in FIG. 5, the DAC 400 comprises 2 NMOS transistors M for providing reference current b0 And M b1 8 NMOS transistors M9, M10, M11, M12, M13, M14, M15, M16 for providing 8-bit output current, 2 tunable correction NMOS transistors M cal1 And M cal2 Forming; transistor M b0 Is connected to the gate and to the gates of M9, M10, M11, M12 and a reference current source I 0 One end of (A) is 0 The other end of the power supply is connected with a power supply VDD1; resistance R 1 One end of the SWITCH is connected with a power supply VDD2, and the other end is connected with a SWITCH 1 、SWITCH 2 、SWITCH 3 、SWITCH 4 And a transistor M cal1 Drain of (2), SWITCH 1 The other end of the first and second switches is connected with the drain of the transistor M9 and the SWITCH 2 The other end of the first and second switches is connected to the drain of the transistor M10 and the SWITCH 3 The other end of the first and second switches is connected to the drain of the transistor M11 and the SWITCH 4 The other end of the transistor M12, transistors M9, M10, M11, M12, M cal1 Source of (3) is grounded, M cal1 Grid connection tuning correction voltage V cal1 (ii) a Transistor M b1 Is connected to the gate and to the gates of M13, M14, M15, M16 and a reference current source I 1 One end of (A) is 1 The other end of the power supply is connected with a power supply VDD1; resistance R 2 One end of the SWITCH is connected with a power supply VDD2, and the other end is connected with a SWITCH 5 、SWITCH 6 、SWITCH 7 、SWITCH 8 And a transistor M cal2 Drain of (2), SWITCH 5 The other end of the first and second switches is connected to the drain of the transistor M13 and the SWITCH 6 The other end of the first and second switches is connected to the drain of the transistor M14, the SWITCH 7 The other end of the first SWITCH is connected to the drain of the transistor M15 and the SWITCH 8 The other end of the transistor M16, transistors M13, M14, M15, M16, M cal2 Source of (D) is grounded, M cal2 Is connected with a tuning correction voltage V cal2 (ii) a The transistor M b0 And M b1 A reference current is provided, 8 transistors M9 and M10,M11, M12, M13, M14, M15 and M16 generate 8-bit output current; the 8-bit output currents are respectively in direct proportion to the reference current, and the proportionality coefficient is related to the transistor size; two tunable rectifying transistors M cal1 And M cal2 The output current is tuned to improve the output accuracy of the digital-to-analog converter.
Without departing from the spirit and scope of the present invention, many variations and modifications may be made by one of ordinary skill in the art in light of the present disclosure.
Claims (4)
1. A flexible artificial retina stimulation chip is characterized in that a circuit is a retina stimulation unit array and comprises m rows and n columns of stimulation units, a first time sequence control circuit, 1 digital-to-analog converter and 2 constant bias circuits; the output electric signals of the stimulation unit array stimulate the optic nerve of the human body through the electrodes to generate vision; each stimulation unit represents a pixel, and the output signals of the digital-to-analog converter are subjected to time division multiplexing by adopting an analog memory and a second time sequence control circuit so as to adjust the conduction state of partial transistors in the stimulation units and simulate the perception of human bodies on light signals; the digital-to-analog converter has 8-bit resolution, can output 256 current control signals, and is provided with two tunable correction transistors for tuning output current and improving the output precision of the digital-to-analog converter; 2 constant current bias circuits provide constant bias for the transistors of the stimulation unit; a first time sequence control circuit is adopted among each stimulation unit for time sequence control;
the stimulation unit is formed by connecting two NMOS transistors M1 and M4 with fixed grid bias voltage and two NMOS transistors M2 and M3 with adjustable grid bias voltage; the drain of the transistor M1 is connected to a power supply VDD, and the gate is connected to a fixed bias V bi The source electrode is connected with the drain electrode of the transistor M2; the grid electrode of the transistor M2 is connected with the output end of the analog memory ARAM1, and the source electrode is connected with the output electrode and the drain electrode of the transistor M3; the grid electrode of the transistor M3 is connected with the output end of the analog memory ARAM2, and the source electrode of the transistor M3 is connected with the drain electrode of the transistor M4; the gate of transistor M4 is connected to a fixed bias V bd The source electrode is grounded; the control signal of the analog memory ARAM1 is connected with the control signal VCA and is connected to the input end of the second time sequence control circuit, the output end of the second time sequence control circuit is connected with the control signal input end of the analog memory ARAM2, and the input ends of the analog memories ARAM1 and ARAM2 are both connected to the control signal VC; the transistors M1 and M4 are light-sensitive transistors and have photosensitive characteristics, and the grid electrodes are respectively connected with fixed bias voltage and can convert optical signals including the intensity and wavelength of light into electric signals; the threshold voltage of the transistor can be changed by light, so that the current of the transistor can be changed along with the change of the optical signal under the fixed bias voltage; the transistors M2 and M3 are regulating transistors, the grid voltage of the regulating transistors is controlled by VC, the VC realizes time division multiplexing through analog memories ARAM1 and ARAM2, the grid voltage of the transistors M2 and M3 is controlled, and the stimulation intensity of an output electrode is regulated.
2. The flexible artificial retina stimulation chip according to claim 1, wherein the first timing control circuit is composed of 4 NMOS transistors M5, M6, M7, M8; the drain of the transistor M5 is connected to the power supply VDD and the drain of the transistor M6, and the gate is connected to the control signal VC 1 The source electrode is connected with the drain electrode of the transistor M7 and the grid electrode of the transistor M8; gate connection control signal VC of transistor M6 2 A source connected to the output of the first timing control circuit and to the drain of transistor M8; the grid electrode of the transistor M7 is connected to the input end of the first time sequence control circuit, and the source electrode is grounded; the source of the transistor M8 is grounded; 4 transistors are connected into a two-stage phase reversal unit to form a delay circuit so as to control the working time sequence of the circuit; in the stimulation unit, the two analog memories ARAM1 and ARAM2 are alternately conducted, and the conduction time sequence of the two analog memories ARAM1 and ARAM2 is the control point of the second time sequence control circuit; the conduction time sequence of each part of the chip can be controlled by adopting a plurality of first time sequence control circuits; the working time sequence of the stimulating units of m rows and n columns is controlled by a plurality of first time sequence control circuits.
3. The flexible artificial retina stimulation chip according to claim 2, wherein the analog memory comprises ARAM1 and ARAM2, which are composed of NMOS transistor M and capacitor C; the drain electrode of the transistor M is connected to the input end of the analog memory, the grid electrode of the transistor M is connected with the control signal VC, the source electrode of the transistor M is connected to the output end of the analog memory and one end of the capacitor C, and the other end of the capacitor C is grounded; the analog memory is used for transmitting and adjusting the grid control voltage of the transistors M2 and M3 in the stimulation unit; according to the adjustment of the second time sequence control circuit, when the control signal is high, namely the grid voltage of an NMOS transistor M of the analog memory is high, the transistor is turned on, a signal is transmitted from the input node to the output node, and the capacitor C is charged; when the control signal is low, namely the grid voltage of an NMOS transistor M of the analog memory is low, the transistor is closed, the charge quantity stored by the capacitor C changes slowly, the voltage basically keeps unchanged, and the signal is latched at the output end; according to the time division multiplexing strategy, the analog memories ARAM1 and ARAM2 in the stimulation unit are alternately conducted, and the control signal VC is presented to the gates of the transistors M2 and M3 in a time division multiplexing mode so as to control the conduction states of the transistors M2 and M3, thereby regulating the output signal and further controlling the stimulation of the electrode on the optic nerve.
4. The flexible artificial retina stimulation chip according to claim 3, wherein the digital-to-analog converter consists of 2 NMOS transistors M for providing reference current b0 And M b1 8 NMOS transistors M9, M10, M11, M12, M13, M14, M15, M16 providing 8-bit output current, 2 tunable correction NMOS transistors M cal1 And M cal2 Forming; transistor M b0 Is connected to the gate and to the gates of M9, M10, M11, M12 and a reference current source I 0 One end of (A) is 0 The other end of the power supply is connected with a power supply VDD1; resistance R 1 One end of the SWITCH is connected with a power supply VDD2, and the other end of the SWITCH is connected with a SWITCH 1 、SWITCH 2 、SWITCH 3 、SWITCH 4 And a transistor M cal1 Drain of (2), SWITCH 1 The other end of the first and second switches is connected with the drain of the transistor M9 and the SWITCH 2 The other end of the first and second switches is connected to the drain of the transistor M10 and the SWITCH 3 The other end of the first SWITCH is connected to the drain of the transistor M11, the SWITCH 4 Another end of (a) is connected toConnected to the drain of the transistor M12, and transistors M9, M10, M11, M12, M cal1 Source of (3) is grounded, M cal1 Grid connection tuning correction voltage V cal1 (ii) a Transistor M b1 Is connected to the gate and to the gates of M13, M14, M15, M16 and a reference current source I 1 One end of (A) a 1 The other end of the power supply is connected with a power supply VDD1; resistance R 2 One end of the SWITCH is connected with a power supply VDD2, and the other end of the SWITCH is connected with a SWITCH 5 、SWITCH 6 、SWITCH 7 、SWITCH 8 And a transistor M cal2 Drain of (2), SWITCH 5 The other end of the first and second switches is connected to the drain of the transistor M13 and the SWITCH 6 The other end of the first and second switches is connected to the drain of the transistor M14, the SWITCH 7 The other end of the first and second switches is connected to the drain of the transistor M15 and the SWITCH 8 The other end of the first transistor is connected to the drain of a transistor M16, and transistors M13, M14, M15, M16, M cal2 Source of (3) is grounded, M cal2 Grid connection tuning correction voltage V cal2 (ii) a The transistor M b0 And M b1 Providing a reference current, and generating 8-bit output currents by 8 transistors M9, M10, M11, M12, M13, M14, M15 and M16; the 8-bit output currents are respectively in direct proportion to the reference current, and the proportionality coefficient is related to the transistor size; two tunable rectifying transistors M cal1 And M cal2 The output current is tuned to improve the output accuracy of the digital-to-analog converter.
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| CN101058004A (en) * | 2007-05-28 | 2007-10-24 | 重庆大学 | Visual cortex nerve stimulating device and stimulating method |
| CN101590305A (en) * | 2009-06-18 | 2009-12-02 | 重庆大学 | Be used for the artificial retina electrostimulation pixel circuit that visual performance is repaired |
| JP2018143448A (en) * | 2017-03-03 | 2018-09-20 | 株式会社ニデック | Vision recovery assisting system and vision system nerve stimulation device |
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| CN100391558C (en) * | 2005-12-17 | 2008-06-04 | 重庆大学 | Retina electrostimulation pixel circuit for artificial vision rehabilitation |
| WO2010027871A1 (en) * | 2008-08-26 | 2010-03-11 | Second Sight Medical Products | System and method for measuring and fitting spatio-temporal vision |
| US8571669B2 (en) * | 2011-02-24 | 2013-10-29 | Nano-Retina, Inc. | Retinal prosthesis with efficient processing circuits |
| CN104873330B (en) * | 2015-06-19 | 2017-06-13 | 浙江诺尔康神经电子科技股份有限公司 | A kind of artificial retina implant |
| CN106606818A (en) * | 2015-10-21 | 2017-05-03 | 田荣侠 | Visual prosthesis optic nerve stimulator circuit |
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| CN101058004A (en) * | 2007-05-28 | 2007-10-24 | 重庆大学 | Visual cortex nerve stimulating device and stimulating method |
| CN101590305A (en) * | 2009-06-18 | 2009-12-02 | 重庆大学 | Be used for the artificial retina electrostimulation pixel circuit that visual performance is repaired |
| JP2018143448A (en) * | 2017-03-03 | 2018-09-20 | 株式会社ニデック | Vision recovery assisting system and vision system nerve stimulation device |
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