CN111600604A - Method and system for generating digital chip peripheral clock - Google Patents
Method and system for generating digital chip peripheral clock Download PDFInfo
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- CN111600604A CN111600604A CN202010719740.6A CN202010719740A CN111600604A CN 111600604 A CN111600604 A CN 111600604A CN 202010719740 A CN202010719740 A CN 202010719740A CN 111600604 A CN111600604 A CN 111600604A
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- 230000001174 ascending effect Effects 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a method and a system for generating a digital chip peripheral clock, which mainly select N-bit registers from a register N1 to a register Nn from a low bit to a high bit; during initialization, initial values of 0 or 1 are respectively assigned to each bit register; setting the period length of a peripheral clock to be generated as m; when generating an external clock, the frequency of the reference high-frequency clock is f; when the xth high-frequency reference clock signal is received, the output of the peripheral clock generator is the initial value of the register Nx, and the register N1 forms a peripheral clock from the initial value of the register Nm; and after the mth high-frequency reference clock signal is received, counting the high-frequency reference clock signal again, and continuing to generate the peripheral clock by the peripheral clock generator. The peripheral clock generated by the invention has more free ends, the frequency and the duty ratio of the generated peripheral clock can be adjusted, fractional frequency division can be generated, a certain frequency spreading function can be generated, and the electromagnetic interference to a system is reduced.
Description
Technical Field
The invention relates to the technical field of digital electronics, in particular to a method and a system for generating a digital chip peripheral clock.
Background
The digital chip usually includes a synchronous peripheral interface, and the clock of the synchronous peripheral is driven by a clock generator of the peripheral and is output to the outside through the chip pins. The peripheral clock is typically divided by a counter from a high frequency clock f. The principle of the peripheral clock generation method is as follows:
1) setting the initial value of a counter to be N, and the initial value output by a clock generator to be 0;
2) every time a high-frequency reference clock is received, the counter is decreased by 1;
3) every time a high frequency reference clock is received, the value of the counter is compared: if the counter equals [ N/2], the clock generator outputs 1; if the counter is equal to 1, the clock generator output is 0 while reloading the counter to N; otherwise, the clock generator output remains unchanged.
As can be seen from the above principle, the peripheral clock generation system can only perform integer frequency division, i.e. the output clock is 1/N of the reference clock f, and the duty ratio is fixed to 1/2 (N is even) or [ N/2 ]/N. This generates a clock with certain limitations, reducing the compatibility and ease of use of the peripheral. Meanwhile, the interval between the rising edge and the falling edge of the output peripheral clock is fixed, so that the frequency spectrum energy of the clock is concentrated on the set frequency, and the electromagnetic interference to the system is stronger when the clock is output outwards through a chip pin.
Disclosure of Invention
Aiming at the defects, the technical problems to be solved by the invention are as follows: the invention provides a method and a system for generating a digital chip peripheral clock, which can generate fractional frequency division, adjustable duty ratio, adjustable frequency and generate a certain spread spectrum function, and reduce electromagnetic interference to the system.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a method for generating a digital chip peripheral clock comprises the following steps:
s1, selecting an N-bit register from a register N1 to a register Nn from a low bit to a high bit, wherein N is a positive integer;
s2, respectively assigning initial values of 0 or 1 to each bit register during initialization;
s3, setting the period length of the peripheral clock to be generated as m, wherein m is less than or equal to n;
s4, when generating the peripheral clock, referring to the high-frequency clock frequency as f; when an x-th high-frequency reference clock signal is received, the output of the peripheral clock generator is an initial value of a register Nx, wherein x is a positive integer from 1 to m, and the initial value from the register N1 to the register Nm forms a peripheral clock signal;
and S5, when the mth high-frequency reference clock signal is received, counting the high-frequency reference clock signal again, executing S4 and S5, and continuously generating the peripheral clock signal.
The optimal mode is that the initial value of the n-bit register forms one or more of a rising sequence, a falling sequence and a common sequence; when the initial values of the two adjacent registers are 0 and 1 respectively, the initial values of the two adjacent registers form a rising sequence; when the initial values of the two adjacent registers are 1 and 0 respectively, the initial values of the two adjacent registers form a descending sequence; when the initial values of the two adjacent registers are 0 or 1 at the same time, the initial values of the two adjacent registers form a common sequence.
Preferably, in S2, when the initial value from the register N1 to the register Nm includes y rising sequences during initialization, the frequency of the generated peripheral clock signal is f × y/m, where y is a positive integer not greater than m.
Preferably, m is set to be divisible by y, and the peripheral clock signal is an m/y integer division of the high frequency reference clock f.
Preferably, the initial value of the n-bit register forms a rising sequence and a falling sequence, and the duty ratio of the generated peripheral clock signal is adjusted by adjusting the interval between the rising sequence and the falling sequence.
Preferably, the initial values of the n-bit registers form a rising sequence and a falling sequence, and the intervals between the rising sequence and the falling sequence are adjusted to be equal or unequal, so that the frequency of the generated peripheral clock signal is shifted around f × y/m.
A system for generating a digital chip peripheral clock comprises a main control unit, a register unit, a reference high-frequency clock, a clock counter and a peripheral clock generator, wherein the register unit, the reference high-frequency clock, the clock counter and the peripheral clock generator are respectively and electrically connected with the main control unit; the register unit comprises N-bit registers from a low bit to a high bit, namely a register N1 to a register Nn; when the main control unit is initialized, initial values of 0 or 1 are respectively assigned to each bit register; the reference high-frequency clock is used for outputting a reference high-frequency clock signal with the frequency f; the clock counter is used for counting a reference high-frequency clock signal output by the reference high-frequency clock; the peripheral clock generator is used for outputting an initial value of a register Nx when an x-th high-frequency reference clock signal is received, wherein x is a positive integer from 1 to m, and the register N1 to the initial value of the register Nm form a peripheral clock signal; and after the mth high-frequency reference clock signal is received, the main control unit controls the clock counter to clear and count again, and the peripheral clock generator continues to generate a peripheral clock.
Preferably, the system further comprises a frequency setting unit electrically connected with the main control unit, the frequency setting unit transmits a corresponding frequency electrical signal to the main control unit according to the frequency of a peripheral clock signal to be generated, the frequency electrical signal comprises an initial value of each register, and the main control unit sets the initial value of each register during initialization according to the received frequency electrical signal.
Preferably, when the frequency of the peripheral clock to be generated is f multiplied by y/m, wherein y is a positive integer not greater than m; the frequency electric signal comprises y rising sequences from the setting register N1 to the initial value of the register Nm, and when the initial values of two adjacent registers are 0 and 1 respectively, the initial values of the two adjacent registers form the rising sequences.
The optimal mode is that the system also comprises a duty ratio adjusting unit which is electrically connected with the main control unit, the duty ratio adjusting unit transmits a corresponding adjusting electric signal to the main control unit according to the duty ratio of a peripheral clock signal to be generated, the adjusting electric signal is the interval between a rising sequence and a falling sequence which are formed by the initial values of the registers, and when the initial values of two adjacent registers are respectively 1 and 0, the initial values of the two adjacent registers form a falling sequence; and the main control unit sets the initial value of each register during initialization according to the received adjusting electric signal.
After the technical scheme is adopted, the invention has the beneficial effects that:
the invention relates to a method and a system for generating a digital chip peripheral clock, which mainly select a bit register from a register N1 to a register Nn from a low bit to a high bit; during initialization, initial values of 0 or 1 are respectively assigned to each bit register; setting the period length of a peripheral clock to be generated as m; when generating an external clock, the frequency of the reference high-frequency clock is f; when the xth high-frequency reference clock signal is received, the output of the peripheral clock generator is the initial value of the register Nx, and the register N1 to the initial value of the register Nm form the peripheral clock signal; and after the mth high-frequency reference clock signal is received, counting the high-frequency reference clock signal again, and continuously generating the peripheral clock signal by the peripheral clock generator. The peripheral clock generated by the invention has more free ends, the frequency and the duty ratio of the generated peripheral clock can be adjusted, fractional frequency division can be generated, a certain frequency spreading function can be generated, and the electromagnetic interference to a system is reduced.
Drawings
FIG. 1 is a flow chart of a method for generating a peripheral clock of a digital chip according to the present invention;
FIG. 2 is a block diagram of the present invention;
FIG. 3 is a schematic block diagram of a system for generating a digital chip peripheral clock according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The first embodiment is as follows:
as shown in fig. 1 and 2, a method for generating a digital chip peripheral clock includes the following steps:
s1, selecting an N-bit register from a register N1 to a register Nn from a low bit to a high bit, wherein N is a positive integer;
step S2, respectively assigning initial values of 0 or 1 to each bit register during initialization;
step S3, setting the period length of the peripheral clock to be generated as m, wherein m is less than or equal to n;
step S4, when generating the peripheral clock, the reference high frequency clock frequency is f; when an x-th high-frequency reference clock signal is received, the output of the peripheral clock generator is an initial value of a register Nx, wherein x is a positive integer from 1 to m, and the initial value from the register N1 to the register Nm forms a peripheral clock signal;
and step S5, when the mth high-frequency reference clock signal is received, counting the high-frequency reference clock signal again, executing S4 and S5, and continuing to generate the peripheral clock signal.
The peripheral clock generated by the invention has more free ends, and the frequency and the duty ratio of the generated peripheral clock can be adjusted by adjusting the initial value of the bit register, so that fractional frequency division can be generated, a certain frequency spreading function can be generated, and the electromagnetic interference to a system is reduced.
In the example, the initial value of the n-bit register forms one or more of a rising sequence, a falling sequence and a common sequence; when the initial values of the two adjacent registers are 0 and 1 respectively, the initial values of the two adjacent registers form a rising sequence; when the initial values of the two adjacent registers are 1 and 0 respectively, the initial values of the two adjacent registers form a descending sequence; when the initial value of the adjacent three-bit register is 0 or 1 at the same time, the initial value of the adjacent two-bit register is in a common sequence.
In step S2, during initialization, if the initial values of the register N1 to the register Nm include y rising sequences, the frequency of the generated peripheral clock signal is f × y/m, where y is a positive integer not greater than m, and then a fraction is obtained. When m is set to be divisible by y, the peripheral clock signal generated is an m/y integer division of the high frequency reference clock f.
In this example, the initial values of the n-bit registers form a rising sequence and a falling sequence, and the duty cycle of the generated peripheral clock signal is adjusted by adjusting the interval between the rising sequence and the falling sequence.
The initial values of the n-bit registers form a rising sequence and a falling sequence, and the intervals between the rising sequence and the falling sequence are adjusted to be equal or unequal, so that the frequency of the generated peripheral clock signal jumps around f multiplied by y/m, and the electromagnetic interference on the system is reduced.
Therefore, the invention controls the frequency of the external clock signal by the initialization mode of the double-bit sequence combination (the initial value of the n-bit register forms a rising sequence and a falling sequence); controlling the duty ratio of an external clock signal by an initialization mode of a dibit sequence combination; controlling the spectrum spread of the external clock signal by an initialization mode of the dibit sequence combination; the electromagnetic interference of the peripheral clock to the system is reduced by the initialization mode of the double-bit sequence combination; the denominator control of the fractional division is performed by a variable high frequency reference clock period.
In summary, compared with the prior art, the method of the present invention has the following advantages:
the method has more degrees of freedom for clock waveforms generated by frequency division, can adjust the frequency of peripheral clock signals, duty ratio and fractional frequency division on certain precision, and solves the problem that the original method can only realize integer frequency division and cannot adjust the duty ratio.
Example two:
as shown in fig. 2 and fig. 3, a system for generating a digital chip peripheral clock includes a main control unit, a register unit, a reference high frequency clock, a clock counter, and a peripheral clock generator, which are electrically connected to the main control unit, respectively, and in this example, a multi-way selection switch is further included, and an initial value of the output one way of register is determined by the multi-way selection switch; the register unit comprises N-bit registers, wherein the N-bit registers are from a low bit to a high bit from a register N1 to a register Nn; when the main control unit is initialized, an initial value of 0 or 1 is respectively assigned to each bit register; wherein the reference high-frequency clock is used for outputting a reference high-frequency clock signal with the frequency f; the clock counter is used for counting a reference high-frequency clock signal output by the reference high-frequency clock; the peripheral clock generator is used for outputting an initial value of a register Nx when an x-th high-frequency reference clock signal is received, wherein x is a positive integer from 1 to m, and the initial value from the register N1 to the register Nm forms a peripheral clock signal; and after the mth high-frequency reference clock signal is received, the main control unit clears the control clock counter and counts again, and the peripheral clock generator continues to generate the peripheral clock signal.
The system also comprises a frequency setting unit electrically connected with the main control unit, wherein the frequency setting unit transmits corresponding frequency electric signals to the main control unit according to the frequency of peripheral clock signals to be generated, the frequency electric signals comprise initial values of all registers, and the main control unit sets the initial values of all the registers during initialization according to the received frequency electric signals. When the peripheral clock frequency to be generated is f multiplied by y/m, fractional frequency division can be obtained at the moment, wherein y is a positive integer not greater than m; the frequency electric signal comprises y ascending sequences from setting the register N1 to the initial value of the register Nm, and the initial values of the adjacent two-bit registers form ascending sequences when the initial values of the adjacent two-bit registers are 0 and 1 respectively.
The system also comprises a duty ratio adjusting unit which is electrically connected with the main control unit, wherein the duty ratio adjusting unit transmits a corresponding adjusting electric signal to the main control unit according to the duty ratio of a peripheral clock to be generated, the adjusting electric signal is the interval between a rising sequence and a falling sequence formed by the initial values of the registers, and when the initial values of two adjacent registers are respectively 1 and 0, the initial values of the two adjacent registers form a falling sequence; the main control unit sets the initial value of each register during initialization according to the received adjusting electric signal.
In the system for generating the digital chip peripheral clock, the control unit gives an initial value of 0 or 1 to each bit register when initializing, and sets a peripheral clock period to be generated, so that the clock counter counts reference high-frequency clock signals according to the period. The control unit controls the peripheral clock generator to output the initial value of the register of the corresponding bit according to the counting of the clock counter, and the peripheral clock generator generates the required peripheral clock signal after the counting of the clock counter is finished. At the moment, the clock counter is cleared and counts again, and the peripheral clock generator continues to output peripheral clock signals. Therefore, the invention can generate fractional frequency division, adjustable duty ratio, adjustable frequency and certain spread spectrum function, and reduce the electromagnetic interference to the system.
According to different initial value settings and m selection of different n-bit registers, different peripheral clock updates can be generated; the maximum denominator of the fractional division is determined by n.
The above-described preferred embodiments of the present invention are not intended to limit the present invention, and any modifications, equivalent methods for generating a peripheral clock of a digital chip, and system improvements, made within the spirit and principle of the present invention, should be included in the scope of the present invention.
Claims (10)
1. A method for generating a digital chip peripheral clock is characterized by comprising the following steps:
s1, selecting an N-bit register from a register N1 to a register Nn from a low bit to a high bit, wherein N is a positive integer;
s2, respectively assigning initial values of 0 or 1 to each bit register during initialization;
s3, setting the period length of the peripheral clock to be generated as m, wherein m is less than or equal to n;
s4, when generating the peripheral clock, referring to the high-frequency clock frequency as f; when an x-th high-frequency reference clock signal is received, the output of the peripheral clock generator is an initial value of a register Nx, wherein x is a positive integer from 1 to m, and the initial value from the register N1 to the register Nm forms a peripheral clock signal;
and S5, when the mth high-frequency reference clock signal is received, counting the high-frequency reference clock signal again, executing S4 and S5, and continuously generating the peripheral clock signal.
2. The method for generating the peripheral clock of the digital chip according to claim 1, wherein the initial value of the n-bit register forms one or more of a rising sequence, a falling sequence and a normal sequence;
when the initial values of the two adjacent registers are 0 and 1 respectively, the initial values of the two adjacent registers form a rising sequence;
when the initial values of the two adjacent registers are 1 and 0 respectively, the initial values of the two adjacent registers form a descending sequence;
when the initial values of the two adjacent registers are 0 or 1 at the same time, the initial values of the two adjacent registers form a common sequence.
3. The method of claim 2, wherein in step S2, if y rising sequences are included in the initial values of the registers N1 to Nm during initialization, the frequency of the generated peripheral clock signal is f × y/m, where y is a positive integer not greater than m.
4. The method of claim 3, wherein the peripheral clock signal is divided by an integer m/y of the high frequency reference clock f by setting m to be divisible by y.
5. The method of claim 3, wherein the initial values of the n-bit registers form a rising sequence and a falling sequence, and the duty cycle of the generated peripheral clock signal is adjusted by adjusting the interval between the rising sequence and the falling sequence.
6. The method for generating a peripheral clock of a digital chip according to claim 3, wherein the initial values of the n-bit registers form a rising sequence and a falling sequence, and the intervals between the rising sequence and the falling sequence are adjusted to be equal or unequal, so that the frequency of the generated peripheral clock signal is shifted around f x y/m.
7. A system for generating a digital chip peripheral clock is characterized by comprising a main control unit, a register unit, a reference high-frequency clock, a clock counter and a peripheral clock generator, wherein the register unit, the reference high-frequency clock, the clock counter and the peripheral clock generator are respectively and electrically connected with the main control unit;
the register unit comprises N-bit registers from a low bit to a high bit, namely a register N1 to a register Nn; when the main control unit is initialized, initial values of 0 or 1 are respectively assigned to each bit register;
the reference high-frequency clock is used for outputting a reference high-frequency clock signal with the frequency f;
the clock counter is used for counting a reference high-frequency clock signal output by the reference high-frequency clock;
the peripheral clock generator is used for outputting an initial value of a register Nx when an x-th high-frequency reference clock signal is received, wherein x is a positive integer from 1 to m, and the register N1 to the initial value of the register Nm form a peripheral clock signal;
and after the mth high-frequency reference clock signal is received, the main control unit controls the clock counter to clear and count again, and the peripheral clock generator continues to generate a peripheral clock.
8. The system for generating a peripheral clock of a digital chip according to claim 7, further comprising a frequency setting unit electrically connected to the main control unit, wherein the frequency setting unit transmits a corresponding frequency electrical signal to the main control unit according to a frequency of a peripheral clock signal to be generated, the frequency electrical signal includes an initial value of each register, and the main control unit sets the initial value of each register during initialization according to the received frequency electrical signal.
9. The system for generating a peripheral clock of a digital chip according to claim 8, wherein the peripheral clock to be generated has a frequency of f x y/m, where y is a positive integer no greater than m; the frequency electric signal comprises y rising sequences from the setting register N1 to the initial value of the register Nm, and when the initial values of two adjacent registers are 0 and 1 respectively, the initial values of the two adjacent registers form the rising sequences.
10. The system for generating a peripheral clock of a digital chip according to claim 8, further comprising a duty ratio adjusting unit electrically connected to the main control unit, wherein the duty ratio adjusting unit transmits a corresponding adjusting electrical signal to the main control unit according to a duty ratio of a peripheral clock signal to be generated, the adjusting electrical signal is an interval between a rising sequence and a falling sequence formed by initial values of the registers, and when the initial values of two adjacent registers are 1 and 0, the initial values of the two adjacent registers form a falling sequence;
and the main control unit sets the initial value of each register during initialization according to the received adjusting electric signal.
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| CN110221650A (en) * | 2019-06-18 | 2019-09-10 | 中国人民解放军国防科技大学 | Clock generator suitable for high-performance network processor chip |
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- 2020-07-24 CN CN202010719740.6A patent/CN111600604A/en active Pending
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| CN1460328A (en) * | 2001-03-30 | 2003-12-03 | 皇家菲利浦电子有限公司 | Baud rate generator with fractional divider |
| US20050253632A1 (en) * | 2003-10-14 | 2005-11-17 | Fahim Amr M | Low-power direct digital synthesizer with analog interpolation |
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Application publication date: 20200828 |