CN111599856B - Double-channel enhanced quasi-vertical structure GaN-based JFET and preparation method thereof - Google Patents

Double-channel enhanced quasi-vertical structure GaN-based JFET and preparation method thereof Download PDF

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CN111599856B
CN111599856B CN202010459159.5A CN202010459159A CN111599856B CN 111599856 B CN111599856 B CN 111599856B CN 202010459159 A CN202010459159 A CN 202010459159A CN 111599856 B CN111599856 B CN 111599856B
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CN111599856A (en
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郭慧
陈敦军
张�荣
郑有炓
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Nanjing University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H01L29/66909—Vertical transistors, e.g. tecnetrons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66924—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with an active layer made of a group 13/15 material

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Abstract

The invention discloses a double-channel enhanced quasi-vertical GaN-based JFET (junction field Effect transistor), which is applied to n‑The upper left and right regions of the GaN layer form two double channels formed by two p-n junctions parallel to the growth direction, each n being‑-the GaN channel is sandwiched between two p-GaN layers, n‑The GaN channel is in the pinch-off state of the p-n built-in electric field at zero bias. And its preparing process are also disclosed. The device adjusts parameters such as the width and the doping concentration of an n-type GaN channel, so that the n-type channel under zero bias is in a pinch-off state caused by an electric field built in a p-n junction, and the channel can be in a conducting state only by applying forward bias, namely the device has positive threshold voltage. Meanwhile, the double channels ensure the large current output of the device.

Description

Double-channel enhanced quasi-vertical structure GaN-based JFET and preparation method thereof
Technical Field
The invention relates to a double-channel enhanced quasi-vertical GaN-based JFET and a preparation method thereof, and belongs to the technical field of semiconductor devices.
Background
The power semiconductor device is used as a core device of a power electronic system such as power conversion, a control circuit and power management, and is widely applied to important fields such as power transmission, transportation and consumer electronics. The GaN-based junction field effect transistor has the advantages of high working frequency, high input impedance, low on-resistance, high power density, high breakdown voltage and the like, so that the GaN-based junction field effect transistor has important application in the fields of variable resistors and power amplifiers. JFETs are typically depletion mode devices that are on-state at zero bias, and for power electronics applications, power semiconductor devices are often required to be enhancement mode devices, otherwise the design difficulty of the drive circuit is increased and the off-state loss of the power semiconductor device is increased.
Disclosure of Invention
The invention aims to provide a double-channel enhancement type quasi-vertical structure GaN-based JFET (junction field effect transistor), wherein the JFET device has large current output.
The purpose of the invention is realized by the following technical scheme:
a double-channel enhancement type GaN-based JFET with a quasi-vertical structure sequentially comprises the following structures:
a substrate;
n formed on the surface of the substrate+A GaN layer and a layer formed on n+-a drain electrode on the GaN layer;
at n+N formed on the surface of the GaN layer--a GaN layer;
at n-The upper left and right regions of the GaN layer form two double channels formed by two p-n junctions parallel to the growth direction, each n being--the GaN channel is sandwiched between two p-GaN layers, n--the GaN channel is in a pinch-off state of the p-n built-in electric field at zero bias;
a gate electrode disposed on the p-GaN layer;
growth at n--n on GaN channel+-a GaN layer;
a source electrode provided at n--n on GaN channel+-a GaN layer.
The invention also discloses a preparation method of the double-channel enhanced quasi-vertical structure GaN-based JFET, which comprises the following steps:
(1) firstly, a layer of n is epitaxially grown on a substrate by utilizing an MOCVD system+A GaN layer followed by an epitaxial layer of n--a GaN layer followed by a further p-GaN layer to form a GaN epitaxial wafer;
(2) depositing a mask layer on the surface of a GaN epitaxial wafer by using a PECVD method, spin-coating a photoresist layer on the surface of the mask layer, forming a photoetching pattern by exposure, development and baking, then patterning the mask layer by using the photoresist as a mask by using an RIE (reactive ion etching) method on the basis, and finally removing the photoresist on the epitaxial wafer by using acetone;
(3) etching two grooves on the GaN epitaxial wafer by using an ICP (inductively coupled plasma) chlorine-based plasma etching method;
(4) growing n in the groove through mask selection by using MBE method--GaN channel and n+A GaN layer such that n-GaN filling the etched-away regions forms a p-n junction with the p-GaN layer, n+The GaN layer is used for forming ohmic contact of a source electrode, and the mask layer is removed after growth is completed;
(5) use ofUsing the photoresist as a mask, etching drain electrode deposition regions at two sides of the device by ICP etching to n+-a GaN layer;
(6) evaporating and plating a source electrode and a drain electrode by adopting electron beam evaporation, and annealing to form ohmic contact;
(7) and evaporating a gate electrode on the surface of the p-GaN layer by adopting electron beam evaporation, and annealing.
Preferably, in step (1), n is epitaxially grown to a thickness of 1 to 4 μm+A GaN layer, epitaxial with n of 2-10 μm-A GaN layer, a p-GaN layer of 0.5-2 μm epitaxy, where n+GaN layer doping concentration 1 x 1018-1*1019cm-3，n--doping concentration of GaN layer of 1 x 1016-8*1016cm-3The doping concentration of the p-GaN layer is 1 x 1017-8*1017cm-3。
Preferably, the mask layer in the step (2) is SiN or SiO2The thickness is 200-500 nm.
Preferably, the depth of the grooves in step (3) is the same as the thickness of the p-GaN layer to ensure that the p-GaN is completely etched away, the width is 0.2-0.8 μm, and the distance between every two grooves is 0.5-5 μm.
Preferably, the doping concentration of n-GaN in the step (4) is 1 x 1016-8*1016cm-3，n+The doping concentration of GaN is 1 x 1018-1*1019cm-3The mask layer is removed using HF.
Preferably, step (5) may be performed by 0.2 to 0.5. mu.m.
Preferably, in the step (6), the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with the thickness of 30/150/50/100nm, and N is at 850 ℃ after evaporation2Annealing in the atmosphere for 30 s.
Preferably, in step (7), the gate electrode is a Ni/Au multilayer metal with a thickness of 20/20nm, and is annealed in an air atmosphere at 500 ℃ for 10min after evaporation.
The invention has the beneficial effect that the enhancement type GaN-based junction field effect transistor (GaN-JFET) is realized by utilizing multiple channels. The traditional junction field effect transistor adopts a wide single channel for ensuring large output current, is in a depletion mode,the on state at zero bias increases the off-state loss of the power semiconductor device and is unsafe to use. Not only do enhancement devices do not suffer from these problems, but they also simplify the drive circuitry. Meanwhile, the parallel multi-channel ensures large output current of the GaN-based junction field effect transistor; and a quasi-vertical structure is adopted, a conductive GaN homogeneous substrate is not needed, and the cost of the device can be reduced. Different from the traditional method of etching the channel layer and then carrying out the regrowth of the p-GaN layer, n-The regrowth of the GaN layer is homoepitaxial growth, so that a regrowth interface with high quality can be ensured, and the reliability of the device is improved. Simultaneously, p-GaN and n-The interface of the GaN layer in the vertical direction is obtained by in-situ growth, the defect introduced by etching is avoided at the most critical p-n junction interface of the device, and the depletion and pinch-off of a channel are facilitated and the on-state leakage current of the device is reduced.
Drawings
Fig. 1 is a schematic structural view of a GaN epitaxial wafer obtained in step (1) of example 1.
Fig. 2 is a schematic structural view of the GaN epitaxial wafer obtained in step (2) of example 1.
Fig. 3 is a schematic structural view of the GaN epitaxial wafer obtained in step (3) of example 1.
Fig. 4 is a schematic structural view of the GaN epitaxial wafer obtained in step (4) of example 1.
Fig. 5 is a schematic structural view of the GaN epitaxial wafer obtained in step (5) of example 1.
Fig. 6 is a schematic structural view of the GaN-based JFET obtained in step (7) of example 1.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
A preparation method of a double-channel enhanced quasi-vertical structure GaN-based JFET comprises the following steps:
(1) firstly, a layer of n with the thickness of 1 mu m is epitaxially grown on a substrate 1 by utilizing an MOCVD system+ A GaN layer 2 followed by an epitaxial layer of n with a thickness of 2 μm-A GaN channel layer 3 followed by an epitaxial layer 4 of p-GaN of thickness 0.5 μm, as shown in FIG. 1, where n is+GaN layer doping concentration 1 x 1018cm-3，n--doping concentration of GaN layer 4 x 1016cm-3The doping concentration of the p-GaN layer is 1 x 1017cm-3；
(2) Depositing a mask layer 5 with the thickness of 200nm on the surface of the GaN epitaxial wafer by using a PECVD method, as shown in figure 2, spin-coating a layer of photoresist on the surface of the mask layer, forming a photoetching pattern through exposure, development and baking, then patterning the mask layer by using an RIE (reactive ion etching) method by using the photoresist as a mask on the basis, and finally removing the photoresist on the epitaxial wafer by using acetone;
(3) etching two grooves 6 with the depth of 0.5 μm on the GaN epitaxial wafer by using an ICP (inductively coupled plasma) chlorine-based plasma etching method, wherein the width of each groove is 0.2 μm, and the distance between every two grooves is 0.5 μm, as shown in FIG. 3;
(4) growing n in the groove through mask selection by using MBE method-GaN channel 7 and n+ A GaN layer 8, such that n-GaN filling the etched-away regions forms a p-n junction with the p-GaN layer, n+-GaN layer for forming ohmic contact to source, n-GaN having a doping concentration of 1 x 1016cm-3，n+Doping concentration of GaN 1 x 1018cm-3Removing the mask layer by using HF after the growth is finished, as shown in FIG. 4;
(5) using photoresist as mask, adopting ICP etching method to etch drain electrode deposition regions at two sides of the device, etching depth to n+A GaN layer, which may be over-etched by 0.2-0.5 μm, as shown in fig. 5;
(6) evaporating and plating a source electrode 9 and a drain electrode 10 by adopting electron beam evaporation, wherein the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with the thickness of 30/150/50/100nm, and the N is 850 ℃ after evaporation2Annealing in atmosphere for 30s to form ohmic contactContacting;
(7) and evaporating a gate electrode 11 on the surface of the p-GaN layer by adopting electron beam evaporation, wherein the gate electrode is made of Ni/Au multilayer metal and has the thickness of 20/20nm, and annealing for 10min in an air atmosphere at 500 ℃, as shown in FIG. 6.
Example 2
A preparation method of a double-channel enhanced quasi-vertical structure GaN-based JFET comprises the following steps:
(1) firstly, a layer of n with the thickness of 4 mu m is epitaxially grown on a substrate 1 by utilizing an MOCVD system+A GaN layer followed by an epitaxial layer of n with a thickness of 10 μm-A GaN channel layer followed by an epitaxial layer of p-GaN with a thickness of 2 μm, where n+GaN layer doping concentration 1 x 1019cm-3，n--doping concentration of GaN layer 1 x 1016cm-3The doping concentration of the p-GaN layer is 8 x 1017cm-3；
(2) Depositing a mask layer with the thickness of 500nm on the surface of a GaN epitaxial wafer by using a PECVD method, spin-coating a layer of photoresist on the surface of the mask layer, forming a photoetching pattern by exposure, development and baking, then patterning the mask layer by using the photoresist as a mask by using an RIE (reactive ion etching) method on the basis, and finally removing the photoresist on the epitaxial wafer by using acetone;
(3) etching two grooves with the depth of 2 microns on the GaN epitaxial wafer by using an ICP (inductively coupled plasma) chlorine-based plasma etching method, wherein the width of each groove is 0.8 micron, and the distance between every two grooves is 5 microns;
(4) growing n in the groove through mask selection by using MBE method--a GaN channel and n+A GaN layer such that n-GaN filling the etched-away regions forms a p-n junction with the p-GaN layer, n+-GaN layer for forming ohmic contact to source, n-GaN having a doping concentration of 8 x 1016cm-3，n+The doping concentration of GaN is 1 x 1019cm-3Removing the mask layer by using HF after the growth is finished;
(5) using photoresist as mask, adopting ICP etching method to etch drain electrode deposition region at two sides of device, etching depth to n+-a GaN layer, over-etched 0.2-0.5 μm;
(6) evaporating and plating a source electrode and a drain electrode by adopting electron beam evaporation, wherein the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with the thickness of 30/150/50/100nm, and the N temperature is 850 ℃ after evaporation2Annealing for 30s in the atmosphere to form ohmic contact;
(7) evaporating and evaporating a gate electrode by using an electron beam, wherein the gate electrode is made of Ni/Au multilayer metal and has the thickness of 20/20nm, and annealing for 10min in an air atmosphere at 500 ℃.
Example 3
A preparation method of a double-channel enhanced quasi-vertical structure GaN-based JFET comprises the following steps:
(1) firstly, a layer of n with the thickness of 3 mu m is epitaxially grown on a substrate 1 by utilizing an MOCVD system+A GaN layer followed by an epitaxial layer of n with a thickness of 5 μm-A GaN channel layer followed by an epitaxial layer of p-GaN with a thickness of 1 μm, where n+GaN layer doping concentration of 5 x 1018cm-3，n--doping concentration of GaN layer of 8 x 1016cm-3The doping concentration of the p-GaN layer is 4 x 1017cm-3；
(2) Depositing a mask layer with the thickness of 400nm on the surface of a GaN epitaxial wafer by using a PECVD method, spin-coating a layer of photoresist on the surface of the mask layer, forming a photoetching pattern by exposure, development and baking, then patterning the mask layer by using the photoresist as a mask by using an RIE (reactive ion etching) method on the basis, and finally removing the photoresist on the epitaxial wafer by using acetone;
(3) etching two grooves with the depth of 1.0 mu m on the GaN epitaxial wafer by using an ICP (inductively coupled plasma) chlorine-based plasma etching method, wherein the width of each groove is 0.5 mu m, and the distance between every two grooves is 3 mu m;
(4) growing n in the groove through mask selection by using MBE method--GaN channel and n+A GaN layer such that n-GaN filling the etched-away regions forms a p-n junction with the p-GaN layer, n+-GaN layers for forming ohmic contacts to the source, the doping concentration of n-GaN being 4 x 1016cm-3，n+The doping concentration of GaN is 5 x 1018cm-3Removing the mask layer by using HF after the growth is finished;
(5) using photoresist as mask, adopting ICP etching method to etch drain electrode deposition region at two sides of device, etching depth to n+-a GaN layer, over-etched 0.2-0.5 μm;
(6) evaporating and plating a source electrode and a drain electrode by adopting electron beam evaporation, wherein the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal with the thickness of 30/150/50/100nm, and the N temperature is 850 ℃ after evaporation2Annealing for 30s in the atmosphere to form ohmic contact;
(7) evaporating and plating a gate electrode by adopting electron beam evaporation, wherein the gate electrode is made of Ni/Au multilayer metal and has the thickness of 20/20nm, and annealing for 10min in an air atmosphere at 500 ℃.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims (9)

1. A double-channel enhancement type quasi-vertical structure GaN-based JFET sequentially comprises the following structures:
a substrate;
n formed on the surface of the substrate+-a GaN layer and a layer formed on n+-a drain electrode on the GaN layer;
at n+N formed on the surface of the GaN layer--a GaN layer;
at n-The upper left and right regions of the GaN layer form two double channels formed by two p-n junctions parallel to the growth direction, each n being--the GaN channel is sandwiched between two p-GaN layers, n--the GaN channel is in a pinch-off state of the p-n built-in electric field at zero bias;
a gate electrode disposed on the p-GaN layer;
growth at n--n on GaN channel+-a GaN layer;
a source electrode provided at n--n on GaN channel+-a GaN layer.
2. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET according to claim 1, comprising the following steps of:
(1) firstly, a layer of n is epitaxially grown on a substrate by utilizing an MOCVD system+A GaN layer followed by an epitaxial layer of n--a GaN layer followed by a further p-GaN layer to form a GaN epitaxial wafer;
(2) depositing a mask layer on the surface of a GaN epitaxial wafer by using a PECVD method, spin-coating a photoresist layer on the surface of the mask layer, forming a photoetching pattern by exposure, development and baking, then patterning the mask layer by using the photoresist as a mask by using an RIE (reactive ion etching) method on the basis, and finally removing the photoresist on the epitaxial wafer by using acetone;
(3) etching two grooves on the GaN epitaxial wafer by using an ICP (inductively coupled plasma) chlorine-based plasma etching method;
(4) growing n in the groove through mask selection by using MBE method--a GaN channel and n+A GaN layer such that n-GaN filling the etched-out areas forming a p-n junction with the p-GaN layer, n+The GaN layer is used for forming ohmic contact of a source electrode, and the mask layer is removed after growth is completed;
(5) using photoresist as mask, adopting ICP etching method to etch drain electrode deposition region at two sides of device, etching depth to n+-a GaN layer;
(6) evaporating and plating a source electrode and a drain electrode by adopting electron beam evaporation, and annealing to form ohmic contact;
(7) and evaporating and plating a gate electrode by adopting electron beam evaporation, and annealing.
3. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET according to claim 2, wherein the method comprises the following steps: extending n of 1-4 mu m in step (1)+A GaN layer, epitaxial with n of 2-10 μm-A GaN layer, a p-GaN layer of 0.5-2 μm epitaxy, where n+GaN layer doping concentration 1 x 1018-1*1019cm-3，n--doping concentration of GaN layer of 1 x 1016-8*1016cm-3The doping concentration of the p-GaN layer is 1 x 1017-8*1017cm-3。
4. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET according to claim 2, wherein the method comprises the following steps: the mask layer in the step (2) is SiN or SiO2The thickness is 200-500 nm.
5. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET of claim 3, wherein the method comprises the following steps: in the step (3), the depth of the grooves is the same as the thickness of the p-GaN layer so as to ensure that the p-GaN is completely etched, the width of the grooves is 0.2-0.8 μm, and the distance between every two grooves is 0.5-5 μm.
6. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET according to claim 4, wherein the method comprises the following steps: n in step (4)-Doping concentration of GaN 1 x 1016-8*1016cm-3，n+The doping concentration of GaN is 1 x 1018-1*1019cm-3The mask layer is removed using HF.
7. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET of claim 6, wherein the method comprises the following steps: in the step (5), the thickness of the coating can be 0.2-0.5 μm.
8. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET of claim 7, wherein the method comprises the following steps: in the step (6), the source electrode and the drain electrode are Ti/Al/Ni/Au multilayer metal, the thickness is 30/150/50/100nm, and N is at 850 ℃ after evaporation2Annealing in the atmosphere for 30 s.
9. The method for preparing the double-channel enhancement type quasi-vertical structure GaN-based JFET of claim 8, wherein the double-channel enhancement type quasi-vertical structure GaN-based JFET comprises: in the step (7), the grid electrode is made of Ni/Au multilayer metal, the thickness is 20/20nm, and the annealing is carried out for 10min in the air atmosphere at 500 ℃ after the vapor deposition.
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