CN111599820B - Semiconductor process and semiconductor structure - Google Patents
Semiconductor process and semiconductor structure Download PDFInfo
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- CN111599820B CN111599820B CN202010478470.4A CN202010478470A CN111599820B CN 111599820 B CN111599820 B CN 111599820B CN 202010478470 A CN202010478470 A CN 202010478470A CN 111599820 B CN111599820 B CN 111599820B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application provides a semiconductor process and a semiconductor structure. The process comprises the following steps: a first stacking structure is formed on the substrate, the stacking structure comprises sacrificial layers and insulating medium layers which are alternately arranged, and channel holes and virtual channel holes are formed in the stacking structure; filling, namely filling sacrificial materials in the channel hole and the virtual channel hole, forming a first filling part in the channel hole, and forming a second filling part in the virtual channel hole, wherein the sacrificial materials are different from the sacrificial layer and the insulating medium layer, and the sacrificial materials are insulating materials; a removing step of removing the first filling part; and a subsequent stacking structure forming step of forming a second stacking structure on the structure from which the first filling part is removed, wherein the channel hole in the second stacking structure is communicated with the channel hole in the first stacking structure. The process solves the problem that the process for avoiding the deformation of the virtual channel hole formed by the multiple stacking technology in the prior art is complex.
Description
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a semiconductor process and a semiconductor structure.
Background
With the development of the 3D NAND technology and the development of the stacking technology, the multi-stacking technology can well solve the challenge of deep hole etching. However, the dummy trench hole formed in the step region by multiple etching in the multiple stack technique may be deformed, which may cause leakage if serious.
In the prior art, a photoetching process is added before the stack structure is etched, the stack structure of a virtual (dummy) area is not directly etched after a channel hole and a virtual channel hole are formed, but forms a photoresist layer or a hard mask layer on the stacked structure, and then carries out photoetching to form a pattern layer which shields the virtual region and exposes the non-virtual region, since the pattern layer blocking the dummy region needs to be thick, the photoresist layer or the hard mask layer needs to be thick, thus, the time for removing the photoresist layer or the hard mask layer above the non-virtual area is longer, the long-time developing and etching process easily denatures the pattern layer above the virtual area, and is difficult to remove subsequently, and moreover, in the process, the photoresist or the hard mask material enters the channel hole and the virtual channel hole which are formed in advance, and is difficult to remove subsequently. The process is complex and difficult.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The main objective of the present application is to provide a semiconductor process and a semiconductor structure, so as to solve the problem in the prior art that the process for avoiding the deformation of the virtual channel hole formed by the multiple stacking technique is complicated.
In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor process including: a first stacking structure forming step of forming a first stacking structure on a substrate, the stacking structure having a channel hole and a dummy channel hole therein; filling sacrificial materials into the channel holes and the dummy channel holes, forming first filling parts in the channel holes, and forming second filling parts in the dummy channel holes, wherein the sacrificial materials are insulating materials; a removing step of removing the first filling part; and a subsequent stacking structure forming step of forming a second stacking structure on the structure from which the first filling part is removed, wherein the channel hole in the second stacking structure is communicated with the channel hole in the previous stacking structure, and the first stacking structure and the second stacking structure respectively comprise sacrificial layers and insulating medium layers which are alternately arranged.
Further, the forming of the first stacked structure includes: providing the substrate; forming a first preparation stacking structure on the substrate, wherein the first preparation stacking structure comprises preparation sacrificial layers and preparation insulating medium layers which are formed alternately; and etching and removing part of the preparation sacrificial layer and the preparation insulating medium layer to form the first stacked structure with the channel hole and the virtual channel hole.
Further, the first filling part formed in the filling step has a gap therein.
Further, the filling step includes: filling the channel hole and the dummy channel hole with the sacrificial material; carrying out planarization treatment on the surface of the structure filled with the sacrificial material; the remaining sacrificial material in the trench hole forms the first filling portion, and the remaining sacrificial material in the dummy trench hole forms the second filling portion.
Further, the removing step includes: forming a mask layer with a preset pattern on the surface of the structure filled with the sacrificial material, wherein the mask layer covers the surface of the first filling part, and the mask layer does not cover the surface of the second filling part; performing predetermined treatment on the sacrificial material in the second filling part, so that the sacrificial material in the second filling part forms a predetermined sacrificial material, wherein the etching selection ratio of the sacrificial material to the predetermined sacrificial material is more than 100; removing the mask layer; and removing the first filling part.
Further, performing a predetermined process on the sacrificial material in the second filling portion so that the sacrificial material in the second filling portion forms a predetermined sacrificial material includes: and injecting predetermined ions into the sacrificial material in the second filling part to form the predetermined sacrificial material, wherein elements corresponding to the predetermined ions are different from elements in the sacrificial material.
Further, after the second stack structure is formed, the semiconductor process further includes: repeating the filling step, the removing step and the subsequent stacked structure forming step at least once in sequence until a predetermined number of the sacrificial layers are formed.
According to another aspect of the present application, a semiconductor structure is provided, which is fabricated by any one of the semiconductor processes.
According to another aspect of the present application, there is provided a semiconductor structure comprising: a substrate; the stacked structures are sequentially stacked on the surface of the substrate, each stacked structure comprises a metal grid and an insulating medium layer which are alternately arranged, a channel hole and a virtual channel hole are formed in each stacked structure, and the channel holes of two adjacent stacked structures are communicated; and the second filling part comprises a sacrificial material, the second filling part is positioned in the first virtual channel hole, the first virtual channel hole is the virtual channel hole with the minimum distance from the substrate, and the sacrificial material is an insulating material.
Further, the number of the stacked structures is N, the number of the second filling portions is N-1, the N-1 second filling portions are located in the first N-1 virtual channel holes, one second filling portion is located in one virtual channel hole, the first N-1 virtual channel holes are N-1 virtual channel holes counted in sequence from the first virtual channel hole along the direction away from the substrate, and N is a positive integer greater than 2.
Use the technical scheme of this application, among the above-mentioned semiconductor technology, at first, form first stacked structure on the basement, have channel hole and virtual channel hole in the stacked structure, later, pack the sacrificial material in channel hole and virtual channel hole, form first filling portion in the channel hole, form second filling portion in the virtual channel hole, then, get rid of first filling portion, and finally, form second stacked structure on getting rid of the structure of first filling portion, channel hole in the second stacked structure and the channel hole intercommunication in the first stacked structure. In the process, before the second stacked structure is formed, the second filling part is formed in the virtual channel in the first stacked structure through the filling step and the removing step, and the hole channel hole in the first stacked structure is not provided with the filling part, so that in the process of forming the second stacked structure, the later formed virtual channel hole cannot deform with the second filling part, thereby avoiding the electric leakage problem caused by deformation, compared with the process for avoiding the deformation of the virtual channel hole formed by the multiple stacking technology in the prior art, the process is simpler, a thicker photoresist layer or a hard mask layer is not required to be formed, a longer removing time is not required, the problem that the pattern layer above the virtual area is difficult to remove due to the deformation caused by the longer removing time is further avoided, and due to the first filling part and the second filling part which are formed, the photoresist or the hard mask material cannot enter the virtual channel hole or the channel hole, the problem of subsequent difficult removal is prevented.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a flow diagram of a semiconductor process according to the present application;
FIG. 2 shows a schematic view of a semiconductor structure formed in accordance with a first stacked structure formation step of the present application;
FIG. 3 shows a schematic view of a semiconductor structure formed according to a fill step of the present application;
FIG. 4 shows a schematic view of a semiconductor structure formed according to a removal step of the present application;
FIG. 5 shows a schematic diagram of a semiconductor structure according to the present application; and
FIG. 6 shows a schematic of a 3D NAND according to the present application.
Wherein the figures include the following reference numerals:
10. a substrate; 20. a sacrificial layer; 20', a metal gate; 30. an insulating dielectric layer; 40. a channel hole; 50. a virtual channel hole; 60. a first filling part; 70. a second filling part.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the process of avoiding the deformation of the dummy trench formed by the multiple stacking technique in the prior art is complicated, and in order to solve the above problems, the present application provides a semiconductor process and a semiconductor structure.
Fig. 1 is a flow chart of a semiconductor process according to an embodiment of the invention, as shown in fig. 1, the semiconductor process comprising the steps of:
step S101, a first stacked structure forming step, forming a first stacked structure on a substrate 10, where the stacked structure has a channel hole 40 and a dummy channel hole 50, as shown in fig. 2, and only one channel hole and only one dummy channel hole are shown in fig. 2, and in practical applications, there may be one or more channel holes and one or more dummy channel holes, respectively;
step S102, a filling step, in which a sacrificial material is filled in the channel hole 40 and the dummy channel hole 50, a first filling portion 60 is formed in the channel hole 40, and a second filling portion 70 is formed in the dummy channel hole 50, and the sacrificial material is an insulating material, as shown in fig. 3;
a step S103 of removing the first filling part 60, as shown in fig. 4;
step S104, a subsequent stacked structure forming step, forming a second stacked structure on the structure from which the first filling portion is removed, the channel hole 40 in the second stacked structure and the channel hole 40 in the first stacked structure being communicated with each other, as shown in fig. 5. The first stack structure and the second stack structure respectively include sacrificial layers 20 and insulating dielectric layers 30 alternately disposed,
in the semiconductor process, first, a first stacked structure is formed on a substrate, a channel hole and a virtual channel hole are formed in the stacked structure, then, sacrificial materials are filled in the channel hole and the virtual channel hole, a first filling portion is formed in the channel hole, a second filling portion is formed in the virtual channel hole, then, the first filling portion is removed, finally, a second stacked structure is formed on the structure with the first filling portion removed, and the channel hole in the second stacked structure is communicated with the channel hole in the first stacked structure. In the process, before the second stacked structure is formed, the second filling part is formed in the virtual channel in the first stacked structure through the filling step and the removing step, and the hole channel hole in the first stacked structure is not provided with the filling part, so that in the process of forming the second stacked structure, the later formed virtual channel hole cannot deform with the second filling part, thereby avoiding the electric leakage problem caused by deformation, compared with the process for avoiding the deformation of the virtual channel hole formed by the multiple stacking technology in the prior art, the process is simpler, a thicker photoresist layer or a hard mask layer is not required to be formed, a longer removing time is not required, the problem that the pattern layer above the virtual area is difficult to remove due to the deformation caused by the longer removing time is further avoided, and due to the first filling part and the second filling part which are formed, the photoresist or the hard mask material cannot enter the virtual channel hole or the channel hole, the problem of subsequent difficult removal is prevented.
In fact, in order to further ensure that the process is simple and efficient, in an embodiment of the present application, the sacrificial material is different from the material of the sacrificial layer 20 and the material of the insulating medium layer 30.
In an embodiment of the present application, the forming step of the first stacked structure includes: providing the substrate; forming a first preparation stacking structure on the substrate, wherein the first preparation stacking structure comprises preparation sacrificial layers and preparation insulating medium layers which are formed alternately; and etching and removing part of the preparation sacrificial layer and the preparation insulating medium layer to form the first stacked structure with the channel hole and the virtual channel hole. Specifically, a preliminary sacrificial layer and a preliminary insulating dielectric layer are alternately formed on a substrate to form a first preliminary stacked structure, and then the first preliminary stacked structure is etched to form a first stacked structure having a channel hole and a dummy channel hole, and a subsequent stacked structure is also formed through the above steps.
In an embodiment of the present application, the first filling portion formed in the filling step has a gap therein. Specifically, the first filling part is provided with a gap inside, so that the contact area of the etchant and the first filling part is increased in the removing step, and the efficiency of removing the first filling part is improved.
In an embodiment of the present application, the filling step includes: filling the channel hole and the dummy channel hole with the sacrificial material; carrying out planarization treatment on the surface of the structure filled with the sacrificial material; the remaining sacrificial material in the trench hole forms the first filling portion, and the remaining sacrificial material in the dummy trench hole forms the second filling portion. Specifically, in the filling step, the surface of the structure filled with the sacrificial material is subjected to planarization treatment, so that the surfaces of the first filling part and the second filling part are more flat, the thickness of a mask layer formed on the surface of the first filling part or the second filling part subsequently can be controlled conveniently, the mask layer is prevented from being uneven in thickness, the removal process is prevented from being complicated, and the semiconductor process is further simplified.
In an embodiment of the present application, the removing step includes: forming a mask layer having a predetermined pattern on a surface of the structure filled with the sacrificial material, the mask layer covering a surface of the first filling portion and the mask layer not covering a surface of the second filling portion; performing a predetermined process on the sacrificial material in the second filling portion so that the sacrificial material in the second filling portion forms a predetermined sacrificial material, wherein an etching selection ratio of the sacrificial material to the predetermined sacrificial material is greater than 100; removing the mask layer; the first filling portion is removed to form the structure shown in fig. 4. Specifically, in the removing step, by performing the predetermined treatment on the sacrificial material in the second filling portion, the etching selection ratio of the sacrificial material to the predetermined sacrificial material is greater than 100, that is, the etching selection ratio of the sacrificial material in the first filling portion to the predetermined sacrificial material formed in the second filling portion is greater than 100, so that the second filling portion is not substantially removed by etching while the first filling portion is further removed.
It should be noted that the etching selection ratio of the sacrificial material to the predetermined sacrificial material is not limited to the above range, and can be adjusted by those skilled in the art according to the actual situation.
In one embodiment of the present application, performing a predetermined process on the sacrificial material in the second filling portion so that the sacrificial material in the second filling portion forms a predetermined sacrificial material includes: and implanting predetermined ions into the sacrificial material in the second filling portion to form the predetermined sacrificial material, wherein elements corresponding to the predetermined ions are different from elements in the sacrificial material. Specifically, the predetermined ions are implanted into the sacrificial material in the second filling portion to form the predetermined sacrificial material, and since the elements corresponding to the predetermined ions are different from the elements in the sacrificial material, it is further ensured that the etching selection ratio of the sacrificial material to the predetermined sacrificial material is greater than 100, so that the second filling portion is not substantially removed by etching while the first filling portion is removed.
It should be noted that, a person skilled in the art can select a suitable predetermined ion according to practical situations, so that the etching selection ratio of the sacrificial material to the predetermined sacrificial material is greater than 100, for example, when the sacrificial material is polysilicon, the predetermined ion is a carbon ion. Of course, the method of the predetermined processing is not limited to this, and those skilled in the art may also adopt other methods of the predetermined processing to make the etching selection ratio of the sacrificial material to the predetermined sacrificial material greater than 100.
In an embodiment of the present application, after the forming of the second stacked structure, the semiconductor process further includes: repeating the filling step, the removing step and the subsequent stacking structure forming step at least once in sequence until a predetermined number of the sacrificial layers are formed. Specifically, the filling step, the removing step and the subsequent stacked structure forming step are repeated at least once in sequence, so that the formed virtual trench holes of the semiconductor structure comprise second filling parts, the trench holes of adjacent stacked structures are communicated until a predetermined number of sacrificial layers are formed, and the second filling parts are arranged in other virtual trench holes except the last formed virtual trench hole, so that the problem of deformation between the later formed virtual trench hole and the first formed trench hole is well solved, the problem of electric leakage caused by the deformation is further solved, and the good electrical performance of the device is further ensured.
The embodiment of the application also provides a semiconductor structure, and the semiconductor structure is manufactured by adopting any one of the semiconductor processes.
In the semiconductor structure, a first stacked structure of the semiconductor structure is formed on a substrate and is provided with a channel hole and a virtual channel hole, a first filling part is formed by filling a sacrificial material in the channel hole, a second filling part is formed by filling the sacrificial material in the virtual channel hole, the first filling part is removed before a second stacked structure is formed, a second stacked structure is formed on the structure with the first filling part removed, and the channel hole in the second stacked structure is communicated with the channel hole in the first stacked structure, so that the semiconductor structure is formed. Among the above-mentioned semiconductor construction, the second filling portion prevents that virtual trench hole from taking place to warp to prevent the electric leakage, and the trench hole among the second stacked structure and the trench hole intercommunication among the first stacked structure, thereby solved among the prior art avoid pile up the technique many times and form the virtual trench hole of technique emergence deformation the comparatively complicated problem of technology, and the material of second filling portion is insulating material, further prevents the electric leakage.
It should be noted that the sacrificial layer and the insulating dielectric layer described above in the present application may be any feasible materials, for example, the material of the sacrificial layer may include silicon nitride and/or silicon oxide, and the material of the insulating dielectric layer may include silicon oxide and/or silicon nitride, but they need to be different. For example, the insulating dielectric layer is a silicon dioxide layer, and the sacrificial layer is a silicon nitride layer.
The substrate of the present application may be selected according to the actual requirements of the device, and may include a silicon substrate, a germanium substrate, a silicon germanium substrate, an SOI substrate, a GOI substrate, or the like.
In practical applications, the semiconductor process may further include other process steps, such as: forming a charge blocking layer, a charge trapping layer, a charge tunnel, a channel layer, an isolation layer and a drain contact structure in the channel hole; removing the sacrificial layer to form a gap region; a material for forming a metal gate in the void region, a metal gate, or the like. These steps may be conventional process steps in the art and are not described in detail herein.
It should be noted that the material of each structural layer may also be any feasible material in the prior art, for example, the charge tunneling layer may be silicon dioxide, the channel layer may be a polysilicon layer, the isolation layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.
It should be further noted that the material of the specific charge blocking layer may be any feasible material in the prior art, such as silicon dioxide, etc., and the formation manner of the charge blocking layer may also be any feasible manner in the prior art, and a person skilled in the art may select a suitable method and a suitable material according to practical situations to form the above-mentioned charge blocking layer of the present application. The material of the charge trapping layer includes at least one of a silicon oxide compound, a silicon nitride compound, a silicon oxynitride compound, and a high-K dielectric, but the material of the charge trapping layer is not limited thereto, and may be other suitable materials.
An embodiment of the present application further provides a semiconductor structure, as shown in fig. 6, including:
a substrate 10;
a plurality of stacked structures sequentially stacked on the surface of the substrate 10, each of the stacked structures including alternately arranged metal gates 20' and insulating dielectric layers 30, each of the stacked structures having a channel hole 40 and a dummy channel hole 50 therein, the channel holes 40 of two adjacent stacked structures being communicated;
the second filling portion 70 includes a sacrificial material, the second filling portion 70 is located in a first dummy trench hole, the first dummy trench hole 50 is the dummy trench hole 50 having the smallest distance from the substrate, and the sacrificial material is an insulating material.
In the semiconductor structure, the second filling part is positioned in the first dummy trench hole, and the second filling can prevent the first dummy trench hole from deforming so as to avoid electric leakage, so that the semiconductor structure has good electrical performance.
In an embodiment of the present application, the number of the stacked structures is N, the number of the second filling portions is N-1, N-1 of the second filling portions are located in the first N-1 of the dummy trench holes, one of the second filling portions is located in one of the dummy trench holes, and the first N-1 of the dummy trench holes are N-1 of the dummy trench holes counted in sequence from the first dummy trench hole along a direction away from the substrate, where N is a positive integer greater than 2. Specifically, the number of the stacked structures is N, the number of the second filling portions is N-1, and the N-1 second filling portions are located in the first N-1 virtual trench holes, because the stacked structures are sequentially formed on the substrate, the second filling portions are located in the first N-1 virtual trench holes, that is, the second filling portions are located in the other virtual trench holes except the last formed virtual trench hole, so that the problem of deformation between the later formed virtual trench hole and the first formed trench hole is well solved, the problem of electric leakage caused by the deformation is further solved, and the good electrical performance of the device is further ensured.
It should be noted that the metal gate and the insulating dielectric layer described above in this application may be any feasible material, for example, the material of the metal gate may be a metal material, and the material of the insulating dielectric layer may include silicon oxide and/or silicon nitride.
The substrate of the present application may be selected according to the actual requirements of the device, and may include a silicon substrate, a germanium substrate, a silicon germanium substrate, an SOI substrate, a GOI substrate, or the like.
In practical applications, the semiconductor process may also include other structures, such as: a charge blocking layer, a charge trapping layer, a charge tunneling layer, a channel layer, an isolation layer, and a drain contact structure in the channel hole.
It should be noted that the material of each structural layer may also be any feasible material in the prior art, for example, the charge tunneling layer may be silicon dioxide, the channel layer may be a polysilicon layer, the isolation layer may be silicon dioxide, and the drain contact structure is formed of a polysilicon material. Of course, the materials of these structural layers may be replaced by other suitable materials, which will not be described herein.
It should be further noted that the material of the specific charge blocking layer may be any feasible material in the prior art, such as silicon dioxide, etc., and the formation manner of the charge blocking layer may also be any feasible manner in the prior art, and a person skilled in the art may select a suitable method and a suitable material according to practical situations to form the above-mentioned charge blocking layer of the present application. The material of the charge trapping layer includes at least one of a silicon oxide compound, a silicon nitride compound, a silicon oxynitride compound, and a high-K dielectric, but the material of the charge trapping layer is not limited thereto, and may be other suitable materials.
In order to make the technical solution of the present application more clearly understood by those skilled in the art, the following description will be given by taking a 3D NAND flash memory as an example.
Examples
The semiconductor structure in this embodiment is a 3D NAND flash memory, and the specific manufacturing process thereof includes:
providing the base 10, wherein the base 10 is a monocrystalline silicon substrate;
forming a first preliminary stacked structure on the substrate 10, wherein the first preliminary stacked structure includes preliminary sacrificial layers and preliminary insulating dielectric layers that are alternately formed, and etching away a portion of the preliminary sacrificial layers and the preliminary insulating dielectric layers to form the first stacked structure having the channel holes 40 and the dummy channel holes 50, and the first stacked structure includes sacrificial layers 20 and insulating dielectric layers 30 that are alternately arranged, the insulating dielectric layers are silicon dioxide layers, and the sacrificial layers are silicon nitride layers, as shown in fig. 2;
filling the channel hole 40 and the dummy channel hole 50 with the sacrificial material, planarizing the surface of the structure filled with the sacrificial material, forming the first filling portion 60 by the remaining sacrificial material in the channel hole 40, and forming the second filling portion 70 by the remaining sacrificial material in the dummy channel hole 50, as shown in fig. 3
Forming a mask layer having a predetermined pattern on a surface of the structure filled with the sacrificial material, the mask layer covering a surface of the first filling portion and the mask layer not covering a surface of the second filling portion 70; implanting predetermined ions into the sacrificial material in the second filling portion 70, so that the sacrificial material in the second filling portion 70 forms a predetermined sacrificial material, the predetermined ions are carbon ions, the sacrificial material is polysilicon, and an etching selection ratio of the sacrificial material to the predetermined sacrificial material is greater than 100; removing the mask layer; removing the first filling part 60, as shown in fig. 4;
forming a second stacked structure on the structure with the first filling portion removed, wherein the channel hole 40 in the second stacked structure is communicated with the channel hole 40 in the first stacked structure, as shown in fig. 5, until N stacked structures are formed, and a second filling portion 70 is disposed in the dummy channel hole of the first N-1 stacked structures;
charge blocking layers, charge trapping layers, charge tunneling layers, channel layers, isolation layers, and drain contact structures (not shown) are formed in the channel holes.
And removing the sacrificial layer to form a gap area, forming a metal gate 20' from the material of the metal gate in the gap area, and obtaining the 3D NAND device, as shown in FIG. 6, wherein only a part of the structural schematic diagram is shown in FIG. 6.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the semiconductor technology of this application, at first, form first stacked structure on the base, have channel hole and virtual channel hole in the stacked structure, later, pack the sacrificial material in channel hole and virtual channel hole, form first filling portion in the channel hole, form second filling portion in the virtual channel hole, then, get rid of first filling portion, finally, form second stacked structure on getting rid of the structure of first filling portion, channel hole in the second stacked structure and the channel hole intercommunication in the first stacked structure. In the process, before the second stacked structure is formed, the second filling part is formed in the virtual channel in the first stacked structure through the filling step and the removing step, and the hole channel hole in the first stacked structure is not provided with the filling part, so that in the process of forming the second stacked structure, the later formed virtual channel hole cannot deform with the second filling part, thereby avoiding the electric leakage problem caused by deformation, compared with the process for avoiding the deformation of the virtual channel hole formed by the multiple stacking technology in the prior art, the process is simpler, a thicker photoresist layer or a hard mask layer is not required to be formed, a longer removing time is not required, the problem that the pattern layer above the virtual area is difficult to remove due to the deformation caused by the longer removing time is further avoided, and due to the first filling part and the second filling part which are formed, the photoresist or the hard mask material cannot enter the virtual channel hole or the channel hole, the problem of subsequent difficult removal is prevented.
2) In the semiconductor structure of the present application, the second filling portion is located in the second dummy trench hole, and the second filling portion can prevent the second dummy trench hole from being deformed to avoid electric leakage, so that the semiconductor structure has good electrical performance.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. A semiconductor process, comprising:
a first stacking structure forming step of forming a first stacking structure on a substrate, the stacking structure having a channel hole and a dummy channel hole therein;
filling sacrificial materials into the channel holes and the dummy channel holes, forming first filling parts in the channel holes, and forming second filling parts in the dummy channel holes, wherein the sacrificial materials are insulating materials;
a removing step of removing the first filling part;
a subsequent stacked structure forming step of forming a second stacked structure on the structure from which the first filling portion is removed, the channel hole in the second stacked structure and the channel hole in the first stacked structure being communicated, the first stacked structure and the second stacked structure respectively including a sacrificial layer and an insulating dielectric layer which are alternately arranged,
after the second stack structure is formed, the semiconductor process further includes:
repeating the filling step, the removing step and the subsequent stacked structure forming step at least once in sequence until a predetermined number of the sacrificial layers are formed.
2. The semiconductor process of claim 1, wherein the step of forming the first stacked structure comprises:
providing the substrate;
forming a first preparation stacking structure on the substrate, wherein the first preparation stacking structure comprises preparation sacrificial layers and preparation insulating medium layers which are formed alternately;
and etching and removing part of the preparation sacrificial layer and the preparation insulating medium layer to form the first stacked structure with the channel hole and the virtual channel hole.
3. The semiconductor process according to claim 1, wherein the first filling portion formed by the filling step has a gap therein.
4. The semiconductor process of claim 1, wherein the filling step comprises:
filling the channel hole and the dummy channel hole with the sacrificial material;
carrying out planarization treatment on the surface of the structure filled with the sacrificial material;
the remaining sacrificial material in the trench hole forms the first filling portion, and the remaining sacrificial material in the dummy trench hole forms the second filling portion.
5. The semiconductor process of claim 1, wherein the removing step comprises:
forming a mask layer with a preset pattern on the surface of the structure filled with the sacrificial material, wherein the mask layer covers the surface of the first filling part, and the mask layer does not cover the surface of the second filling part;
performing predetermined treatment on the sacrificial material in the second filling part, so that the sacrificial material in the second filling part forms a predetermined sacrificial material, wherein the etching selection ratio of the sacrificial material to the predetermined sacrificial material is more than 100;
removing the mask layer;
and removing the first filling part.
6. The semiconductor process according to claim 5, wherein the predetermined treatment of the sacrificial material in the second filling portion so that the sacrificial material in the second filling portion forms a predetermined sacrificial material comprises:
and injecting predetermined ions into the sacrificial material in the second filling part to form the predetermined sacrificial material, wherein elements corresponding to the predetermined ions are different from elements in the sacrificial material.
7. A semiconductor structure, wherein the semiconductor structure is manufactured by the semiconductor process of any one of claims 1 to 6.
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