CN111599807A - Differential input pair transistor for improving performance under standard MOS process and improving method - Google Patents
Differential input pair transistor for improving performance under standard MOS process and improving method Download PDFInfo
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- CN111599807A CN111599807A CN202010440928.7A CN202010440928A CN111599807A CN 111599807 A CN111599807 A CN 111599807A CN 202010440928 A CN202010440928 A CN 202010440928A CN 111599807 A CN111599807 A CN 111599807A
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- 238000003491 array Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention provides a method for improving the performance of differential input pair transistors under a standard MOS process, which reduces the parasitic capacitance of the drain electrode of an MOS transistor as much as possible on the premise of not increasing the layout area, decomposes the grid of the MOS transistor into an array structure, surrounds the drain electrode by using a circular drawing method for the grid electrode, and compresses the drain electrode to the minimum size allowed by the process, and the source electrode is arranged outside the grid electrode at the moment, and the source electrodes of the input pair transistors can be just connected in a sharing way. By reducing the perimeter, corners are avoided, the MOS tube efficiency in unit area is improved, and the parasitic capacitance of the differential input pair tubes is reduced, so that the working frequency is improved, the matching performance is improved, and the offset voltage of the differential input pair tubes is reduced.
Description
Technical Field
The invention relates to the technical field of analog integrated circuits, in particular to a differential input pair transistor for improving performance under a standard MOS (metal oxide semiconductor) process and a improving method.
Background
The general input differential pair transistor is widely applied to input stages in circuits such as an operational amplifier, a comparator and the like, is used for generating an input amplified signal, is composed of two MOS transistors connected with a common source, and can be divided into two cases of a PMOS transistor and an NMOS transistor. Fig. 1a and 1b are a rectangular pattern drawing method of a standard MOS transistor, and since there is a certain matching error inevitably, the gate size of the MOS transistor needs to be increased if the matching error of the MOS transistor is to be decreased. Therefore, in the field of circuits with high precision requirement, the input pair transistors are generally relatively large in size, and the larger the drain parasitic capacitance generated by the input pair transistors, the problem limits the response speed of the circuit.
In order to reduce the layout area as much as possible and reduce the on-resistance of the circuit in the conventional method, one method is to arrange square gate units in an array, wherein the drain regions of the square gate units are positioned in the gate units, and the source regions of the square gate units are positioned among the gate units, fig. 2 is a layout of the method, wherein the drain electrodes of the square gate units have large parasitic capacitance, the gate electrodes of the square gate units have corners, and the matching performance is limited, and the square gate units are generally used in the field of power switching tubes.
Disclosure of Invention
In view of the defects in the prior art, an embodiment of the present invention provides a differential input pair transistor and a boosting method for improving performance in a standard MOS process, so as to solve the above problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme:
a differential input pair transistor with improved performance under a standard MOS process comprises:
a plurality of grid units which are regularly arranged;
a drain region located in each gate unit;
and source regions located between the gate cells.
As a further scheme of the present invention, the gate unit is circular, the gate unit includes two portions, namely an outer portion and an inner portion, the inner portion is a drain region, the outer portion is a source region, and a predetermined spacing distance exists between two adjacent gate units.
As a further scheme of the invention, the grid unit further comprises a drain contact hole positioned at the center in each grid unit; and a source contact hole positioned at the center of the mutually adjacent source regions of the above four gate units.
As a further scheme of the present invention, the regular arrangement is an array arrangement, and the grid unit arrays are connected to form an oblique symmetry.
As a further aspect of the invention, the gate region is in the form of a closed loop; the source contact hole and the drain contact hole are circular or polygonal; the source electrode and the drain electrode are connected by adopting a method of oblique line symmetry, the drain electrode is connected with the inner side of the grid electrode, and the source electrode is connected with the outer side of the grid electrode in a sharing way; the gate region should have a shape corresponding to the shape of the drain region.
The invention also provides a method for improving the performance of the differential input pair transistor under the standard MOS process, which comprises the following steps:
arranging a plurality of grid units in an array mode, wherein each grid unit comprises an outer circle and an inner circle, and a preset spacing distance exists between every two adjacent grid units;
forming drain regions in the gate units;
forming drain contact holes at the centers of the drain regions in the respective gate units;
forming source regions between the gate units;
a source contact hole located at the center of mutually adjacent source regions of the above four gate units is formed.
As a further aspect of the present invention, the gate region is formed in a closed loop form.
As a further aspect of the present invention, the source contact hole and the drain contact hole should be circular or polygonal.
In summary, compared with the prior art, the embodiment of the invention has the following beneficial effects:
1. the invention realizes that the parasitic capacitance of the drain electrode of the MOS tube is reduced as much as possible by reducing the perimeter of the graph on the premise of not increasing the area of the layout.
2. The method of the invention changes the shape of the MOS tube into a round shape in order to avoid corners without changing the standard MOS process, and performs matching connection on the MOS tube array, thereby improving the efficiency of the MOS tube in unit area, reducing the parasitic capacitance of the differential input pair tube, improving the working frequency, improving the matching performance and reducing the offset voltage of the differential input pair tube.
3. The method reduces the parasitic capacitance of the drain electrode of the MOS tube as much as possible on the premise of not increasing the area of the layout, decomposes the grid of the MOS tube into an array structure, surrounds the drain electrode by using a circular drawing method for the grid, compresses the drain electrode to the minimum size allowed by the process, and at the moment, the source electrode is arranged on the outer side of the grid, and the source electrodes of the input geminate transistors can be just connected in a sharing way. By reducing the perimeter, corners are avoided, the MOS tube efficiency in unit area is improved, and the parasitic capacitance of the differential input pair tubes is reduced, so that the working frequency is improved, the matching performance is improved, and the offset voltage of the differential input pair tubes is reduced.
To more clearly illustrate the structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Description of the drawings:
FIG. 1a and FIG. 1b are respectively a drawing of a rectangular pattern of a standard MOS transistor and corresponding symbols;
FIG. 2 is a layout of a MOS transistor according to the conventional method;
FIG. 3 is a MOS transistor layout of an embodiment of the invention;
fig. 4 is a layout of a MOS transistor metal layer according to an embodiment of the present invention.
The specific implementation mode is as follows:
the technical solution of the present invention is further described with reference to the accompanying drawings and specific embodiments.
Referring to fig. 3, the differential input pair transistor for improving performance in a standard MOS process includes a plurality of gate units 1 arranged in an array, where each gate unit 1 is circular, each gate unit 1 includes two portions, namely an outer portion and an inner portion, and a predetermined spacing distance exists between two adjacent gate units;
as shown in fig. 3, the gate cell array connections are all in a diagonal line symmetry method;
a drain region 2 located in each gate unit;
a drain contact hole at the center of the drain region within each gate cell;
source regions 4 located between the respective gate cells;
and a source contact hole 3 positioned at the center of the mutually adjacent source regions of the above four gate cells 1.
In a preferred embodiment of the present invention, wherein the gate region is formed in a closed loop; the source contact hole and the drain contact hole are circular or polygonal; the connection method of the source electrode and the drain electrode adopts a method of oblique line symmetry, the drain electrode is connected with the inner side of the grid electrode, and the source electrode is connected with the outer side of the grid electrode in a sharing way; and in the present invention the gate region should have a shape corresponding to the shape of the drain region. The invention realizes that the parasitic capacitance of the drain electrode of the MOS tube is reduced as much as possible by reducing the perimeter of the graph on the premise of not increasing the area of the layout; under the condition of not changing the standard MOS process procedure, in order to avoid corners, the shape of the MOS tube is changed into a round shape, and the MOS tube array is connected in a matching way, so that the efficiency of the MOS tube in unit area can be improved, the parasitic capacitance of the differential input pair tubes is reduced, the working frequency is improved, the matching performance is improved, and the offset voltage of the differential input pair tubes is reduced.
The invention also provides a method for improving the performance of the differential input pair transistor under the standard MOS process, which comprises the following steps:
referring to fig. 3, the method includes:
(1) drawing of input differential pair tube: the general input differential pair transistor is widely applied to input stages in circuits such as an operational amplifier, a comparator and the like, is used for generating an input amplified signal, is composed of two MOS transistors connected with a common source, and can be divided into two cases of a PMOS transistor and an NMOS transistor. The method changes the shape of the MOS tube into a circle under the condition of not changing the standard MOS process, and performs matched connection on the MOS tube array.
(2) The grid drawing method and the connection method comprise the following steps: the optimal method is to decompose the grid of the MOS tube into an array structure, use a circular drawing method, surround the drain electrode by the grid, compress the size of the drain electrode to the range allowed by the process, and then the outer side of the grid is the source electrode, and the source electrodes of the input tube pair just can be connected in a sharing way.
(3) The connection method of the grid electrode, the source electrode and the drain electrode comprises the following steps: in order to further improve the matching performance and reduce the complexity of connection to the maximum extent, the gate array connection adopts a diagonal line symmetry method, the gates of adjacent MOS transistors are connected at intervals, fig. 4 is a schematic diagram of a 4X4 array thereof, the drain is connected to the inner side of the gate, and the source is connected to the outer side of the gate in a sharing manner.
The method of the invention reduces the parasitic capacitance of the drain electrode of the MOS tube as much as possible on the premise of not increasing the layout area, decomposes the grid of the MOS tube into an array structure, uses a circular drawing method for the grid, surrounds the drain electrode, and compresses the drain electrode to the minimum size allowed by the process, and the source electrode is arranged outside the grid, and the source electrodes of the input geminate transistors can be just connected in a sharing way. By reducing the perimeter, corners are avoided, the MOS tube efficiency in unit area is improved, and the parasitic capacitance of the differential input pair tubes is reduced, so that the working frequency is improved, the matching performance is improved, and the offset voltage of the differential input pair tubes is reduced.
The following provides a specific embodiment of the present invention
Example 1
Fig. 3 is a MOS transistor layout of an embodiment of the present invention.
As shown in fig. 3, in the MOS transistor layout, almost all the regions cover the active region, which is divided into a source region and a drain region by the gate region. Self-alignment between the grid position and the source and drain positions can be achieved by utilizing a self-alignment technology, so that the covering capacitance of the grid to the source and drain is reduced, and the switching speed of the circuit is improved.
The grid region comprises a plurality of grid units 1 which are arranged in an array, the grids of adjacent MOS tubes are connected at intervals in fig. 3, the grid units are connected in an array mode by adopting a diagonal line symmetry method, a preset distance is required to be arranged between every two adjacent grid units, and the rest grid units are arranged in the same way. Each grid unit uses a circular drawing method and surrounds the drain, and the size of the drain is compressed to the range allowed by the process.
Referring to fig. 3, the source regions are located between the gate cells and the sources of the input pair transistors can just share the connection. One or more source contact holes are arranged between two adjacent gate units and at the center of the source region surrounded by four corner regions adjacent to each other.
The region in the middle of each gate unit is a drain region. Contact holes are typically provided in the drain regions. The shape of the drain contact hole generally conforms to the shape of the source contact hole. Wherein the distance from the drain contact hole to any other channel is equal to or greater than a certain minimum drain spacing. The drain size should be determined by the allowable range of the process.
In this embodiment, in order to further improve the matching performance and reduce the complexity of connection to the maximum extent, the connection method of the source and the drain is a diagonal line symmetry method, as shown in fig. 4 of the 4X4 array diagram, the drain is connected to the inside of the gate, and the source is connected to the outside of the gate in common.
The design is helpful to make the adjacent gate units closer to each other, thereby obtaining the effect of obtaining a larger equivalent MOS transistor channel width under the same chip area.
Referring to the actual layout diagram 3, the drain terminal area of the invention is extremely small, and under the minimum regular length and width, R is set as the radius of the drain electrode, so that the circumference of the circle is 6.28R and is smaller than the circumference of the square under the same size, namely 8R, and the smaller the circumference, the smaller the parasitic capacitance. The MOS tube array is connected in a matching way by changing the shape of the MOS tube into a round shape, so that the perimeter of the graph is reduced, corners are avoided, the efficiency of the MOS tube in unit area is improved, and the parasitic capacitance of the differential input pair tube is reduced. Therefore, for chips with the same area, the invention effectively improves the working frequency and further improves the matching performance.
The technical principle of the present invention has been described above with reference to specific embodiments, which are merely preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. Other embodiments of the invention will occur to those skilled in the art without the exercise of inventive faculty, and such will fall within the scope of the invention.
Claims (8)
1. A differential input pair transistor with improved performance under a standard MOS process is characterized by comprising:
a plurality of grid units which are regularly arranged;
a drain region located in each gate unit;
and source regions located between the gate cells.
2. The pair of differential input transistors with performance enhancement under a standard MOS process of claim 1, wherein the gate unit is circular, the gate unit includes two portions, an outer portion and an inner portion, the inner portion is a drain region, the outer portion is a source region, and a predetermined spacing distance exists between two adjacent gate units.
3. The pair of differential input transistors with improved performance in a standard MOS process of claim 2 further comprising a drain contact hole centrally located within each gate cell; and a source contact hole positioned at the center of the mutually adjacent source regions of the above four gate units.
4. The differential input pair transistor with improved performance in the standard MOS process of claim 3, wherein the regular arrangement is an array arrangement, and the gate unit arrays are connected to form an oblique symmetry.
5. The pair of differential input transistors with improved performance in a standard MOS process according to any one of claims 1-4, wherein the gate region is in the form of a closed loop; the source contact hole and the drain contact hole are circular or polygonal; the source electrode and the drain electrode are connected by adopting a method of oblique line symmetry, the drain electrode is connected with the inner side of the grid electrode, and the source electrode is connected with the outer side of the grid electrode in a sharing way; the gate region should have a shape corresponding to the shape of the drain region.
6. A method for improving the performance of a differential input pair transistor under a standard MOS process is characterized by comprising the following steps:
arranging a plurality of grid units in an array mode, wherein each grid unit comprises an outer circle and an inner circle, and a preset spacing distance exists between every two adjacent grid units;
forming drain regions in the gate units;
forming drain contact holes at the centers of the drain regions in the respective gate units;
forming source regions between the gate units;
a source contact hole located at the center of mutually adjacent source regions of the above four gate units is formed.
7. The method for improving the performance of a differential input pair transistor under the standard MOS process of claim 6, wherein the gate region is formed in a closed loop.
8. The method of claim 7, wherein the source contact hole and the drain contact hole are circular or polygonal.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050106825A1 (en) * | 2003-11-13 | 2005-05-19 | Budong You | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
| CN101657901A (en) * | 2006-12-28 | 2010-02-24 | 马维尔国际贸易有限公司 | Geometry of MOS device with low on-resistance |
| CN101771084A (en) * | 2010-01-20 | 2010-07-07 | 电子科技大学 | Layout structure of transverse power components |
| CN102142462A (en) * | 2011-02-25 | 2011-08-03 | 北京大学 | Power MOS transistor of asymmetric structure and array thereof |
| CN105470308A (en) * | 2015-12-30 | 2016-04-06 | 无锡中感微电子股份有限公司 | MOS transistor |
| CN105514102A (en) * | 2014-10-17 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Layout structure, semiconductor device and electronic apparatus |
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2020
- 2020-05-22 CN CN202010440928.7A patent/CN111599807B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050106825A1 (en) * | 2003-11-13 | 2005-05-19 | Budong You | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
| CN101657901A (en) * | 2006-12-28 | 2010-02-24 | 马维尔国际贸易有限公司 | Geometry of MOS device with low on-resistance |
| CN101771084A (en) * | 2010-01-20 | 2010-07-07 | 电子科技大学 | Layout structure of transverse power components |
| CN102142462A (en) * | 2011-02-25 | 2011-08-03 | 北京大学 | Power MOS transistor of asymmetric structure and array thereof |
| CN105514102A (en) * | 2014-10-17 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Layout structure, semiconductor device and electronic apparatus |
| CN105470308A (en) * | 2015-12-30 | 2016-04-06 | 无锡中感微电子股份有限公司 | MOS transistor |
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