CN111599762B - Manufacturing method of embedded germanium-silicon epitaxial layer - Google Patents

Manufacturing method of embedded germanium-silicon epitaxial layer Download PDF

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CN111599762B
CN111599762B CN202010466192.0A CN202010466192A CN111599762B CN 111599762 B CN111599762 B CN 111599762B CN 202010466192 A CN202010466192 A CN 202010466192A CN 111599762 B CN111599762 B CN 111599762B
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silicon
silicon nitride
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CN111599762A (en
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李中华
李润领
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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Abstract

The invention discloses a manufacturing method of an embedded germanium-silicon epitaxial layer, which comprises the following steps: a semiconductor substrate having a gate structure is provided. A first silicon dioxide layer and a second silicon nitride layer are formed. The groove for forming PMOS in self-alignment comprises: performing first silicon nitride etching by using the first silicon dioxide layer as a stop layer; etching silicon dioxide; forming a groove by self-aligned etching; the shape of the groove is made sigma-shaped. And forming an embedded germanium-silicon epitaxial layer. Performing media stripping, comprising: carrying out phosphoric acid wet etching; forming a third silicon dioxide layer and a fourth silicon nitride layer; performing silicon nitride plasma etching; carrying out hydrofluoric acid wet etching; carrying out phosphoric acid wet etching; and removing the residual third silicon dioxide layer and the first silicon dioxide layer. The invention can prevent germanium-silicon residues from appearing at the top corner of the gate structure, prevent the loss of the critical dimension of the gate structure and the loss of semiconductor substrate materials between the gate structures, and improve the reliability of the gate dielectric layer.

Description

Manufacturing method of embedded germanium-silicon epitaxial layer
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an embedded sige epitaxial layer.
Background
After a germanium-silicon growth area is defined and a groove is formed in a side wall adopted in the existing 28nm technology node embedded germanium-silicon epitaxial layer growth process, the thickness of silicon nitride (SiN) of a hard mask layer (HM) remained at the top corner of a grid structure of a PMOS (P-channel metal oxide semiconductor) is smaller than that of silicon nitride (SiN) of the hard mask layer (HM)
Figure BDA0002512734200000011
The selection ratio of the germanium silicon to the HM SiN is reduced, and germanium silicon residues are easily grown at the top corner of the grid structure of the PMOS. Secondly, after the growth of the germanium and silicon is finished, in order to strip the SiN on the top end and the side wall of the grid structure of the NMOS, the action time of phosphoric acid is as high as 6 minutes, and finally, the SiN is removed, and meanwhile, the silicon loss of the active region is caused to be as high as or greater than the standard value of the Si in the area of the NMOS>
Figure BDA0002512734200000012
Furthermore, to completely strip away the SiN, phosphoric acid has exposed the polysilicon gate and the gate dielectric layer, such as the gate oxide layer, during an Over Etch (OE) phase, which can result in loss of critical dimensions of the gate structure and reduced gate oxide reliability (GOI).
Referring to the drawings, the following description of the prior art is provided, as shown in fig. 1A to fig. 1F, which are schematic device structures in steps of a method for manufacturing an embedded sige-si epitaxial layer; the manufacturing method of the existing embedded germanium-silicon epitaxial layer comprises the following steps:
step one, as shown in fig. 1A, a semiconductor substrate 101 for integrating PMOS and NMOS is provided. In general, a well region is further formed on the semiconductor substrate 101, the well region includes a P-well 103 and an N-well 104, the NMOS is formed on the P-well 103, and the PMOS is formed on the N-well 104.
A plurality of gate structures formed by overlapping gate dielectric layers and polysilicon gates 105 are formed on the semiconductor substrate 101, a first hard mask layer 106 is formed on the top of each gate structure, and the first hard mask layer 106 is made of silicon nitride; first sidewalls 107 are formed on the sides of the gate structure, and the material of the first sidewalls 107 includes silicon nitride.
Conventionally, the semiconductor substrate 101 is a silicon substrate.
A field oxide layer 102 is formed on the semiconductor substrate 101, a plurality of active regions are isolated by the field oxide layer 102, and each of the PMOS and each of the NMOS are formed in the corresponding active region.
The gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
Step two, as shown in fig. 1B, a second hard mask layer 108 composed of a silicon nitride layer is formed.
And step three, as shown in fig. 1C, performing a photolithography process to form a photoresist 109 pattern, wherein the photoresist 10 pattern opens the formation region of the PMOS and covers the formation region of the NMOS.
And etching the second hard mask layer 108 to expose the surface of the semiconductor substrate 1 between the gate structures. It can be seen that, in the process of etching the second hard mask layer 108, since the first hard mask layer 106 and the first sidewall 107 are both made of silicon nitride, the first hard mask layer 106 and the first sidewall 107 are also damaged and the silicon nitride overlapping thickness at the top corner of the gate structure is reduced, that is, the thickness d101 at the dashed circle 111 is reduced.
And then, performing plasma etching self-alignment on the semiconductor substrate 101 between the second hard mask layers 108 corresponding to the side surfaces of the gate structure to form the groove 110a, where in fig. 1C, the groove 110a is separately denoted by a mark 110 a.
Typically, the recess 110a is U-shaped or bowl-shaped, and the etching process consumes a portion of the thickness of the first hard mask layer 106, the second hard mask layer 108 and the first sidewall 107 in the PMOS region at the same time.
Then, as shown in fig. 1D, the photoresist 109 is removed. In the prior art 28nm technology node process, after the groove 110a is formed, the d101 is usually reduced to
Figure BDA0002512734200000021
This makes the selectivity of the sige epitaxy at the top corners of the gate structure less good, which tends to form sige residues. FIG. 2A is a photograph corresponding to FIG. 1D, and it can be seen that D101 at two top corners of the polysilicon gate 105 are ^ and/or greater than>
Figure BDA0002512734200000022
And &>
Figure BDA0002512734200000023
A in FIG. 2A denotes `>
Figure BDA0002512734200000024
Then, wet etching is performed on the semiconductor substrate 101 to make the shape of the groove 110 be sigma-shaped; typically, the chemical solution used for wet etching includes a tetramethylammonium hydroxide solution (TMAH).
As shown in fig. 1E, an epitaxial growth of sige is performed to form an embedded sige epitaxial layer 112 in the recess 110.
The germanium-silicon epitaxial growth is selective germanium-silicon epitaxial growth. From the thinner thickness of d101 in fig. 1C, the top corner of the gate structure forms sige residues.
Step four, as shown in fig. 1F, a phosphoric acid wet etching process is adopted to simultaneously strip the remaining first hard mask layer 106, the second hard mask layer 108 and the first sidewall 107. Referring back to fig. 1E, d102 corresponds to the maximum thickness of the first hard mask layer 106 and the second hard mask layer 108, and the phosphoric acid wet etching process needs to ensure that silicon nitride corresponding to the thickness d102 is removed, so that the phosphoric acid wet etching process needs a longer etching time, and the longer phosphoric acid wet etching process may cause a loss of a surface material of the semiconductor substrate 101 and a loss of a side material of the polysilicon gate 105, and may also adversely affect a gate dielectric layer such as a gate oxide layer.
Comparing the width d103 of the polysilicon gate 105 of fig. 1E with the width d103a of the polysilicon gate 105 of fig. 1F, it can be seen that the width d103a is smaller than the width d103, which may cause a loss of the critical dimension of the polysilicon gate 105.
As shown in fig. 2B, is a photograph of a formation region of the PMOS corresponding to fig. 1F; it can be seen that sige residues 112a are formed at the top corners of the polysilicon gate 105, i.e., at the regions 111.
FIG. 2C is a photograph of a top view of the substrate shown in FIG. 1F after the steps corresponding to the substrate have been completed; as can be seen, the polysilicon gates 105 are all in a strip structure, and germanium silicon residues 112a are formed at top corners of the polysilicon gates 105 in the PMOS formation region.
FIG. 2D is a photograph showing the formation region of the NMOS corresponding to FIG. 1F; it can be seen that the surface material of the semiconductor substrate 101 generates a loss thickness of
Figure BDA0002512734200000031
A in FIG. 2D denotes ^ er>
Figure BDA0002512734200000032
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of an embedded germanium-silicon epitaxial layer, which can prevent germanium-silicon residues from appearing at the top corner of a gate structure, prevent the loss of the critical dimension of the gate structure and the loss of semiconductor substrate materials between the gate structures, and improve the reliability of a gate dielectric layer.
In order to solve the technical problem, the manufacturing method of the embedded germanium-silicon epitaxial layer provided by the invention comprises the following steps:
providing a semiconductor substrate for integrating PMOS and NMOS, forming a plurality of grid structures formed by overlapping grid dielectric layers and polysilicon grids on the semiconductor substrate, and forming a first hard mask layer on the top of each grid structure, wherein the first hard mask layer is silicon nitride; and forming a first side wall on the side surface of the gate structure, wherein the first side wall is made of silicon nitride.
Forming a second hard mask layer formed by overlapping the first silicon dioxide layer and the second silicon nitride layer; the second hard mask layer covers the surfaces of the first hard mask layer and the first side wall corresponding to the gate structure and extends to the surface of the semiconductor substrate outside the gate structure.
Step three, carrying out a photoetching process to open the forming area of the PMOS and cover the forming area of the NMOS, and etching to form a groove in the semiconductor substrate at two sides of the gate structure in the forming area of the PMOS in a self-alignment manner, wherein the method comprises the following steps:
step 31, performing first silicon nitride etching by taking the first silicon dioxide layer as a stop layer, wherein the first silicon nitride etching adopts plasma etching; the first silicon nitride etching removes the second silicon nitride layer on the top of the grid structure and the second silicon nitride layer on the surface of the semiconductor substrate between the grid structures; the first silicon nitride etching removes the second silicon nitride layers on two sides of the grid structure from the side part; and in the first silicon nitride etching, the first silicon dioxide layer protects the first hard mask layer and the first side wall, so that the thickness reduction of the first hard mask layer and the first side wall at the top angle of the grid structure is prevented.
And 32, etching to remove the first silicon dioxide layer between the first silicon dioxide layer at the top of the grid structure and on the surface of the semiconductor substrate, and overlapping the first silicon dioxide layer and the second silicon nitride layer reserved on the side surface of the first side wall of the grid structure to form a second side wall.
And step 33, performing plasma etching self-alignment on the semiconductor substrate between the second side walls corresponding to the gate structures to form the grooves.
And step 34, performing wet etching on the semiconductor substrate to enable the groove to be sigma-shaped.
And fourthly, performing germanium-silicon epitaxial growth to form an embedded germanium-silicon epitaxial layer in the groove.
Fifthly, a dielectric stripping process is carried out, the dielectric stripping process is used for stripping the second hard mask layer and the first hard mask layer in the NMOS forming area and the second hard mask layer and the first hard mask layer left in the PMOS forming area, and the dielectric stripping process comprises the following sub-steps:
and step 51, performing second silicon nitride etching by adopting a phosphoric acid wet etching process, wherein the first hard mask layer which is not covered by the first silicon dioxide layer and the second silicon nitride layer are removed by the second silicon nitride etching.
And 52, forming a third hard mask layer formed by overlapping the third silicon dioxide layer and the fourth silicon nitride layer.
And 53, performing third silicon nitride etching by taking the third silicon dioxide layer as a stop layer, wherein the third silicon nitride etching adopts plasma etching, the third silicon nitride etching forms third side walls consisting of the rest fourth silicon nitride layers on the side surfaces of the gate structures, and the fourth silicon nitride layers on the surfaces of the semiconductor substrate on the tops of the gate structures and between the third side walls are all removed.
And 54, performing first hydrofluoric acid wet etching to remove the exposed first silicon dioxide layer and the exposed third silicon dioxide layer, wherein the surface of the first hard mask layer at the top of each gate structure in the formation region of the NMOS is exposed after the first hydrofluoric acid wet etching is completed.
And step 55, performing fourth silicon nitride etching by adopting a phosphoric acid wet etching process, wherein the fourth silicon nitride etching removes the first hard mask layer left in the formation region of the NMOS and removes the third side walls.
And 56, removing the residual third silicon dioxide layer and the first silicon dioxide layer.
In a further improvement, in the first step, the semiconductor substrate is a silicon substrate.
In a further improvement, a field oxide layer is formed on the semiconductor substrate, a plurality of active regions are isolated by the field oxide layer, and each PMOS and each NMOS are formed in the corresponding active region.
In a further improvement, the first hard mask layer has a thickness of
Figure BDA0002512734200000051
The height of the polysilicon gate is
Figure BDA0002512734200000052
The first side wall is formed by overlapping silicon oxide and silicon nitride, and the total thickness of the silicon oxide and the silicon nitride of the first side wall is
Figure BDA0002512734200000053
The further improvement is that the gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
In the second step, the first silicon dioxide layer is an atomically deposited silicon dioxide film layer with a thickness of
Figure BDA0002512734200000054
The second silicon nitride layer is an atomic deposition silicon nitride film layer with the thickness of
Figure BDA0002512734200000055
In a further improvement, the photolithography process in the third step comprises:
and sequentially forming a bottom anti-reflection coating and photoresist.
And sequentially carrying out exposure and development to form a photoresist pattern, wherein the photoresist pattern opens the forming area of the PMOS and covers the forming area of the NMOS.
And removing the bottom anti-reflection coating in the opening area by taking the photoresist pattern as a mask.
In a further improvement, the shape of the groove formed in step 33 is U-shaped or bowl-shaped, and the etching process of step 33 consumes part of the thickness of the first hard mask layer in the PMOS region and part of the thickness of the second silicon nitride layer of the second sidewall.
In a further improvement, after step 33 is completed and before step 34 is started, a wet cleaning process is performed to remove the photoresist and the bottom anti-reflective coating.
In a further improvement, the chemical solution used in the wet etching in step 34 includes a tetramethylammonium hydroxide solution.
The further improvement is that the germanium-silicon epitaxial growth process of the fourth step adopts chemical vapor deposition, and the germanium-silicon epitaxial growth process comprises the following sub-steps:
and growing a germanium-silicon seed layer.
And growing a germanium-silicon body layer.
And growing a germanium-silicon cap layer.
In a further improvement, the process time of the second silicon nitride etching in step 51 is 120s to 240s.
In a further improvement, in step 52, the third silicon dioxide layer is an atomic deposition silicon dioxide film layer with a thickness of
Figure BDA0002512734200000056
The fourth silicon nitride layer is an atomic deposition silicon nitride film layer with the thickness of
Figure BDA0002512734200000061
In a further improvement, the process time of the fourth silicon nitride etching in step 55 is 120s to 240s.
In a further improvement, in step 56, the remaining third silicon dioxide layer and the first silicon dioxide layer are removed by a hydrofluoric acid wet etching process.
In a further improvement, the technical node of the PMOS and the NMOS is below 28 nm.
A further improvement is that the germanium-silicon epitaxial growth in the fourth step is selective germanium-silicon epitaxial growth.
After step 33 is completed, the thickness of the first hard mask layer and the first sidewall at the top corner of the gate structure is ensured to prevent germanium-silicon residues from being formed at the top corner of the gate structure in the fourth step.
In a further improvement, after step 33 is completed, the thickness of the first hard mask layer and the first sidewall at the top corner of the gate structure is greater than the thickness of the first sidewall
Figure BDA0002512734200000062
In a further improvement, in step 55, the fourth silicon nitride etching generates silicon loss on the semiconductor substrate between the gate structures, and the thickness of the silicon loss is determined by the thickness of the first hard mask layer.
In step 55, a stacked structure of the first silicon dioxide layer and the third silicon dioxide layer, which is reserved between the first sidewall and the third sidewall, is used as a protective sidewall, so that the silicon loss does not affect the critical dimension of the gate structure and the gate dielectric layer.
The structure of the second hard mask layer of the groove of the germanium-silicon epitaxial layer of the PMOS is specially set, the second hard mask layer is set to be a superposed structure of the first silicon dioxide layer and the second silicon nitride layer, so that the first silicon dioxide layer is arranged between the first hard mask layer and the second silicon nitride layer at the top of the polysilicon gate, the second silicon dioxide layer is etched by taking the first silicon dioxide layer as a stop layer during groove etching, then the first silicon dioxide layer is etched, and then the semiconductor substrate is etched.
In addition, after the embedded germanium-silicon epitaxial layer is formed, the thicker silicon nitride is respectively removed, and mainly, a phosphoric acid wet etching process is adopted to remove the first hard mask layer which is not covered by the first silicon dioxide layer and the second silicon nitride layer; then, a third hard mask layer formed by overlapping a third silicon dioxide layer and a fourth silicon nitride layer is formed, and plasma etching of silicon nitride is carried out to form a third side wall formed by the fourth silicon nitride layer; then, opening the first silicon dioxide layer and the third silicon dioxide layer to expose the surface of the first hard mask layer at the top of the grid structure; then, the first hard mask layer and the third side wall can be removed under the condition that the first silicon dioxide layer and the third silicon dioxide layer protect the side face of the grid structure, namely fourth silicon nitride etching is carried out, the fourth silicon nitride etching process can cause certain loss of the semiconductor substrate material, and the maximum thickness of the silicon nitride removed by the fourth silicon nitride etching process is the thickness of the first hard mask layer; meanwhile, under the protection of the first silicon dioxide layer and the third silicon dioxide layer, the fourth silicon nitride etching process can be prevented from generating an etching effect on the side face of the polysilicon gate of the gate structure, so that the loss of the critical dimension of the gate structure can be prevented; in addition, the size of the polysilicon gate of the gate structure is kept well, and the loss of semiconductor substrate materials is reduced, so that the gate dielectric layer of the gate structure can be well protected, and the reliability of the gate dielectric layer can be improved; finally, the invention is particularly suitable for the technology of the technical node below 28 nm.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1A to fig. 1F are schematic device structures in steps of a conventional method for manufacturing an embedded sige-si epitaxial layer;
FIG. 2A is a photograph corresponding to FIG. 1D;
FIG. 2B is a photograph of a region corresponding to FIG. 1F where PMOS is formed;
FIG. 2C is a photograph of a top view of FIG. 1F after completion of the corresponding steps;
FIG. 2D is a photograph of a formation region of the corresponding NMOS of FIG. 1F;
FIG. 3 is a flow chart of a method for fabricating an embedded SiGe epitaxial layer according to an embodiment of the present invention;
fig. 4A to fig. 4J are schematic device structures in steps of a method for manufacturing an embedded sige-si epitaxial layer according to an embodiment of the present invention;
FIG. 5A is a photograph of a top view of FIG. 4J after completion of the corresponding steps;
fig. 5B is a photograph of a formation region of the NMOS corresponding to fig. 4J.
Detailed Description
Fig. 3 is a flowchart illustrating a method for manufacturing an embedded sige epitaxial layer 12 according to an embodiment of the present invention; fig. 4A to fig. 4J are schematic diagrams of device structures in the steps of the method for manufacturing the embedded sige-si epitaxial layer 12 according to the embodiment of the present invention; the manufacturing method of the embedded germanium-silicon epitaxial layer 12 comprises the following steps:
step one, as shown in fig. 4A, a semiconductor substrate 1 for integrating PMOS and NMOS is provided. In general, a well region is further formed on the semiconductor substrate 1, the well region includes a P-well 3 and an N-well 4, the NMOS is formed on the P-well 3, and the PMOS is formed on the N-well 4.
A plurality of grid electrode structures formed by overlapping grid dielectric layers and polysilicon grids 5 are formed on the semiconductor substrate 1, a first hard mask layer 6 is formed at the top of each grid electrode structure, and the first hard mask layer 6 is made of silicon nitride; a first sidewall 7 is formed on a side surface of the gate structure, and a material of the first sidewall 7 includes silicon nitride.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.
A field oxide layer 2 is formed on the semiconductor substrate 1, a plurality of active regions are isolated by the field oxide layer 2, and each of the PMOS and each of the NMOS are formed in the corresponding active region.
The gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
Step two, as shown in fig. 4B, a second hard mask layer formed by overlapping the first silicon dioxide layer 8 and the second silicon nitride layer 9 is formed; the second hard mask layer covers the surfaces of the first hard mask layer 6 and the first side wall 7 corresponding to the gate structure and extends to the surface of the semiconductor substrate 1 outside the gate structure.
And step three, as shown in fig. 4C, performing a photolithography process to open the formation region of the PMOS and cover the formation region of the NMOS.
The photoetching process in the embodiment of the invention comprises the following steps:
a bottom anti-reflective coating and a photoresist 10 are sequentially formed.
And sequentially carrying out exposure and development to form a photoresist 10 pattern, wherein the photoresist 10 pattern opens the forming region of the PMOS and covers the forming region of the NMOS.
And removing the bottom anti-reflection coating in the opening area by taking the photoresist 10 pattern as a mask.
Etching the semiconductor substrate 1 at two sides of the grid structure of the PMOS forming region to form a groove 11 in a self-alignment manner, and the method comprises the following steps:
step 31, as shown in fig. 4C, performing a first silicon nitride etching using the first silicon dioxide layer 8 as a stop layer, where the first silicon nitride etching is plasma etching; the first silicon nitride etching removes the second silicon nitride layer 9 on the top of the grid structure and the second silicon nitride layer 9 on the surface of the semiconductor substrate 1 between the grid structures; the first silicon nitride etching removes the second silicon nitride layers 9 on two sides of the gate structure from the side part, that is, the second silicon nitride layers 9 on the side surfaces of the gate structure are thinned to a certain extent in the direction vertical to the side surface; in the first silicon nitride etching, the first silicon dioxide layer 8 protects the first hard mask layer 6 and the first side wall 7, so that the thicknesses of the first hard mask layer 6 and the first side wall 7 at the top corner of the gate structure are prevented from being reduced, and the top corner area of the gate structure refers to the area shown by the virtual coil 201. As can be seen from fig. 4C, the first silicon nitride etching is an anisotropic etching, and the second silicon nitride layer 9 on the side of the gate structure is mostly remained.
Step 32, as shown in fig. 4C, the first silicon dioxide layer 8 on the surface of the semiconductor substrate 1 between the first silicon dioxide layer 8 on the top of the gate structure and the gate structure is etched and removed, and the first silicon dioxide layer 8 and the second silicon nitride layer 9 remaining on the side surface of the first sidewall 7 of the gate structure are overlapped to form a second sidewall.
Step 33, as shown in fig. 4C, performing plasma etching on the semiconductor substrate 1 between the second sidewalls corresponding to the gate structures to self-align to form the grooves 11a, where in fig. 4C, the grooves 11a are individually denoted by a mark 11 a.
In the embodiment of the present invention, the shape of the groove 11a formed in step 33 is U-shaped or bowl-shaped, and the etching process in step 33 consumes part of the thickness of the first hard mask layer 6 in the PMOS region and part of the thickness of the second silicon nitride layer 9 in the second sidewall at the same time.
After step 33 is completed and before step 34 is started, a wet cleaning process is performed to remove the photoresist 10 and the bottom anti-reflective coating.
Step 34, as shown in fig. 4D, performing wet etching on the semiconductor substrate 1 to make the shape of the groove 11 be sigma-shaped.
In the embodiment of the present invention, the chemical solution used in the wet etching in step 34 includes a tetramethylammonium hydroxide solution.
Step four, as shown in fig. 4E, performing germanium-silicon epitaxial growth to form an embedded germanium-silicon epitaxial layer 12 in the groove 11.
In the embodiment of the invention, the germanium-silicon epitaxial growth process adopts chemical vapor deposition, and comprises the following steps:
and growing a germanium-silicon seed layer.
And growing a germanium-silicon body layer.
And growing a germanium-silicon cap layer.
The germanium-silicon epitaxial growth is selective germanium-silicon epitaxial growth. After step 33 is completed, the thickness of the first hard mask layer 6 and the first sidewall 7 at the top corner of the gate structure is such that no sige residue is formed at the top corner of the gate structure in step four.
Fifthly, a dielectric stripping process is carried out, the dielectric stripping process is used for stripping the second hard mask layer and the first hard mask layer 6 in the NMOS forming area and the second hard mask layer and the first hard mask layer 6 in the PMOS forming area, and the dielectric stripping process comprises the following steps:
step 51, as shown in fig. 4F, performing a second silicon nitride etching by using a phosphoric acid wet etching process, where the second silicon nitride etching removes both the first hard mask layer 6 and the second silicon nitride layer 9 that are not covered by the first silicon dioxide layer 8.
It can be seen that, in the embodiment of the present invention, the superimposed layers of the second silicon nitride layer 9 and the first hard mask layer 6 are not etched at the same time for a long time, so that the material loss of the semiconductor substrate 1 and the loss of the side material of the polysilicon gate 5 caused by the long actual silicon nitride etching in the prior art can be eliminated. In contrast, in the embodiment of the present invention, during the process of removing the second silicon nitride layer 9 and the first hard mask layer 6 of the PMOS formation region that has been thinned in step 33, both the semiconductor substrate 1 and the polysilicon gate 5 are protected by the first silicon dioxide layer 8, so that the material loss of the semiconductor substrate 1 and the loss of the side material of the polysilicon gate 5 are not generated.
Step 52, as shown in fig. 4G, a third hard mask layer formed by overlapping the third silicon dioxide layer 13 and the fourth silicon nitride layer 14 is formed.
And step 53, as shown in fig. 4H, performing a third silicon nitride etching with the third silicon dioxide layer 13 as a stop layer, where the third silicon nitride etching is plasma etching.
Similarly, the third silicon nitride etching is anisotropic etching, the third silicon nitride etching forms third side walls composed of the remaining fourth silicon nitride layers 14 on the side surfaces of the gate structures, and the fourth silicon nitride layers 14 on the top of each gate structure and the surface of the semiconductor substrate 1 between the third side walls are all removed.
Step 54, as shown in fig. 4I, performing a first hydrofluoric acid wet etching to remove the exposed first silicon dioxide layer 8 and the exposed third silicon dioxide layer 13, wherein after the first hydrofluoric acid wet etching is completed, the surface of the first hard mask layer 6 on the top of each gate structure in the formation region of the NMOS is exposed.
As shown in fig. 4I, after the first hydrofluoric acid wet etching, both the first silicon dioxide layer 8 and the third silicon dioxide layer 13 remain on the side surface of the gate structure and are located between the first sidewall and the third sidewall.
The first hard mask layer 6 with the surface exposed is used for being removed, and it can be seen that the first hard mask layer 6 of the formation region of the NMOS has no loss before, and the thickness thereof is d1.
Step 55, as shown in fig. 4J, performing fourth silicon nitride etching by using a phosphoric acid wet etching process, where the fourth silicon nitride etching removes the first hard mask layer 6 remaining in the formation region of the NMOS and removes each third sidewall.
The fourth silicon nitride etching generates silicon loss to the semiconductor substrate 1 between the gate structures, and the thickness of the silicon loss is determined by the thickness d1 of the first hard mask layer 6. As shown in fig. 4I, a part of the surface of the semiconductor substrate 1 is exposed, and for the formation region of the NMOS, a P well 3 is further formed on the surface of the semiconductor substrate 1; in the formation region of PMOS, the surface of the embedded sige epitaxial layer 12 is exposed, so the silicon loss corresponding to the semiconductor substrate, i.e. the silicon substrate 1, is mainly located in the formation region of NMOS. However, compared with the prior art that the etching is performed simultaneously with the overlapping thickness of the first hard mask layer 6 and the second silicon nitride layer 9, in the embodiment of the present invention, the thickness of the silicon nitride to be etched is reduced, that is, the thickness d1 of the first hard mask layer 6 is reduced, so that the semiconductor material loss generated by the fourth silicon nitride etching on the semiconductor substrate 1 can be reduced.
In addition, in step 55, in the embodiment of the present invention, the stacked structure of the first silicon dioxide layer 8 and the third silicon dioxide layer 13, which is reserved between the first sidewall 7 and the third sidewall, is used as a protective sidewall, so that the silicon loss does not affect the critical dimension of the gate structure and the gate dielectric layer. That is, the fourth silicon nitride etching does not etch the side surface of the polysilicon gate 5, so that the critical dimension of the gate structure is not reduced, and meanwhile, the gate dielectric layer is not exposed, so that the quality of the gate dielectric layer is not adversely affected.
Step 56, as shown in fig. 4J, the remaining third silicon dioxide layer 13 and the first silicon dioxide layer 8 are removed.
In the embodiment of the present invention, the remaining third silicon dioxide layer 13 and the first silicon dioxide layer 8 are removed by a hydrofluoric acid wet etching process.
As shown in fig. 4J, after the step 55 is completed, the thickness of the remaining third silicon dioxide layer 13 and the first silicon dioxide layer 8 is smaller, and the corresponding removal process has a larger adverse effect.
In a preferred embodiment, the technology nodes of the PMOS and NMOS are below 28nm, and the following process parameters can be used:
the first hard mask layer 6 has a thickness of
Figure BDA0002512734200000111
The height of the polysilicon gate 5 is
Figure BDA0002512734200000112
The first side wall 7 is formed by overlapping silicon oxide and silicon nitride, and the total thickness of the silicon oxide and the silicon nitride of the first side wall 7 is
Figure BDA0002512734200000113
The first silicon dioxide layer 8 is an atomically deposited silicon dioxide film layer with a thickness of
Figure BDA0002512734200000114
The second silicon nitride layer 9 is an atomic deposition silicon nitride film layer with a thickness of
Figure BDA0002512734200000115
/>
After step 33 is completed, the thickness of the first hard mask layer 6 and the first sidewall 7 at the top corner of the gate structure is greater than the thickness of the first sidewall
Figure BDA0002512734200000121
The process time of the second silicon nitride etching in the step 51 is 120s to 240s.
In step 52, the third silicon dioxide layer 13 is an atomic deposition silicon dioxide film layer with a thickness of
Figure BDA0002512734200000122
The fourth silicon nitride layer 14 is an atomic deposition silicon nitride film layer with a thickness of
Figure BDA0002512734200000123
The process time of the fourth silicon nitride etching in the step 55 is 120s to 240s.
In the embodiment of the present invention, the critical dimension of the gate structure corresponds to the width d2 of the polysilicon gate 5, and because the surface of the well region covered by the polysilicon gate 5 is used for forming a channel, the width of the polysilicon gate 5 corresponds to the length of the channel; as can be seen from a comparison between fig. 4I and fig. 4J, the width d2 of the polysilicon gate 5 is not reduced.
FIG. 5A is a photograph of a top view taken after the corresponding steps of FIG. 4J have been completed; it can be seen that the polysilicon gate 5 has a strip-shaped structure in a top view, and the width of the polysilicon gate 5 is kept as d2. And the top corners of the polysilicon gate 5 are free of silicon germanium residues.
FIG. 5B shows a photograph corresponding to FIG. 4J; in fig. 5B, the first sidewall 7 is not removed, and dimensions of each position are marked in fig. 5B, and a in each dimension indicates
Figure BDA0002512734200000124
It can be seen that d2 is 50nm and the polysilicon gate 5 has a height +>
Figure BDA0002512734200000125
The thicknesses of the first side walls 7 on the two sides of the polysilicon gate 5 are ^ 5>
Figure BDA0002512734200000126
And &>
Figure BDA0002512734200000127
The distances between the top surfaces of the first side walls 7 and the top surface of the polysilicon gate 5 on both sides of the polysilicon gate 5 are ^ and ^ respectively>
Figure BDA0002512734200000128
And &>
Figure BDA0002512734200000129
It can be seen that the semiconductor substrate 1 has a maximum loss thickness of
Figure BDA00025127342000001210
A loss thickness of @nearthe sides of the polysilicon gate 5>
Figure BDA00025127342000001211
The embodiment of the invention makes special arrangement for the structure of the second hard mask layer of the groove 11 of the germanium-silicon epitaxial layer for self-aligned definition PMOS, and the second hard mask layer is arranged to be a superposed structure of the first silicon dioxide layer 8 and the second silicon nitride layer 9, so that the first silicon dioxide layer 8 is arranged between the first hard mask layer 6 and the second silicon nitride layer 9 at the top of the polysilicon gate 5, and thus, when the groove 11 is etched, the second silicon nitride layer 9 is etched by using the first silicon dioxide layer 8 as a stop layer, then the first silicon dioxide layer 8 is etched, and then the semiconductor substrate 1 is etched, so that under the protection of the first silicon dioxide layer 8, the silicon nitride etching process of the second silicon nitride layer 9 can prevent the thickness reduction of the first hard mask layer 6 and the first side wall 7 at the top corner of the gate structure, and after the etching of the semiconductor substrate 1 is finished and the groove 11 is formed, the top corner of the gate structure can remain thicker silicon nitride material, thus preventing the formation of germanium-silicon residue at the top corner of the gate structure in the epitaxial growth of the germanium-silicon epitaxial growth.
In addition, after the embedded silicon germanium epitaxial layer 12 is formed, the thicker silicon nitride layers are respectively removed, mainly, the first hard mask layer 6 and the second silicon nitride layer 9 which are not covered by the first silicon dioxide layer 8 are removed by adopting a phosphoric acid wet etching process; then, a third hard mask layer formed by overlapping the third silicon dioxide layer 13 and the fourth silicon nitride layer 14 is formed, and plasma etching of silicon nitride is performed to form a third side wall formed by the fourth silicon nitride layer 14; then, opening the first silicon dioxide layer 8 and the third silicon dioxide layer 13 to expose the surface of the first hard mask layer 6 on the top of the gate structure; then, the first hard mask layer 6 and the third side wall can be removed under the condition that the first silicon dioxide layer 8 and the third silicon dioxide layer 13 protect the side face of the gate structure, namely, fourth silicon nitride etching is carried out, the fourth silicon nitride etching process can cause a certain loss of the material of the semiconductor substrate 1, and the maximum thickness of the silicon nitride removed by the fourth silicon nitride etching process is the thickness of the first hard mask layer 6; meanwhile, under the protection of the first silicon dioxide layer 8 and the third silicon dioxide layer 13, the fourth silicon nitride etching process can be prevented from generating an etching effect on the side face of the polysilicon gate 5 of the gate structure, so that the loss of the critical dimension of the gate structure can be prevented; in addition, the size of the polysilicon gate 5 of the gate structure is kept good, and the loss of the material of the semiconductor substrate 1 is reduced, so that the gate dielectric layer of the gate structure can be well protected, and the reliability of the gate dielectric layer can be improved; finally, the embodiment of the invention is particularly suitable for the process of the technical node below 28 nm.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (20)

1. A manufacturing method of an embedded germanium-silicon epitaxial layer is characterized by comprising the following steps:
providing a semiconductor substrate for integrating PMOS and NMOS, forming a plurality of grid structures formed by overlapping grid dielectric layers and polysilicon grids on the semiconductor substrate, and forming a first hard mask layer on the top of each grid structure, wherein the first hard mask layer is silicon nitride; forming a first side wall on the side surface of the grid structure, wherein the first side wall is made of silicon nitride;
forming a second hard mask layer formed by overlapping the first silicon dioxide layer and the second silicon nitride layer; the second hard mask layer covers the surfaces of the first hard mask layer and the first side wall corresponding to the gate structure and extends to the surface of the semiconductor substrate outside the gate structure;
step three, carrying out a photoetching process to open the forming area of the PMOS and cover the forming area of the NMOS, and etching to form a groove in the semiconductor substrate at two sides of the gate structure in the forming area of the PMOS in a self-alignment manner, wherein the method comprises the following steps:
step 31, performing first silicon nitride etching by taking the first silicon dioxide layer as a stop layer, wherein the first silicon nitride etching adopts plasma etching; the first silicon nitride etching removes the second silicon nitride layer on the top of the grid structure and the second silicon nitride layer on the surface of the semiconductor substrate between the grid structures; the first time of silicon nitride etching removes the second silicon nitride layers on two sides of the grid structure from the side part; the first silicon dioxide layer protects the first hard mask layer and the first side wall in the first silicon nitride etching process, and the thickness of the first hard mask layer and the thickness of the first side wall at the top angle of the grid structure are prevented from being reduced;
step 32, etching to remove the first silicon dioxide layer on the surface of the semiconductor substrate between the first silicon dioxide layer at the top of the gate structure and the gate structure, and overlapping the first silicon dioxide layer and the second silicon nitride layer reserved on the side surface of the first side wall of the gate structure to form a second side wall;
step 33, performing plasma etching self-alignment on the semiconductor substrate between the second side walls corresponding to the gate structures to form the grooves;
step 34, performing wet etching on the semiconductor substrate to enable the groove to be sigma-shaped;
step four, performing germanium-silicon epitaxial growth to form an embedded germanium-silicon epitaxial layer in the groove;
fifthly, a dielectric stripping process is carried out, the dielectric stripping process is used for stripping the second hard mask layer and the first hard mask layer in the formation area of the NMOS and the second hard mask layer and the first hard mask layer left in the formation area of the PMOS, and the dielectric stripping process comprises the following steps:
step 51, performing second silicon nitride etching by using a phosphoric acid wet etching process, wherein the first hard mask layer which is not covered by the first silicon dioxide layer and the second silicon nitride layer are removed by the second silicon nitride etching;
step 52, forming a third hard mask layer formed by overlapping the third silicon dioxide layer and the fourth silicon nitride layer;
step 53, performing third silicon nitride etching with the third silicon dioxide layer as a stop layer, wherein the third silicon nitride etching adopts plasma etching, the third silicon nitride etching forms third side walls composed of the remaining fourth silicon nitride layers on the side surfaces of the gate structures, and the fourth silicon nitride layers on the surface of the semiconductor substrate between the tops of the gate structures and the third side walls are all removed;
step 54, performing a first hydrofluoric acid wet etching to remove the exposed first silicon dioxide layer and the exposed third silicon dioxide layer, wherein the surface of the first hard mask layer at the top of each gate structure in the formation region of the NMOS is exposed after the first hydrofluoric acid wet etching is completed;
step 55, performing fourth silicon nitride etching by adopting a phosphoric acid wet etching process, wherein the fourth silicon nitride etching removes the first hard mask layer left in the formation area of the NMOS and removes the third side walls;
and 56, removing the residual third silicon dioxide layer and the first silicon dioxide layer.
2. The method of manufacturing an embedded sige epitaxial layer of claim 1 wherein: in the first step, the semiconductor substrate is a silicon substrate.
3. The method of manufacturing an embedded sige epitaxial layer of claim 2 wherein: and forming a field oxide layer on the semiconductor substrate, isolating a plurality of active regions by the field oxide layer, and forming each PMOS and each NMOS in the corresponding active region.
4. The method of manufacturing an embedded sige epitaxial layer of claim 1 or 2 wherein: the first hard mask layer has a thickness of
Figure QLYQS_1
The height of the polysilicon gate is
Figure QLYQS_2
The first side wall is formed by overlapping silicon oxide and silicon nitride, and the total thickness of the first side wall is
Figure QLYQS_3
5. The method of manufacturing an embedded sige epitaxial layer of claim 1 wherein: the gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
6. The method for manufacturing an embedded silicon germanium epitaxial layer according to claim 1, wherein: in the second step, the first silicon dioxide layer is an atomic deposition silicon dioxide film layer with the thickness of
Figure QLYQS_4
The second silicon nitride layer is an atomic deposition silicon nitride film layer with the thickness of
Figure QLYQS_5
7. The method for manufacturing an embedded silicon germanium epitaxial layer according to claim 1, wherein: the photoetching process in the third step comprises the following steps:
sequentially forming a bottom anti-reflection coating and photoresist;
sequentially carrying out exposure and development to form a photoresist pattern, wherein the photoresist pattern opens a forming area of the PMOS and covers a forming area of the NMOS;
and removing the bottom anti-reflection coating of the opening area by taking the photoresist pattern as a mask.
8. The method of manufacturing an embedded sige epitaxial layer of claim 7 wherein: the shape of the groove formed in step 33 is a U shape or a bowl shape, and the etching process of step 33 consumes part of the thickness of the first hard mask layer of the PMOS region and part of the thickness of the second silicon nitride layer of the second sidewall.
9. The method of manufacturing an embedded sige epitaxial layer of claim 8 wherein: after step 33 is completed and before step 34 is started, a wet cleaning process is performed to remove the photoresist and the bottom anti-reflective coating.
10. The method of manufacturing an embedded sige epitaxial layer of claim 9 wherein: the chemical solution used in the wet etching in step 34 includes a tetramethylammonium hydroxide solution.
11. The method of manufacturing an embedded sige epitaxial layer of claim 1 wherein: the germanium-silicon epitaxial growth process of the step four adopts chemical vapor deposition, and comprises the following sub-steps:
growing a germanium-silicon seed layer;
growing a germanium-silicon body layer;
and growing a germanium-silicon cap layer.
12. The method of manufacturing an embedded sige epitaxial layer of claim 4 wherein: the process time of the second silicon nitride etching in the step 51 is 120 to-240 s.
13. The method of manufacturing an embedded sige epitaxial layer of claim 1 wherein: in step 52, the third silicon dioxide layer is an atomic deposition silicon dioxide film layer with a thickness of
Figure QLYQS_6
/>
The fourthThe silicon nitride layer is an atomic deposition silicon nitride film layer with the thickness of
Figure QLYQS_7
14. The method of manufacturing an embedded sige epitaxial layer of claim 4 wherein: the process time of the fourth silicon nitride etching in the step 55 is 120s to 240s.
15. The method of manufacturing an embedded sige epitaxial layer of claim 4 wherein: in step 56, the remaining third silicon dioxide layer and the first silicon dioxide layer are removed by a hydrofluoric acid wet etching process.
16. The method of manufacturing an embedded sige epitaxial layer of claim 2 wherein: the technical nodes of the PMOS and the NMOS are below 28 nm.
17. The method for manufacturing an embedded silicon germanium epitaxial layer according to claim 1 or 16, wherein: the germanium-silicon epitaxial growth in the step four is selective germanium-silicon epitaxial growth;
after step 33 is completed, the thickness of the first hard mask layer and the first sidewall at the top corner of the gate structure is ensured to prevent germanium-silicon residues from being formed at the top corner of the gate structure in the fourth step.
18. The method of manufacturing an embedded sige epitaxial layer of claim 17 wherein: after step 33 is completed, the thickness of the first hard mask layer and the first sidewall at the top corner of the gate structure is greater than the thickness of the first sidewall
Figure QLYQS_8
19. The method of manufacturing an embedded sige epitaxial layer of claim 16 wherein: in step 55, the fourth silicon nitride etching generates silicon loss on the semiconductor substrate between the gate structures, and the thickness of the silicon loss is determined by the thickness of the first hard mask layer.
20. The method of manufacturing an embedded sige epi layer of claim 19 wherein: in step 55, the stacked structure of the first silicon dioxide layer and the third silicon dioxide layer reserved between the first side wall and the third side wall is used as a protective side wall, so that the silicon loss does not affect the critical dimension of the gate structure and the gate dielectric layer.
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