CN111599748A - Method for manufacturing interconnection structure - Google Patents

Method for manufacturing interconnection structure Download PDF

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CN111599748A
CN111599748A CN202010463913.2A CN202010463913A CN111599748A CN 111599748 A CN111599748 A CN 111599748A CN 202010463913 A CN202010463913 A CN 202010463913A CN 111599748 A CN111599748 A CN 111599748A
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etching
layer
dielectric layer
stop layer
opening
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卢俊玮
王冠博
董宗谕
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Nexchip Semiconductor Corp
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Nexchip Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a manufacturing method of an interconnection structure, which comprises the steps of etching a second etching stop layer and a first dielectric layer with partial thickness on a substrate to form a first opening, forming a second dielectric layer on the second etching stop layer, then using the second etching stop layer as a mask to etch the second dielectric layer, the first dielectric layer and the first etching stop layer in sequence to form a groove and a through hole, removing the second etching stop layer while etching the first dielectric layer to form the through hole, and then filling metal in the groove and the through hole to form a metal layer. Compared with the prior art that the grooves and the through holes are filled with metal step by step, the contact resistance of the metal between the grooves and the through holes is reduced, the chemical mechanical grinding process after the metal is filled is reduced, the process flow is shortened, and the production cost is reduced.

Description

Method for manufacturing interconnection structure
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a method for manufacturing an interconnect structure.
Background
With the development of integrated circuit technology, the integration level of integrated circuits and semiconductor technology have been greatly improved. In the semiconductor manufacturing process, the aluminum interconnection line has good conductive performance, and the aluminum has good adhesion performance with dielectric materials and semiconductor materials, so the aluminum interconnection line is widely applied to back-end interconnection of integrated circuits; however, as the integration level is further improved, the size of the wire is smaller and smaller, and the resistance of the aluminum wire is higher, it is difficult to meet the requirement of high current density, so the aluminum interconnection wire is gradually transited to the copper wire.
In back end of line (BEOL) fabrication, a deep trench process for forming a copper interconnect structure is called an Ultra Thick Metal (UTM) interconnect process, and the UTM interconnect process usually forms a trench with a depth of about 3-6 μm, and is generally used in a process for fabricating a radio frequency product inductor.
The UTM interconnection process directly affects the performance and reliability of copper interconnections and the cost of the process, and therefore, reducing the process flow of copper interconnection manufacturing and improving the performance and reliability of copper interconnections become important research points in the industry.
Disclosure of Invention
The invention aims to provide a manufacturing method of an interconnection structure, which is used for reducing process steps, reducing production cost and improving the performance of the interconnection structure.
In order to achieve the above object, the present invention provides a method for manufacturing an interconnect structure, comprising:
providing a substrate, wherein a front metal layer, a first etching stop layer, a first dielectric layer and a second etching stop layer are sequentially formed on the substrate;
etching the second etching stop layer and the first dielectric layer with partial thickness to form a first opening;
forming a second dielectric layer on the second etching stop layer, wherein the second dielectric layer fills the first opening;
etching the second dielectric layer, the second etching stop layer, the first dielectric layer and the first etching stop layer to form a second opening, wherein the front metal layer is exposed out of the second opening; and
filling metal in the second opening to form a metal layer;
optionally, the forming process of the second opening includes:
performing first dry etching to etch the second dielectric layer until the second etching stop layer is exposed to form a groove;
performing a second dry etching to etch the second dielectric layer filled in the first opening with the exposed second etching stop layer as a mask, extending and etching the first dielectric layer corresponding to the first opening to expose the first etching stop layer to form a through hole, and etching to remove the exposed second etching stop layer while etching the second dielectric layer and the first dielectric layer in the first opening to make the trench extend to at least the first dielectric layer;
and carrying out third dry etching, and etching the exposed first etching stop layer until the front metal layer is exposed, so that the through hole extends to the front metal layer.
Optionally, the second dry etching process includes:
etching the second dielectric layer filled in the first opening by using the exposed second etching stop layer as a mask by using a first etching gas, extending and etching the first dielectric layer corresponding to the first opening to a first height, and at least reserving part of the thickness of the second etching stop layer;
and etching the first dielectric layer by using a second etching gas and taking the reserved second etching stop layer as a mask until the first etching stop layer is exposed, and removing the reserved second etching stop layer while etching the first dielectric layer.
Optionally, the first etching gas and the second etching gas both include CF4、CHF3、CH2F2Or C4F8And O2。
Optionally, when the first etching gas is used for etching, the ranges of the etching selection ratios a of the first dielectric layer, the second dielectric layer and the second etching stop layer are as follows: a is more than or equal to 6 and less than or equal to 12.
Optionally, when the second etching gas is used for etching, the range of the etching selection ratio a of the first dielectric layer to the second etching stop layer is as follows: a is more than or equal to 5 and less than or equal to 8.
Optionally, the etching gas for the first dry etching includes CF4And CHF3The etch rate is 50 a/s to 100 a/s.
Optionally, the etching gas for the third dry etching includes CF4、O2And N2And introducing H after etching the first etching stop layer2。
Optionally, the first etching stop layer is made of doped silicon carbide, and the front layer metal and the metal filling the second opening are both copper or copper alloy.
Optionally, the metal layer is an ultra-thick metal layer, and the thickness of the metal layer is greater than that of the front metal layer.
In summary, the present invention provides a method for manufacturing an interconnect structure, which includes etching a second etching stop layer and a first dielectric layer with a partial thickness on a substrate to form a first opening, forming a second dielectric layer on the second etching stop layer, then sequentially etching the second dielectric layer, the first dielectric layer and the first etching stop layer to form a trench and a via using the second etching stop layer as a mask, removing the second etching stop layer while etching the first dielectric layer to form the via, and then filling metal in the trench and the via to form a metal layer. Compared with the prior art in which the grooves and the through holes are filled with metal step by step, the metal contact resistance between the grooves and the through holes is reduced, the process flow is shortened, the production time is saved, and the production cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIGS. 1A-1F are schematic views of a method of fabricating an interconnect structure in accordance with corresponding steps;
FIG. 2 is a flow chart of a method of fabricating an interconnect structure according to one embodiment of the present invention;
fig. 3A to fig. 3H are schematic structural diagrams corresponding to respective steps of a method for manufacturing an interconnect structure according to an embodiment of the invention.
Wherein the reference numbers indicate:
100-a substrate; 101-an interlayer dielectric layer; 102-front metal layer; 103-a first etch stop layer; 104-a first dielectric layer; 105-a second etch stop layer; 106 — a first mask; 107-through holes; 108-a first metal layer; 109-a third etch stop layer; 110-a second dielectric layer; 111-a second mask; 112-a trench; 113-a second metal layer; 114-a passivation layer;
200-a substrate; 201-interlayer dielectric layer; 202-front metal layer; 203-a first etch stop layer; 204-a first dielectric layer; 205-a second etch stop layer; 206-a first photoresist layer; 207-a first opening; 208-a second dielectric layer; 209-a second photoresist layer; 110-a trench; 211-a through hole; 212-a metal layer; 213-passivation layer.
Detailed Description
For the fabrication of copper interconnect structures, the prior art generally uses a conventional Via first (Via) Trench last (Trench) fabrication process, and particularly with reference to fig. 1A to 1F, including the following steps:
first, a substrate 100 is provided, a semiconductor device and a plurality of metal interconnection layers (not shown) are formed on the substrate 100, here, an interlayer dielectric layer 101 and a front metal layer 102 formed in the interlayer dielectric layer 101 are simplified to be shown, then, a first etch stop layer 103, a first dielectric layer 104 and a second etch stop layer 105 are sequentially formed on the interlayer dielectric layer 101, and a first mask 106 is formed on the second etch stop layer 105 to define a Via (Via), as shown in fig. 1A.
Then, the second etch stop layer 105, the first dielectric layer 104, and the first etch stop layer 103 are sequentially etched to expose the front metal layer 102, and a via 107 is formed, as shown in fig. 1B.
Next, the via hole 107 is filled with a first metal layer 108, and the first metal layer 108 is connected to the previous metal layer 102, as shown in fig. 1C. A portion of the first metal layer 108, the second etch stop layer 105 and a portion of the first dielectric layer 104 are removed by a Chemical Mechanical Polishing (CMP) process to form a via structure, as shown in fig. 1D.
Next, a third etch stop layer 109 and a second dielectric layer 110 are formed on the first dielectric layer 104, and a second mask 111 is formed on the second dielectric layer 110 to define a Trench (Trench), as shown in fig. 1D.
Next, the second dielectric layer 110 and the third etching stop layer 109 are sequentially etched to form a trench 112, exposing a portion of the first dielectric layer 104 and the first metal layer 108 in the via 107, as shown in fig. 1E.
Next, the trench 112 is filled with a second metal layer 113, and a planarization process is performed by Chemical Mechanical Polishing (CMP) to remove a portion of the second metal layer 113 covering the surface of the second dielectric layer 110 to form a trench structure, and then a passivation layer 114 is formed on the trench structure, as shown in fig. 1F.
The copper interconnection structure manufactured by the method has multiple process steps and longer production period. The process needs two planarization processes, so that the cost is high; meanwhile, the contact resistance between the metal layers filled twice is influenced by independent etching, and the resistance value is larger.
In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing an interconnect structure, which includes etching a second etching stop layer on a substrate and a first dielectric layer with a partial thickness to form a first opening, forming a second dielectric layer on the second etching stop layer, sequentially etching the second dielectric layer, the first dielectric layer and the first etching stop layer to form a trench and a via using the second etching stop layer as a mask, removing the second etching stop layer while etching the second dielectric layer to form the via, and filling metal in the trench and the via to form a metal layer. Compared with the prior art in which the grooves and the through holes are filled with metal step by step, the method reduces the contact resistance of the metal between the grooves and the through holes, shortens the process flow, saves the production time and reduces the production cost.
The method for fabricating the interconnect structure of the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings, it being understood, however, that the concepts of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. The drawings are in simplified form and are not to scale, but are provided for convenience and clarity in describing embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. Although elements in one drawing may be readily identified as such in other drawings, the present disclosure does not identify each element as being identical to each other in every drawing for clarity of description.
Fig. 2 is a flowchart of a method for manufacturing an interconnect structure provided in this embodiment, and as shown in fig. 2, the method for manufacturing an interconnect structure provided in this embodiment includes:
s01: providing a substrate, wherein a front metal layer, a first etching stop layer, a first dielectric layer and a second etching stop layer are sequentially formed on the substrate;
s02: etching the second etching stop layer and the first dielectric layer with partial thickness to form a first opening;
s03: forming a second dielectric layer on the second etching stop layer, wherein the second dielectric layer fills the first opening;
s04: etching the second dielectric layer, the second etching stop layer, the first dielectric layer and the first etching stop layer to form a second opening, wherein the front metal layer is exposed out of the second opening; and
s05: and filling metal in the second opening to form a metal layer.
Fig. 3A to 3H are schematic structural diagrams corresponding to corresponding steps of the method for manufacturing an interconnect structure according to this embodiment. The method of manufacturing the interconnect structure provided in the present embodiment will be described in detail below with reference to fig. 2 and fig. 3A to 3H. In this embodiment, taking an interconnect structure with an ultra-thick top metal layer as an example, the specific manufacturing method is as follows:
referring to fig. 3A, step S01 is performed to provide a substrate 200 on which a front metal layer 202, a first etch stop layer 203, a first dielectric layer 204 and a second etch stop layer 205 are sequentially formed.
The substrate 200 may be a semiconductor substrate such as a silicon substrate, and may also be made of other materials, such as germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or silicon carbide (SiC) materials. Active devices such as transistors (not shown) and interconnect structures (not shown) connecting the active devices are formed over the active surface of the substrate 200, the interconnect structures including metal lines and vias, which may be formed of pure copper or copper alloys, and which may be formed using a single damascene process and/or a dual damascene process. The interconnect structure includes a plurality of metal layers, namely, Ml, m2.. Mn, with an ultra-thick top metal layer (UTM) formed on the metal layer Mn, which is collectively referred to as a front metal layer 202 in this embodiment. Fig. 3A simply shows only the interlayer dielectric layer 201 and the previous metal layer 202 formed in the interlayer dielectric layer 201, and it should be noted that the "metal layer" referred to herein refers to a collection of metal lines in the same layer.
A first etching stop layer 203, a first dielectric layer 204 and a second etching stop layer 205 are sequentially formed on the interlayer dielectric layer 201. The first etch stop layer 203 may be formed of silicon carbide (NDC) Doped to prevent diffusion of metal in the front metal layer 202 into the first dielectric layer 204. In other embodiments of the present invention, the material of the first etch stop layer 203 may also be silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or the like. The first dielectric layer 204 may be formed of Undoped Silicate Glass (USG), tetraethyl orthosilicate (TEOS), fluorine doped silica glass (FSG), or a low-k (low dielectric constant) dielectric material. The material of the second etch stop layer 205 may be silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or the like. In this embodiment, the material of the first etch stop layer 203 is NDC, the material of the first dielectric layer 204 is Tetraethylorthosilicate (TEOS), and the material of the second etch stop layer 205 is silicon oxynitride (SiON).
Referring to fig. 3A and 3B, step S02 is performed to etch the second etch stop layer 205 and a portion of the thickness of the first dielectric layer 204 to form a first opening 207. Specifically, first, a first photoresist layer 206 is formed on the second etch stop layer 205 and patterned to define a pattern of a first opening 207, as shown in fig. 3A; then, using the patterned first photoresist layer 206 as a mask, the second etch stop layer 205 and a portion of the thickness of the first dielectric layer 204 are etched to form a first opening 207, and the first photoresist layer 206 is removed by ashing, as shown in fig. 3B. A pattern of a via hole to be formed subsequently is defined by the first opening 207, an etching depth of the first opening 207 is adapted to an etching method of the via hole to be formed subsequently, in this embodiment, the etching of the first opening 207 extends to the first dielectric layer 204, and in other embodiments of the present invention, the etching of the first opening 207 may also be stopped at the second etching stop layer 205.
Referring to fig. 3C, step S03 is performed to form a second dielectric layer 208 on the second etch stop layer 205, wherein the second dielectric layer 208 fills the first opening 207. In this embodiment, the material of the second dielectric layer 208 is the same as the material of the first dielectric layer, and is tetraethyl orthosilicate (TEOS), the thickness of the second dielectric layer 208 directly determines the subsequent formation of the metal layer, and for the super-thick metal layer, the thickness of the second dielectric layer 208 ranges from 3 μm to 6 μm.
Referring to fig. 3C to fig. 3G, step S04 is executed to etch the second dielectric layer 208, the second etch stop layer 205, the first dielectric layer 204 and the first etch stop layer 203 to form a second opening, and the second opening exposes the front metal layer 202. The method for forming the second opening comprises the following steps:
performing a first dry etching to etch the second dielectric layer 208 until a portion of the second etch stop layer 205 is exposed, so as to form a trench 210;
performing a second dry etching to etch the second dielectric layer 208 filled in the first opening 207 with the exposed portion of the second etch stop layer 205 as a mask, and extending and etching the first dielectric layer 204 to expose the first etch stop layer 203 to form a via 211, and etching to remove the exposed portion of the second etch stop layer 205 while etching the second dielectric layer 208 and the first dielectric layer 204 in the first opening 207, so that the trench 210 extends at least to the first dielectric layer 204;
and performing third dry etching, namely etching the exposed first etching stop layer 203 until the front metal layer 202 is exposed, so that the through hole 211 extends to the front metal layer 202.
Specifically, referring to fig. 3C and 3D, first, a first dry etching is performed to form a second photoresist layer 209 on the second dielectric layer 208, and the second photoresist layer 209 is patterned to define a pattern of a trench 210; then, the second dielectric layer 208 is etched by using the patterned second photoresist layer 209 as a mask until a portion of the second etch stop layer 205 is exposed, thereby forming a trench 210. Preferably, a bottom anti-reflective layer BARC (not shown) is formed on the second dielectric layer 208 before the second photoresist layer 209 is formed, and is removed by ashing together with the second photoresist layer 209 after the trench 210 is etched.
Etching the second dielectric layer 208 by a dry etching process until part of the second etch stop layer 205 is exposed, wherein the etching gas is CF4And CHF3The etching rate of the second dielectric layer 208 is
Figure BDA0002511927320000081
For example
Figure BDA0002511927320000082
Or
Figure BDA0002511927320000083
And the like. In this embodiment, the etching rate of the second dielectric layer is higher than that of a dielectric layer in the prior art, the higher etching rate is selected to relatively reduce the etching time of the second dielectric layer 208, and the reduction of the etching time of the second dielectric layer 208 relatively reduces the exposure time of the second etching stop layer 205, and the additional etching of the second etching stop layer 205 while etching the second dielectric layer 208 is also relatively reduced, so that the second etching stop layer 205 can retain a sufficient thickness for subsequent processes.
Next, referring to fig. 3E, a second dry etching is performed, and first, a first etching gas is used to etch the second dielectric layer 208 filled in the first opening by using the exposed portion of the second etching stop layer 205 as a mask, and the first dielectric layer 204 corresponding to the first opening is extended and etched to the first height D1, and at least a portion of the thickness of the second etching stop layer is remained. Illustratively, the first etching gas comprises CF4、CHF3Or C4F8And O2For example, C can be used4F8And O2As an etching gas, the first dielectric layer 204 and the second dielectric layer 208 are subjected toAnd etching with high selectivity. The range of the etching selection ratio a of the first dielectric layer 204 to the second etching stop layer 205 is as follows: 6 ≦ a ≦ 12, for example, a ≦ 7, a ≦ 9, a ≦ 11, and the like, and accordingly, when the second dielectric layer 208 filled in the first opening is etched, the etching selection ratio a of the second dielectric layer 208 to the second etch stop layer 205 ranges from: a is more than or equal to 6 and less than or equal to 12. The first dielectric layer 204 is etched with a high selectivity ratio to a first height D1, defining the via 211 pattern while leaving a thickness of the second etch stop layer 205 to mask the next etching of the first dielectric layer 204.
Then, referring to fig. 3F, using a second etching gas and the remaining second etching stop layer 205 as a mask, etching the first dielectric layer 204 until the first etching stop layer 203 is exposed, forming a through hole 211, and etching the first dielectric layer 204 while removing the remaining portion of the second etching stop layer 205, so that the trench 210 at least extends to the first dielectric layer 204. Illustratively, the second etching gas comprises CF4、CHF3Or C4F8And O2The etching selectivity of the first dielectric layer 204 is smaller than that of the first dry etching, and the range of the etching selectivity a of the first dielectric layer 204 to the second etching stop layer 205 is as follows: 5 ≦ a ≦ 8, e.g., a ═ 6, a ═ 7, or a ═ 8, and the like. The first etching gas and the second etching gas may be the same in type, or different in type, and when the first dielectric layer 204 is etched to the first height D1, the first etching gas and the second etching gas are switched. In this embodiment, the second etching stop layer 205 is etched while the first dielectric layer 204 with the remaining thickness is etched, so as to avoid adjusting the etching gas again to etch the second etching stop layer 205 after the first dielectric layer 204 with the remaining thickness is etched, and relatively reduce the process time.
Then, referring to fig. 3G, a third dry etching is performed to etch the exposed first etching stop layer 203 to expose the front metal layer 202, so that the through hole 211 extends to the through holeThe front metal layer 202. In this embodiment, the material of the first etching stop layer 203 is doped silicon carbide (NDC), a Liner Removal (LRM) process is used to etch the first etching stop layer 203, and the etching gas includes CF4、O2And N2And the like. In the LRM etching process, O is introduced2Therefore, the front metal layer 202 (e.g. copper) exposed after etching the first etch stop layer 203 is oxidized, so that H is introduced after LRM etching2Reducing the oxidized metal. In other embodiments of the present invention, the etching gas may also be CH2F2、O2And N2After LRM etching, CO and CO can be used2The gas protects the metal in the front metal layer.
It should be noted that, in the process of forming the through hole in this embodiment, the second etching stop layer 205 is removed while the first dielectric layer 204 is etched, so that it is not necessary to strictly control the etching gas to realize a high etching selectivity ratio when the first etching stop layer 203 is etched, which is convenient for etching the first etching stop layer 203 by using the LRM process, and is convenient for subsequently introducing H2And carrying out metal reduction. In other embodiments of the present invention, the second etch stop layer 205 may also be removed step by step during the process of removing the first dielectric layer 204 and the first etch stop layer 203 by etching, which is not limited herein.
In this embodiment, the second dry etching is an etching having a high selection ratio for the first dielectric layer 204 and the second etching stop layer 205, but the selection ratio is different in the two dry etching, because different etching selection ratios are adopted, the second etching stop layer 205 is used as a mask for etching the trench 210 and the via hole 211 to etch the dielectric layers (the first dielectric layer 204 and the second dielectric layer 208), and is etched and removed while the first dielectric layer 204 is etched, so that the process steps are reduced, and the generation period is shortened.
In this embodiment, the trench 210 and the through hole 211 are etched by a dry etching process, which includes but is not limited to reactive ion etching, ion beam etching, plasma etching or laser cuttingPreferably, the etching of the trenches and vias can be performed by changing the etching gas using an advanced reactive ion etching process (RIE). The etching gas includes a mixture gas of a fluorocarbon (CF) -based gas and/or a hydrofluorocarbon (CHF) -based gas and a carrier gas including, but not limited to, argon (Ar), helium (He), or nitrogen (N)2) Etc. O may be added to the etching gas according to the etching requirement2Or CO or the like. In addition, the etching of the trench 210 and the via 211 both adopt a self-aligned lithography process, which is not described herein again.
Referring to fig. 3H, step S05 is performed to fill the second opening with metal to form a metal layer 212. In this embodiment, the metal filled in the second opening is copper, for example, the copper metal may be filled in the second opening through a copper electroplating (Cu Plating) process, and then the excess copper metal is removed through a Chemical Mechanical Polishing (CMP) process. Optionally, a metal barrier layer and a copper seed layer may be deposited in the second opening before the electroplated copper fills the second opening, so as to prevent the copper formed subsequently from infiltrating into other layers to cause short circuit of the device and enable the metal copper to be formed better in adhesion. The material of the metal barrier layer can be one or a combination of titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN). In addition, after the completion of the filling of the electroplated copper and the removal of the excess copper metal by chemical mechanical polishing, a passivation layer 212 is formed on the second dielectric layer 208 and the metal layer 212, wherein the material of the passivation layer 212 may be silicon oxide (SiO)2) Silicon nitride (SiN), silicon oxynitride (SiON), or the like.
In the embodiment, the groove and the through hole are sequentially formed through a dry etching process, then a metal filling process is performed at one time to form the metal layer, and compared with the step-by-step metal filling of the groove and the through hole, the contact resistance of metal between the groove and the through hole is reduced, and particularly for an interconnection structure with an ultra-thick top metal layer, the performance and reliability are improved more obviously.
In summary, the present invention provides a method for manufacturing an interconnect structure, which includes etching a second etching stop layer and a first dielectric layer with a partial thickness on a substrate to form a first opening, forming a second dielectric layer on the second etching stop layer, then sequentially etching the second dielectric layer, the first dielectric layer and the first etching stop layer to form a trench and a via using the second etching stop layer as a mask, removing the second etching stop layer while etching the first dielectric layer to form the via, and then filling metal in the trench and the via to form a metal layer. Compared with the prior art that the grooves and the through holes are filled with metal step by step, the contact resistance of the metal between the grooves and the through holes is reduced, the chemical mechanical grinding process after the metal is filled is reduced, the process flow is shortened, and the production cost is reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (10)

1. A method of fabricating an interconnect structure, comprising:
providing a substrate, wherein a front metal layer, a first etching stop layer, a first dielectric layer and a second etching stop layer are sequentially formed on the substrate;
etching the second etching stop layer and the first dielectric layer with partial thickness to form a first opening;
forming a second dielectric layer on the second etching stop layer, wherein the second dielectric layer fills the first opening;
etching the second dielectric layer, the second etching stop layer, the first dielectric layer and the first etching stop layer to form a second opening, wherein the front metal layer is exposed out of the second opening; and
and filling metal in the second opening to form a metal layer.
2. The method of claim 1, wherein the forming of the second opening comprises:
performing first dry etching to etch the second dielectric layer until the second etching stop layer is exposed to form a groove;
performing a second dry etching to etch the second dielectric layer filled in the first opening with the exposed second etching stop layer as a mask, extending and etching the first dielectric layer corresponding to the first opening to expose the first etching stop layer to form a through hole, and etching to remove the exposed second etching stop layer while etching the second dielectric layer and the first dielectric layer in the first opening to make the trench extend to at least the first dielectric layer;
and carrying out third dry etching, and etching the exposed first etching stop layer until the front metal layer is exposed, so that the through hole extends to the front metal layer.
3. The method for manufacturing an interconnect structure according to claim 2, wherein the second dry etching process comprises:
etching the second dielectric layer filled in the first opening by using the exposed second etching stop layer as a mask by using a first etching gas, extending and etching the first dielectric layer corresponding to the first opening to a first height, and at least reserving part of the thickness of the second etching stop layer;
and etching the first dielectric layer by using a second etching gas and taking the reserved second etching stop layer as a mask until the first etching stop layer is exposed, and removing the reserved second etching stop layer while etching the first dielectric layer.
4. The method of claim 3, wherein the first etching gas and the second etching gas each comprise CF4、CHF3、CH2F2Or C4F8And O2。
5. The method for manufacturing an interconnect structure according to claim 4, wherein when the first etching gas is used for etching, the ranges of etching selection ratios A of the first dielectric layer, the second dielectric layer and the second etching stop layer are as follows: a is more than or equal to 6 and less than or equal to 12.
6. The method for manufacturing an interconnect structure according to claim 4, wherein when the second etching gas is used for etching, an etching selection ratio A of the first dielectric layer to the second etching stop layer is in a range of: a is more than or equal to 5 and less than or equal to 8.
7. The method for manufacturing an interconnect structure according to claim 4, wherein the etching gas of the first dry etching comprises CF4And CHF3The etch rate is 50 a/s to 100 a/s.
8. The method for manufacturing an interconnect structure according to claim 7, wherein the etching gas for the third dry etching comprises CF4、O2And N2And introducing H after etching the first etching stop layer2。
9. The method of claim 1, wherein the material of the first etch stop layer is doped silicon carbide, and the front layer metal and the metal filling the second opening are both copper or copper alloy.
10. The method of claim 1, wherein the metal layer is an ultra-thick metal layer, and the thickness of the metal layer is greater than that of the previous metal layer.
CN202010463913.2A 2020-05-27 2020-05-27 Method for manufacturing interconnection structure Pending CN111599748A (en)

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Cited By (1)

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CN112967997A (en) * 2021-02-02 2021-06-15 长江存储科技有限责任公司 Back-end metal filling method, filling device, storage device and semiconductor device

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CN102610563A (en) * 2012-04-06 2012-07-25 上海集成电路研发中心有限公司 Method for preparing copper dual damascene structure
CN103972164A (en) * 2014-05-21 2014-08-06 上海华力微电子有限公司 Copper-interconnection Damascus process method
CN110504210A (en) * 2019-08-26 2019-11-26 上海华力集成电路制造有限公司 The manufacturing process of copper wiring technique

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Publication number Priority date Publication date Assignee Title
CN102610563A (en) * 2012-04-06 2012-07-25 上海集成电路研发中心有限公司 Method for preparing copper dual damascene structure
CN103972164A (en) * 2014-05-21 2014-08-06 上海华力微电子有限公司 Copper-interconnection Damascus process method
CN110504210A (en) * 2019-08-26 2019-11-26 上海华力集成电路制造有限公司 The manufacturing process of copper wiring technique

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