CN111599675A - Self-aligned double patterning method - Google Patents
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- CN111599675A CN111599675A CN202010446514.5A CN202010446514A CN111599675A CN 111599675 A CN111599675 A CN 111599675A CN 202010446514 A CN202010446514 A CN 202010446514A CN 111599675 A CN111599675 A CN 111599675A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
The invention provides a self-aligned double patterning method, which comprises the steps of forming a silicon-containing filling material layer, an anti-reflection layer and a photoresist pattern on a layer to be etched; etching the silicon-containing filling material layer by taking the photoresist pattern as a mask and carrying out heat treatment on the silicon-containing filling material layer to ensure that the silicon-containing filling material pattern is contracted to form a silicon dioxide pattern; depositing an etching mask layer and etching back to form a side wall on the side wall of the silicon dioxide pattern; removing the silicon dioxide pattern; and etching the layer to be etched to form a target pattern. The invention utilizes the characteristic that the silicon-containing filling material shrinks after high-temperature heat treatment to obtain smaller pattern spacing compared with the traditional self-aligned double patterning process, thereby being beneficial to the miniaturization of a semiconductor device; and the silicon-containing filling material can be used as a sacrificial layer in a self-aligned double patterning method by utilizing the characteristic that silicon dioxide is generated after high-temperature heat treatment, so that the steps of growing, etching and removing the sacrificial layer in the traditional process are omitted, the process flow is simplified, and the cost is saved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a self-aligned double patterning method.
Background
As for the technology nodes of 14 nm and below, a single Patterning technology using a Deep Ultraviolet (DUV) lithography process cannot meet the requirement, but an Extreme Ultraviolet (EUV) lithography process or a Double Patterning (SADP) technology must be used as one of the Double Patterning technologies, and a Self-aligned Double Patterning (SADP) technology uses only one lithography process, but uses less one lithography process than the conventional Double Patterning technology, and has a certain cost advantage, so the Self-aligned Double Patterning technology is gradually adopted in the industry.
In the self-aligned double patterning process flow, the distance between the target patterns depends on the size of the previously formed photoresist patterns, so that as the miniaturization requirement of the semiconductor device patterns becomes higher and higher, the distance between the target patterns also needs to be smaller and smaller, and accordingly, the size of the photoresist patterns also needs to be smaller and smaller, which provides a high challenge to the photolithography process and increases the difficulty of the photolithography process. In addition, although the self-aligned double patterning process only uses one photolithography process, the self-aligned double patterning process still uses a plurality of thin film deposition and etching processes, and the process is still complicated.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method of self-aligned double patterning, which is used to solve the problems of high requirement on the photolithography process and complex process in the miniaturization of the pattern in the prior art.
To achieve the above and other related objects, the present invention provides a method of self-aligned double patterning, the method comprising at least the steps of:
growing a layer to be etched on a silicon wafer;
sequentially forming a silicon-containing filling material layer, an anti-reflection layer and a photoresist on the layer to be etched, and carrying out exposure and development on the photoresist to form a photoresist pattern;
etching the silicon-containing filling material layer by taking the photoresist pattern as a mask to form a silicon-containing filling material pattern;
fourthly, carrying out heat treatment on the silicon-containing filling material pattern to enable the silicon-containing filling material pattern to shrink to form a silicon dioxide pattern;
depositing an etching mask layer covering the silicon dioxide pattern and the layer to be etched on the layer to be etched;
sixthly, etching the etching mask layer until the top of the silicon dioxide pattern and the surface of the layer to be etched are exposed, and forming etching mask layer side walls on the side walls of the silicon dioxide pattern;
seventhly, etching and removing the silicon dioxide pattern;
and step eight, etching the layer to be etched by taking the etching mask layer side wall as a mask to form a target pattern.
Preferably, the layer to be etched is a dielectric layer.
Preferably, the material of the layer to be etched is at least one of silicon dioxide, silicon nitride, silicon oxynitride, monocrystalline silicon and polycrystalline silicon.
Preferably, the layer to be etched is a non-dielectric layer.
Preferably, the material of the layer to be etched is at least one of metal nitride, metal oxide and metal.
Preferably, the method for forming the silicon-containing filling material layer on the layer to be etched in the second step comprises: and spin-coating a silicon-containing filling material on the layer to be etched, and baking the silicon-containing filling material to form the silicon-containing filling material layer.
Preferably, the silicon-containing filler material layer formed in step two has a silicon content of 30-97%.
Preferably, the temperature for baking the silicon-containing filling material in the step two is 100-200 ℃.
Preferably, the temperature for baking the silicon-containing filler material in the second step is 150 ℃.
Preferably, the time for baking the silicon-containing filler material in the second step is 60 to 300 seconds.
Preferably, the time for baking the silicon-containing filler material in the second step is 180 seconds.
Preferably, the method for etching the silicon-containing filling material layer in the third step comprises: and (3) carrying out plasma dry etching by using fluorine-based gas as etching gas.
Preferably, the temperature for performing the heat treatment on the silicon-containing filling material pattern in the fourth step is 400-.
Preferably, the heat treatment time for the pattern of silicon-containing filler material in step four is 30 to 300 minutes.
Preferably, the gas atmosphere for performing the heat treatment on the pattern of the silicon-containing filling material in the fourth step includes at least one of hydrogen peroxide vapor, water vapor, oxygen and ozone.
Preferably, the shrinkage ratio of the silicon filling material pattern in step four is 10-30%.
Preferably, in the process of removing the silicon dioxide pattern by etching in the seventh step, the etching selection ratio of the etching mask layer side wall to the silicon dioxide pattern is greater than or equal to 3: 1.
Preferably, the method for removing the silicon dioxide pattern by etching in the seventh step includes at least one of dry etching and wet etching.
As described above, the self-aligned double patterning method of the present invention has the following advantages: the invention can obtain smaller pattern spacing than the traditional self-alignment double patterning method by utilizing the characteristic that the silicon-containing filling material shrinks after being subjected to high-temperature heat treatment, thereby being beneficial to the miniaturization of a semiconductor device; and the silicon-containing filling material can be used as a sacrificial layer in the self-aligned double patterning method by utilizing the characteristic that silicon dioxide is generated after high-temperature heat treatment, so that the steps of growing the sacrificial layer, etching the sacrificial layer and removing the sacrificial layer in the traditional self-aligned double patterning method are omitted, the process flow is simplified, and the cost is saved.
Drawings
FIGS. 1 to 8 are schematic views of structures formed in the self-aligned double patterning process according to the present invention;
FIG. 9 is a flow chart of the self-aligned double patterning method of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Fig. 9 shows a flow chart of the self-aligned double patterning method of the present invention, and fig. 9 shows a flow chart of the self-aligned double patterning method of the present invention. The self-aligned double patterning method at least comprises the following steps: growing a layer to be etched on a silicon wafer; sequentially forming a silicon-containing filling material layer, an anti-reflection layer and a photoresist on the layer to be etched, and carrying out exposure and development on the photoresist to form a photoresist pattern; etching the silicon-containing filling material layer by taking the photoresist pattern as a mask to form a silicon-containing filling material pattern; fourthly, carrying out heat treatment on the silicon-containing filling material pattern to enable the silicon-containing filling material pattern to shrink to form a silicon dioxide pattern; depositing an etching mask layer covering the silicon dioxide pattern and the layer to be etched on the layer to be etched; sixthly, etching the etching mask layer until the top of the silicon dioxide pattern and the surface of the layer to be etched are exposed, and forming etching mask layer side walls on the side walls of the silicon dioxide pattern; seventhly, etching and removing the silicon dioxide pattern; and step eight, etching the layer to be etched by taking the etching mask layer side wall as a mask to form a target pattern.
The self-aligned double patterning method in this embodiment includes the following steps:
growing a layer to be etched on a silicon wafer; further, the layer to be etched is a dielectric layer. Furthermore, the material of the layer to be etched (dielectric layer) is at least one of silicon dioxide, silicon nitride, silicon oxynitride, monocrystalline silicon and polycrystalline silicon. In other embodiments, the layer to be etched may also be a non-dielectric layer, and further, the material of the layer to be etched (non-dielectric layer) is at least one of metal nitride, metal oxide, and metal. As shown in fig. 1, a layer to be etched 110 is grown on a silicon wafer 100; the layer to be etched 110 is used to form a final target pattern, and the layer to be etched 110 may be a dielectric layer, such as silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, or the like; or a non-dielectric layer such as titanium nitride, tantalum nitride, metal, etc.; combinations of two or more of the above materials are also possible.
Sequentially forming a silicon-containing filling material layer, an anti-reflection layer and a photoresist on the layer to be etched, and carrying out exposure and development on the photoresist to form a photoresist pattern; further, the method for forming the silicon-containing filling material layer on the layer to be etched in the second step comprises the following steps: and spin-coating a silicon-containing filling material on the layer to be etched, and baking the silicon-containing filling material to form the silicon-containing filling material layer. Still further, the silicon content of the silicon-containing filler material layer formed in the second step is 30-97%. Further, the temperature for baking the silicon-containing filling material is 100-200 ℃. In the second step of this embodiment, the baking temperature of the silicon-containing filling material is 150 ℃. Further, the time for baking the silicon-containing filling material in the second step is 60-300 seconds. In the second step of this embodiment, the time for baking the silicon-containing filler material is 180 seconds.
As shown in fig. 2, a silicon-containing filling material 170 is spin-coated on one of the layers to be etched 110 and baked, and then an anti-reflection layer 130 and a photoresist are formed, and the photoresist is exposed and developed to form the photoresist pattern 141; the photoresist pattern 141 has a size a.
Etching the silicon-containing filling material layer by taking the photoresist pattern as a mask to form a silicon-containing filling material pattern; further, in this embodiment, the method for etching the silicon-containing filling material layer in the third step includes: and (3) carrying out plasma dry etching by using fluorine-based gas as etching gas.
As shown in fig. 3, the photoresist pattern 141 is used as a mask to etch and form the silicon-containing filling material pattern 171; the etching is plasma dry etching using fluorine-based gas as etching gas, and since the silicon-containing filling material pattern 171 is formed by etching using the photoresist pattern 141 as a mask, the dimension c of the silicon-containing filling material pattern 171 depends on the dimension a of the photoresist pattern 141.
Fourthly, carrying out heat treatment on the silicon-containing filling material pattern to enable the silicon-containing filling material pattern to shrink to form a silicon dioxide pattern; further, the temperature for performing the heat treatment on the silicon-containing filling material pattern in the fourth step is 400-. And further, in the fourth step, the heat treatment time for the pattern of the silicon-containing filling material is 30-300 minutes. Furthermore, the gas atmosphere for heat treatment of the pattern of the silicon-containing filling material in the fourth step includes at least one of hydrogen peroxide vapor, water vapor, oxygen and ozone. Further, the shrinkage ratio of the silicon filling material pattern in the fourth step is 10-30%.
As shown in fig. 4, the fourth step is to perform a heat treatment on the silicon-containing filler material pattern 171 to form the silicon dioxide pattern 172 after shrinkage; in the fourth step of the present invention, in the (high temperature) heat treatment process of the pattern of the silicon-containing filling material, silicon atoms in the pattern 171 of the silicon-containing filling material chemically react with hydrogen peroxide vapor, water vapor or oxygen to generate silicon dioxide, and at the same time, the pattern shrinks to form the shrunk pattern 172 of silicon dioxide, in the present invention, the shrinkage proportion of the pattern 171 of the silicon-containing filling material after the high temperature heat treatment is between 10% and 30%, so that the dimension d of the shrunk pattern 172 of silicon dioxide is 10% to 30% smaller than the dimension c of the pattern 171 of the silicon-containing filling material, that is, 0.7c is less than or equal to d is less than or equal to 0.9 c.
Depositing an etching mask layer covering the silicon dioxide pattern and the layer to be etched on the layer to be etched; as shown in fig. 5, depositing the etch mask layer 150; the etch mask layer 150 is required to cover the top and side of the silicon dioxide pattern 172 in step four, and the upper surface of the layer to be etched 110 in step one.
Sixthly, etching the etching mask layer until the top of the silicon dioxide pattern and the surface of the layer to be etched are exposed, and forming etching mask layer side walls on the side walls of the silicon dioxide pattern; as shown in fig. 6, the etching mask layer 150 is etched six times to form the etching mask layer sidewall 151; after etching back the etching mask layer 150, the top of the silicon dioxide pattern 172 in the fourth step and the upper surface of the layer to be etched 110 in the first step are exposed, and the etching mask layer sidewall 151 is formed on the side surface of the silicon dioxide pattern 172.
Seventhly, etching and removing the silicon dioxide pattern; further, in the seventh step, in the process of removing the silicon dioxide pattern by etching, the etching selection ratio of the etching mask layer side wall to the silicon dioxide pattern is greater than or equal to 3: 1. The method for removing the silicon dioxide pattern by etching in the seventh step comprises at least one of dry etching and wet etching.
As shown in fig. 7, the silicon dioxide pattern 172 is removed, and the etching mask layer sidewall 151 is left; because the etching mask layer side wall 151 and the silicon dioxide pattern 172 have a certain etching selection ratio, the etching selection ratio of the etching mask layer side wall to the silicon dioxide pattern is greater than or equal to 3:1, the silicon dioxide pattern 172 can be removed by an etching method, and the etching mask layer side wall 151 is reserved.
And step eight, etching the layer to be etched by taking the etching mask layer side wall as a mask to form a target pattern. As shown in fig. 8, the layer to be etched 110 is etched by using the etching mask layer sidewall 172 as a mask, so as to form the finally required target pattern 111; the distance e between the adjacent target patterns 111 depends on the size a of the photoresist pattern in the second step and the shrinkage (c-d) of the silicon dioxide pattern 172 in the fourth step, and when the shrinkage is larger, the distance e between the adjacent target patterns 111 is smaller, thereby facilitating the miniaturization of the semiconductor device.
In summary, the present invention utilizes the property of the silicon-containing filling material shrinking after high temperature heat treatment to obtain a smaller pattern pitch than the conventional self-aligned dual patterning method, which is beneficial to the miniaturization of the semiconductor device; and the silicon-containing filling material can be used as a sacrificial layer in the self-aligned double patterning method by utilizing the characteristic that silicon dioxide is generated after high-temperature heat treatment, so that the steps of growing the sacrificial layer, etching the sacrificial layer and removing the sacrificial layer in the traditional self-aligned double patterning method are omitted, the process flow is simplified, and the cost is saved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (18)
1. A method of self-aligned double patterning, the method comprising:
growing a layer to be etched on a silicon wafer;
sequentially forming a silicon-containing filling material layer, an anti-reflection layer and a photoresist on the layer to be etched, and carrying out exposure and development on the photoresist to form a photoresist pattern;
etching the silicon-containing filling material layer by taking the photoresist pattern as a mask to form a silicon-containing filling material pattern;
fourthly, carrying out heat treatment on the silicon-containing filling material pattern to enable the silicon-containing filling material pattern to shrink to form a silicon dioxide pattern;
depositing an etching mask layer covering the silicon dioxide pattern and the layer to be etched on the layer to be etched;
sixthly, etching the etching mask layer until the top of the silicon dioxide pattern and the surface of the layer to be etched are exposed, and forming etching mask layer side walls on the side walls of the silicon dioxide pattern;
seventhly, etching and removing the silicon dioxide pattern;
and step eight, etching the layer to be etched by taking the etching mask layer side wall as a mask to form a target pattern.
2. The method of self-aligned double patterning as claimed in claim 1, wherein: and the layer to be etched in the first step is a dielectric layer.
3. The method of self-aligned double patterning as claimed in claim 2, wherein: and in the first step, the layer to be etched is made of at least one of silicon dioxide, silicon nitride, silicon oxynitride, monocrystalline silicon and polycrystalline silicon.
4. The method of self-aligned double patterning as claimed in claim 1, wherein: and the layer to be etched in the first step is a non-dielectric layer.
5. The method of self-aligned double patterning as claimed in claim 4, wherein: and in the first step, the layer to be etched is made of at least one of metal nitride, metal oxide and metal.
6. The method of self-aligned double patterning as claimed in claim 1, wherein: in the second step, the method for forming the silicon-containing filling material layer on the layer to be etched comprises the following steps: and spin-coating a silicon-containing filling material on the layer to be etched, and baking the silicon-containing filling material to form the silicon-containing filling material layer.
7. The method of self-aligned double patterning as claimed in claim 1, wherein: the silicon content of the silicon-containing filling material layer formed in the second step is 30-97%.
8. The method of self-aligned double patterning as claimed in claim 6, wherein: in the second step, the temperature for baking the silicon-containing filling material is 100-200 ℃.
9. The method of self-aligned double patterning as claimed in claim 8, wherein: in the second step, the baking temperature of the silicon-containing filling material is 150 ℃.
10. The method of self-aligned double patterning as claimed in claim 6, wherein: and in the second step, the time for baking the silicon-containing filling material is 60-300 seconds.
11. The method of self-aligned double patterning as claimed in claim 10, wherein: and in the second step, the time for baking the silicon-containing filling material is 180 seconds.
12. The method of self-aligned double patterning as claimed in claim 1, wherein: the method for etching the silicon-containing filling material layer in the third step comprises the following steps: and (3) carrying out plasma dry etching by using fluorine-based gas as etching gas.
13. The method of self-aligned double patterning as claimed in claim 1, wherein: the temperature for performing the heat treatment on the silicon-containing filling material pattern in the fourth step is 400-.
14. The method of self-aligned double patterning as claimed in claim 1, wherein: and in the fourth step, the heat treatment time for the pattern of the silicon-containing filling material is 30-300 minutes.
15. The method of self-aligned double patterning as claimed in claim 1, wherein: in the fourth step, the gas atmosphere for carrying out heat treatment on the pattern of the silicon-containing filling material comprises at least one of hydrogen peroxide steam, water vapor, oxygen and ozone.
16. The method of self-aligned double patterning as claimed in claim 1, wherein: and the shrinkage ratio of the silicon filling material pattern in the fourth step is 10-30%.
17. The method of self-aligned double patterning as claimed in claim 1, wherein: and seventhly, in the process of removing the silicon dioxide pattern by etching, the etching selection ratio of the etching mask layer side wall to the silicon dioxide pattern is greater than or equal to 3: 1.
18. The method of self-aligned double patterning as claimed in claim 1, wherein: and seventhly, the method for removing the silicon dioxide pattern by etching comprises at least one of dry etching or wet etching.
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| US20180204719A1 (en) * | 2017-01-13 | 2018-07-19 | Varian Semiconductor Equipment Associates, Inc. | Multiple patterning approach using ion implantation |
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2020
- 2020-05-25 CN CN202010446514.5A patent/CN111599675A/en active Pending
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| CN1234607A (en) * | 1998-04-27 | 1999-11-10 | 日本电气株式会社 | Method for forming slotted isolation structure |
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| CN101276728A (en) * | 2007-03-30 | 2008-10-01 | 南亚科技股份有限公司 | Method for transferring graphic pattern |
| US20110034035A1 (en) * | 2009-08-06 | 2011-02-10 | Applied Materials, Inc. | Stress management for tensile films |
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| US20180204719A1 (en) * | 2017-01-13 | 2018-07-19 | Varian Semiconductor Equipment Associates, Inc. | Multiple patterning approach using ion implantation |
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