CN111599391B

CN111599391B - Scalable multi-port bulk memory cell based on dynamic reconfigurable technology

Info

Publication number: CN111599391B
Application number: CN202010448230.XA
Authority: CN
Inventors: 陈波寅; 徐彦峰; 庄雪亚; 单悦尔; 闫华; 董宜平
Original assignee: Wuxi Zhongwei Yixin Co Ltd; China Key System and Integrated Circuit Co Ltd
Current assignee: Wuxi Zhongwei Yixin Co Ltd; China Key System and Integrated Circuit Co Ltd
Priority date: 2020-05-25
Filing date: 2020-05-25
Publication date: 2022-03-22
Anticipated expiration: 2040-05-25
Also published as: CN111599391A

Abstract

The invention discloses an expandable multiport blocky memory cell based on a dynamic reconfigurable technology, which relates to the field of programmable logic devices, wherein the expandable multiport blocky memory cell can be dynamically switched between a multiport mode and a common mode based on the dynamic reconfigurable technology through special physical layout and design, when a large amount of parallel operations occur, the expandable multiport blocky memory cell can be switched into the multiport mode, and two blocky SRAMs work in parallel, so that the requirement of the parallel multithread operation can be met; when no special requirement exists, the SRAM can work in a common working mode, and the two block-shaped SRAMs work in series to be configured into a common SRAM to be multiplexed to a basic logic unit; the switching of two working modes can be realized through the two block-shaped SRAMs, the reuse rate is high, the balance of performance and resources can be achieved, the method is suitable for various use scenes, the flexibility is high, the universality is good, and the read-write port selectivity is high.

Description

Scalable multi-port bulk memory cell based on dynamic reconfigurable technology

Technical Field

The invention relates to the field of programmable logic devices, in particular to an extensible multi-port block-shaped memory unit based on a dynamic reconfigurable technology.

Background

Programmable logic devices have the advantages of short development cycle, low cost, low risk, high integration level, high flexibility, and convenience for electronic system maintenance and upgrade, and are popular with users of terminal products, become the mainstream of integrated circuit chips, and are widely applied in various fields such as communication, control, video, information processing, electronics, internet, automobile, aerospace, and the like.

The programmable logic device mainly comprises a control system, a programmable logic unit, a digital signal processing DSP, a storage unit block SRAM, a plurality of high-speed interfaces, a clock module, an IP core and the like. The FPGA is a flexible and universal programmable logic device, along with the development of the FPGA, units such as a CPU (central processing unit), an AI (analog input) unit and the like are also integrated into the FPGA, the requirement on the operation performance of a system is more and more clear, and a large amount of parallel operation appears in the logic of the FPGA, so that the requirement on a multi-port block SRAM (static random access memory) is increased. The same address width area of the multi-port block SRAM is larger than that of a common single-port or double-port block SRAM, the multi-port block SRAM special for solidification and integration can enable the FPGA to be consumed by the multi-port block SRAM to have a large area, and the characteristics of low reuse rate and low power consumption are contrary to the flexibility of a programmable logic device, so that the method has the advantage that the performance and the area are considered to be a huge challenge for the programmable logic device.

Disclosure of Invention

The invention provides an expandable multi-port block-shaped memory unit based on a dynamic reconfigurable technology, aiming at the problems and the technical requirements, and the expandable multi-port block-shaped memory unit comprises a dynamic reconfiguration interface, a first block-shaped SRAM, a second block-shaped SRAM, a read control module and a write control module, wherein the two SRAMs are completely the same and have ports of 1R1W, the input end of the dynamic reconfiguration interface acquires configuration parameters, the output end of the dynamic reconfiguration interface is connected with the read control module, the write control module, the first block-shaped SRAM and the second block-shaped SRAM, and the dynamic reconfiguration interface configures configuration bits of the read control module, the write control module, the first block-shaped SRAM and the second block-shaped SRAM according to the acquired configuration parameters, so that the expandable multi-port block-shaped memory unit is dynamically switched between a multi-port working mode and a common working mode;

when the expandable multi-port block-shaped memory unit is in a multi-port working mode, the first block-shaped SRAM and the second block-shaped SRAM work in parallel under the control of an internal address control module, the first block-shaped SRAM and the second block-shaped SRAM occupy the same address, and the effective address width of the expandable multi-port block-shaped memory unit is the effective address width of the first block-shaped SRAM; the write control module acquires write data through the two write data ports and writes the write data into one of the block SRMA, the read control module acquires read data from one of the block SRAMs and outputs the read data through one read data port, or the write control module acquires write data through one write data port and writes the write data into one of the block SRMA, the read control module acquires read data from one of the block SRAMs and outputs the read data through the two read data ports, or the write control module acquires write data through the two write data ports and writes the write data into one of the block SRMA, and the read control module acquires read data from one of the block SRAMs and outputs the read data through the two read data ports;

when the expandable multi-port block-shaped memory unit is in a common working mode, the first block-shaped SRAM and the second block-shaped SRAM work in series under the control of an internal address control module, the first block-shaped SRAM occupies a low-order address, the second block-shaped SRAM occupies a high-order address, and the effective address width of the expandable multi-port block-shaped memory unit is the sum of the effective address width of the first block-shaped SRAM and the effective address width of the second block-shaped SRAM; the read control module and the write control module are both in a bypass state, write data is written in through a write port of the block SRAM, and data of the block SRAM is output through a read port.

The further technical scheme is that the address control modules in the two block-shaped SRAMs comprise address indication mark circuits;

when the expandable multi-port block-shaped memory unit is in a multi-port working mode, the address indication mark circuit indicates that the state of the indication mark bit of each address is a new state or an old state, and the states of the indication mark bits of the same address in the two block-shaped SRAMs are always opposite; after the write control module writes write data, the address indication mark circuit updates the state of the indication mark bits in the two block-shaped SRAMs; the read control module acquires read data according to the states of the indication flag bits in the two block-shaped SRAMs;

when the expandable multi-port block-shaped memory unit is in a common working mode, the address indication mark circuits inside the two block-shaped SRAMs are in a bypass state.

The write control module comprises a first input MUX _ REG, a second input MUX _ REG and an input selection scheduler, wherein the two input MUX _ REGs are respectively connected with two write data ports, the two input MUX _ REGs respectively comprise a write register inside, and the two input MUX _ REGs control the writing of the obtained write data according to the selection of the input selection scheduler;

the read control module comprises a first output MUX _ REG, a second output MUX _ REG and an output selection scheduler, the two output MUX _ REGs are respectively connected with the two read data ports, the two output MUX _ REGs respectively comprise a read register inside, and the two output MUX _ REGs are used for controlling and acquiring read data according to the selection of the output selection scheduler.

The method comprises the following steps that two input MUX _ REGs inquire a block SRAM in an idle state through an input selection scheduler and write acquired write data, an address indication mark circuit sets the state of an indication mark position of a corresponding address of the block SRAM, where the data are written, to be a new state, and sets the state of an indication mark position of the same address of the other block SRAM to be an old state;

and the two output MUX _ REGs inquire the block SRAM with the state of the address flag bit of the corresponding address as a new state through the output selection scheduler and acquire read data to output.

The further technical scheme is that when two input MUX _ REGs write the same address at the same time, the MUX _ REGs are normalized into one-time write operation; when the two output MUX _ REGs read the same address at the same time, the two output MUX _ REG outputs are read from the block SRAM with the state of the address flag bit being the new state and registered respectively.

The further technical scheme is that each input MUX _ REG uses a write register to register the obtained write data for one beat and then selects and controls to write the data into one block SRAM; and each output MUX _ REG registers the acquired read data by using the read register for one beat and then outputs the read data.

The further technical scheme is that when two output MUX _ REGs simultaneously obtain read data from the same block SRAM, two read operations are cached, the first output MUX _ REG read operation registers data in the first period and then outputs the data after one beat, and the second output MUX _ REG read operation directly outputs the data in the second period.

The further technical scheme is that when the condition of reading and writing in the same address and period occurs, the expandable multi-port block-shaped memory unit supports a write penetration mode, the input MUX _ REG directly transmits the acquired write data to the output MUX _ REG for output, or the input MUX _ REG registers the acquired write data by using a write register and then transmits the write data to the output MUX _ REG for output.

The method has the further technical scheme that when the expandable multi-port block-shaped memory unit is switched from a common working mode to a multi-port working mode, the expandable multi-port block-shaped memory unit reserves data in one of the block-shaped SRAMs, the indicating flag bits of all addresses in the block-shaped SRAMs for reserving the data are set to be in a new state, and the indicating flag bits of all addresses in the other block-shaped SRAM are set to be in an old state.

The beneficial technical effects of the invention are as follows:

the application discloses an expandable multi-port block-shaped storage unit based on a dynamic reconfigurable technology, the working mode of the block-shaped storage unit can be dynamically switched between a multi-port mode and a common mode through special physical layout and design, when a large amount of parallel operations occur, the block-shaped storage unit can be switched into the multi-port mode, two block-shaped SRAMs work in parallel, the requirement of multi-thread parallel operations can be met through the management of a parallel linked list and a lookup table, and the system performance of an FPGA in network and AI application is improved; when no special requirement exists, the SRAM can work in a common working mode, and the two block-type SRAMs work in series to be configured into common SRAMs which are multiplexed to a basic logic unit. The switching of two working modes can be realized through the two block-shaped SRAMs, the reuse rate is high, the balance of performance and resources can be achieved, the system is suitable for various use scenes, the flexibility is high, the universality is good, the read-write port selectivity is high, and the system is flexible and convenient to adapt to the FPGA of each scale.

Drawings

Fig. 1 is a schematic diagram of a logic structure of an expandable multi-port block memory cell according to the present application.

Fig. 2 is a schematic port expansion diagram of an expandable multi-port block memory cell of the present application.

FIG. 3 is a schematic diagram of effective address width of the block memory cell of the present application in two operating modes.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

Please refer to a schematic diagram of a logic structure of the scalable multi-port bulk storage unit shown in fig. 1, the scalable multi-port bulk storage unit includes a dynamic reconfiguration interface DRP, a first bulk SRAM, a second bulk SRAM, a read control module, and a write control module, the two bulk SRAMs are completely the same, and the ports of the two bulk SRAMs are both 1R 1W. The input end of the dynamic reconfiguration interface DRP acquires configuration parameters, and the output end of the dynamic reconfiguration interface DRP is connected with the read control module, the write control module, the first block SRAM and the second block SRAM, and the dynamic reconfiguration interface configures configuration bits of the read control module, the write control module, the first block SRAM and the second block SRAM according to the acquired configuration parameters, so that the expandable multi-port block memory unit is dynamically switched between a multi-port working mode and a common working mode:

when the expandable multi-port block-shaped memory unit is in a multi-port working mode, namely, is above a true dual port, the first block-shaped SRAM and the second block-shaped SRAM work in parallel under the control of an internal address control module, the first block-shaped SRAM and the second block-shaped SRAM occupy the same address, and the effective address width of the expandable multi-port block-shaped memory unit is the effective address width of the first block-shaped SRAM.

With reference to the PFGA internal block SRAM expansion process shown in fig. 2, the basic block SRAM supports at most true dual ports: 1R1W, 2W, 2R, whereas in the multi-port mode of the present application, the scalable multi-port block memory cell can be scaled to three ports: 2R1W or 1R2W, or the highest configurable expansion to four port 2R 2W. As in FIG. 3, attr _2R1W indicates that the multi-port bulk memory cell is expanded into a three-port 1R2W, when: the write control module acquires write data through two write data ports and writes the write data into one of the block SRMA, and the read control module acquires read data from one of the block SRMA and outputs the read data through one read data port. attr _1R2W denotes expanding the multi-port bulk memory cell to a three-port 2R1W, at which time: the write control module acquires write data through one write data port and writes the write data into one of the block SRMA, and the read control module acquires read data from one of the block SRMA and outputs the read data through two read data ports. attr _2R2W denotes expanding the multi-port bulk memory cell to a four-port 2R2W, at which time: the write control module acquires write data through the two write data ports and writes the write data into one of the block SRMA, and the read control module acquires read data from one of the block SRMA and outputs the read data through the two read data ports.

The write control module includes a first input MUX _ REG, a second input MUX _ REG, and an input select scheduler RR1, where the two input MUX _ REG are connected to two write data ports, respectively, e.g., the first input MUX _ REG is connected to write _ a _ addr and write _ a _ data of write data port write _ a, and the second input MUX _ REG is connected to write _ b _ addr and write _ b _ data of write data port write _ b in FIG. 1. The two input MUX _ REGs respectively include write registers therein, and the two input MUX _ REGs selectively control writing of the acquired write data according to the input selection scheduler RR 1. The read control module includes a first output MUX _ REG, a second output MUX _ REG and an output selection scheduler RR2, the two output MUX _ REGs are respectively connected to two read data ports, for example, in fig. 1, the first output MUX _ REG is connected to read _ a _ addr and read _ a _ data of read data port read _ a, and the second output MUX _ REG is connected to read _ b _ addr and read _ b _ data of read data port read _ b. The two output MUX _ REGs respectively include read registers therein, and the two output MUX _ REGs selectively control the acquisition of read data according to the output selection scheduler RR 2.

When the expandable multi-port block-shaped memory unit is in a multi-port working mode, the write ports of the first block-shaped SRAM and the second block-shaped SRAM are selectively controlled through the write control module, namely through two input MUX _ REG selection controls, and the read ports of the two block-shaped SRAMs are selectively controlled through the read control module, namely through two output MUX _ REG selection controls. IN order to meet the requirement of high performance, read-write data is registered for one beat at a data port, namely, the input MUX _ REG registers for one beat of the acquired write data by using a write register and then is selectively controlled to be written into one of the block-shaped SRAMs, and the output MUX _ REG registers for one beat of the acquired read data by using a read register and then is output, so that the delay of the ports IN2REG and REG2OUT is met.

In a multi-port mode of operation, the address control modules within the two block SRAMs include address indicator flag circuitry. When the scalable multi-port block memory unit is in the multi-port working mode, the address indication flag circuit indicates that the state of the indication flag bit of each address is a new state (N) or an old state (O), and the states of the indication flag bits for the same address in the two block SRAMs are always opposite, as shown in fig. 1.

Since the ports of the first block SRAM and the second block SRAM in the present application are both 1R1W, data can be read and written simultaneously according to multiple ports, and a single block SRAM cannot complete read and write operations, the present application adopts the structure of the parallel dual block SRAM, and by comparing the input selection scheduler RR1, the two input MUX _ REGs query the block SRAM in an idle state through the input selection scheduler RR1 and write the obtained write data. After the write control module writes write data, the address indication mark circuit updates the states of the indication mark bits in the two block-shaped SRAMs, the state of the indication mark bit of the corresponding address of the block-shaped SRAM in which the data is written is set as a new state N, and the state of the indication mark bit of the same address of the other block-shaped SRAM is set as an old state O. When the read control module reads data, the two output MUX _ REGs query the state of the address flag bit of the corresponding address through the output selection scheduler RR2, and read the data in the block SRAM of which the state of the indication flag bit is set to the new state N.

When two input MUX _ REGs write the same address at the same time, unify into write operation once; when the two output MUX _ REGs read the same address at the same time, the two output MUX _ REG outputs are read from the block SRAM with the state of the address flag bit being the new state and registered respectively.

The two output MUX _ REGs can also internally control whether read data adopts register output, and the design can be used for solving read conflict, namely the situation that two read data ports read the same block SRAM simultaneously. The method adopts a read enable-to-read data valid 2cycle structure, when two read data ports (namely two output MUX _ REGs) read one block SRAM at the same time, two read operations are cached, the first output MUX _ REG read operation is output after the first cycle data is registered for one beat, and the second output MUX _ REG read operation is directly output after the second cycle data is registered for one beat.

When the reading and writing are performed in the same address and period, the expandable multi-port block-shaped memory unit supports a write penetration mode, and the write penetration mode supports two modes: the input MUX _ REG directly transmits the acquired write data to output the MUX _ REG for output, namely the write data is directly penetrated through a data port and is not written into a write register; or, the input MUX _ REG registers the obtained write data by using the write register for one beat and then transmits the write data to the output MUX _ REG for output.

When the expandable multi-port block-shaped memory unit is in a common working mode, a first block-shaped SRAM and a second block-shaped SRAM work in series under the control of an internal address control module, the first block-shaped SRAM occupies a low-order address, the second block-shaped SRAM occupies a high-order address, and the effective address width of the expandable multi-port block-shaped memory unit is the sum of the effective address width of the first block-shaped SRAM and the effective address width of the second block-shaped SRAM. As shown in FIG. 3, attr _1R1W indicates that the multi-port block memory cell is in a normal mode of operation. At this time, the two block SRAMs are expanded into a whole block of block SRAMs through addresses, the read control module and the write control module are both in a bypass state, that is, the two input MUX _ REGs, the two output MUX _ REGs, the input selection scheduler RR1 and the output selection scheduler RR2 are all in a bypass state, meanwhile, the address indication flag circuits inside the two block SRAMs are also in a bypass state, write data are written through write ports of the block SRAMs, and data of the block SRAMs are output through read ports.

During dynamic switching, when the expandable multi-port block memory unit is switched from a common working mode to a multi-port working mode, the expandable multi-port block memory unit reserves data in one of the block SRAMs, sets the indicating flag bits of all addresses in the block SRAMs for reserving the data to be in a new state, and sets the indicating flag bits of all addresses in the other block SRAM to be in an old state.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. The expandable multi-port block-shaped storage unit based on the dynamic reconfigurable technology is characterized by comprising a dynamic reconfiguration interface, a first block-shaped SRAM, a second block-shaped SRAM, a read control module and a write control module, wherein the two SRAMs are completely the same and have ports of 1R1W, the input end of the dynamic reconfiguration interface acquires configuration parameters, and the output end of the dynamic reconfiguration interface is connected with the read control module, the write control module, the first block-shaped SRAM and the second block-shaped SRAM;

when the expandable multi-port block-shaped memory unit is in a multi-port working mode, the first block-shaped SRAM and the second block-shaped SRAM work in parallel under the control of an internal address control module, the first block-shaped SRAM and the second block-shaped SRAM occupy the same address, and the effective address width of the expandable multi-port block-shaped memory unit is the effective address width of the first block-shaped SRAM; the write control module acquires write data through two write data ports and writes the write data into one of the block SRMA, the read control module acquires read data from one of the block SRAMs and outputs the read data through one read data port, or the write control module acquires write data through one write data port and writes the write data into one of the block SRMA, the read control module acquires read data from one of the block SRAMs and outputs the read data through two read data ports, or the write control module acquires write data through two write data ports and writes the write data into one of the block SRMA, and the read control module acquires read data from one of the block SRAMs and outputs the read data through two read data ports;

when the expandable multi-port block-shaped storage unit is in a common working mode, the first block-shaped SRAM and the second block-shaped SRAM work in series under the control of an internal address control module, the first block-shaped SRAM occupies a low-order address, the second block-shaped SRAM occupies a high-order address, and the effective address width of the expandable multi-port block-shaped storage unit is the sum of the effective address width of the first block-shaped SRAM and the effective address width of the second block-shaped SRAM; the read control module and the write control module are both in a bypass state, write data are written in through a write port of the block SRAM, and data of the block SRAM are output through a read port.

2. The scalable multi-port bulk memory cell of claim 1, wherein the address control modules inside the two bulk SRAMs comprise address indicator flag circuits;

when the expandable multi-port block-shaped memory unit is in a multi-port working mode, the address indication mark circuit indicates that the state of the indication mark bit of each address is a new state or an old state, and the states of the indication mark bits of the same address in the two block-shaped SRAMs are always opposite; after the write control module writes write data, the address indication mark circuit updates the state of the indication mark bits in the two block-shaped SRAMs; the reading control module acquires read data according to the states of the indication flag bits in the two block-shaped SRAMs;

3. The scalable multi-port bulk memory cell of claim 2,

the write control module comprises a first input MUX _ REG, a second input MUX _ REG and an input selection scheduler, the two input MUX _ REGs are respectively connected with two write data ports, write registers are respectively arranged in the two input MUX _ REGs, and the two input MUX _ REGs control the writing of the obtained write data according to the selection of the input selection scheduler;

the read control module comprises a first output MUX _ REG, a second output MUX _ REG and an output selection scheduler, the two output MUX _ REGs are respectively connected with two read data ports, the two output MUX _ REGs respectively comprise a read register inside, and the two output MUX _ REGs are used for obtaining read data according to the selection control of the output selection scheduler.

4. The scalable multiport block memory unit according to claim 3, wherein two input MUX _ REGs query a block SRAM in an idle state through the input selection scheduler and write the obtained write data, and the address indication flag circuit sets a state of an indication flag bit of a corresponding address of the block SRAM to which data is written to a new state and a state of an indication flag bit of the same address of another block SRAM to an old state;

and the two output MUX _ REGs inquire the block SRAM with the state of the address flag bit of the corresponding address as a new state through the output selection scheduler and acquire read data output.

5. The scalable multi-port block memory cell of claim 4, wherein when two input MUX _ REGs write the same address at the same time, they are normalized to a write-once operation; when the two output MUX _ REGs read the same address at the same time, the two output MUX _ REG outputs are read from the block SRAM with the state of the address flag bit being the new state and registered respectively.

6. The scalable multi-port block memory unit of claim 3 or 4, wherein each of the input MUX _ REGs registers one beat of acquired write data with the write register and then selectively controls writing into one of the block SRAMs; and each output MUX _ REG utilizes the read register to register the obtained read data for one beat and then outputs the read data.

7. The scalable multi-port block memory cell of claim 6, wherein when two output MUX _ REGs simultaneously fetch read data from the same block SRAM, two read operations are buffered, a first output MUX _ REG read operation registers a beat of data to be output, and a second output MUX _ REG read operation directly outputs data in a second cycle.

8. The scalable multi-port block memory unit of claim 3, wherein when the same address and period of read and write occurs, the scalable multi-port block memory unit supports a write-through mode, the input MUX _ REG directly transmits the obtained write data to the output MUX _ REG for output, or the input MUX _ REG registers the obtained write data for one beat by using the write register and then transmits the write data to the output MUX _ REG for output.

9. The scalable multi-port block memory unit of claim 2, wherein when the scalable multi-port block memory unit switches from a normal operation mode to a multi-port operation mode, the scalable multi-port block memory unit retains data in one of the block SRAMs, sets the indicator flag bits of all addresses in the data-retained block SRAMs to a new state, and sets the indicator flag bits of all addresses in the other block SRAMs to an old state.