CN111599323A

CN111599323A - Shift register, driving method and grid driving circuit

Info

Publication number: CN111599323A
Application number: CN202010101870.3A
Authority: CN
Inventors: 高翔宇; 刘子正; 龚文俊
Original assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Wuhan BOE Optoelectronics Technology Co Ltd
Priority date: 2020-02-19
Filing date: 2020-02-19
Publication date: 2020-08-28
Anticipated expiration: 2040-02-19
Also published as: CN111599323B

Abstract

The invention provides a shift register, a driving method and a grid driving circuit, belongs to the technical field of display, and can solve the problems of waveform distortion and long falling time of a falling edge of an existing output signal. A shift register of the present invention includes: the system comprises an input module, an output module and a pull-up node lifting module; the input module is configured to respond to an input signal and pre-charge a pull-up node through the input signal; the pull-up node is a connecting node between the input module and the output module; the output module is configured to respond to the electric potential of the pull-up node and output a first clock signal through the signal output end; the pull-up node boosting module is configured to respond to a potential of the signal output terminal and output the second clock signal through the pull-up output terminal.

Description

Shift register, driving method and grid driving circuit

Technical Field

The invention belongs to the technical field of display, and particularly relates to a shift register, a driving method and a grid driving circuit.

Background

With the continuous development of the display industry, liquid crystal display products have attracted more attention due to their advantages of low cost, narrow frame, light weight, and the like, and Gate Driver on Array (GOA) technology has come to work under this background. The GOA technology is that a grid driving circuit and a thin film transistor array are manufactured on an array substrate together, and pixel units are started line by line through a plurality of cascaded shift registers, so that a display product displays colorful pictures.

The inventor finds that at least the following problems exist in the prior art: the existing shift register has insufficient performance when meeting the requirements of larger size, higher resolution and higher refresh rate, and particularly, the falling edge waveform of the output signal is distorted, and the falling Time (Fall Time, Tf) is longer, so that the pixels of the current row are easy to output by mistake.

Disclosure of Invention

The present invention is directed to at least one of the technical problems in the prior art, and provides a shift register, a driving method thereof, and a gate driving circuit.

The technical scheme adopted for solving the technical problem of the invention is a shift register, which comprises: the system comprises an input module, an output module and a pull-up node lifting module;

the input module is configured to respond to an input signal and pre-charge a pull-up node through the input signal; the pull-up node is a connection node between the input module and the output module;

the output module is configured to respond to the electric potential of the pull-up node and output the first clock signal through a signal output end;

the pull-up node boosting module is configured to respond to a potential of the signal output terminal and output a second clock signal through a pull-up output terminal.

Optionally, the input module comprises: a first transistor; the control electrode and the first electrode of the first transistor are connected with the signal input end, and the second electrode is connected with the pull-up node;

the output module includes: a third transistor; a control electrode of the third transistor is connected with a pull-up node, a first electrode is connected with a first clock signal end, and a second electrode is connected with a signal output end;

the upper node elevation module includes: a seventh transistor; and a control electrode of the seventh transistor is connected with the signal output end, a first electrode of the seventh transistor is connected with the second clock signal end, and a second electrode of the seventh transistor is connected with the pull-up output end.

Optionally, the shift register further includes: a pull-up control module;

the pull-up control module is configured to precharge the pull-up node by the input signal or a second clock signal when the input signal is input by the input unit or the second clock signal is input by the pull-up node boosting unit.

Optionally, the pull-up control module comprises: a capacitor;

one end of the capacitor is connected with the upper pull node, and the other end of the capacitor is connected with the signal output end.

Optionally, the shift register further includes: the device comprises a pull-down control module, a pull-down module, a first noise reduction module and a second noise reduction module;

the pull-down control module is configured to respond to a first power supply voltage and control the potential of a pull-down node through the first power supply voltage; the pull-down node is a connection node between the pull-down control module and the pull-down module;

the pull-down module is configured to pull down the pull-down node in response to a potential of the pull-up node;

the first noise reduction module is configured to reduce noise of the pull-up node by a second power supply voltage in response to a potential of the pull-down node;

the second noise reduction module is configured to reduce noise of the signal output terminal by a second power supply voltage in response to a potential of the pull-down node.

Optionally, the pull-down control module comprises a ninth transistor and a fifth transistor; a control electrode of the ninth transistor is connected with a first power supply voltage end, a first electrode of the ninth transistor is connected with a first power supply voltage end, and a second stage of the ninth transistor is connected with a control electrode of the fifth transistor; a control electrode of the fifth transistor is connected with a second electrode of the ninth transistor, a first electrode of the fifth transistor is connected with a first power voltage end, and a second electrode of the fifth transistor is connected with a pull-down node;

the pull-down module comprises a sixth transistor and an eighth transistor; a control electrode of the sixth transistor is connected with the pull-up node, a first electrode of the sixth transistor is connected with the pull-down node, and a second electrode of the sixth transistor is connected with a second power supply voltage end; a control electrode of the eighth transistor is connected with the upper pull node, a first electrode of the eighth transistor is connected with a second electrode of the ninth transistor, and the second electrode of the eighth transistor is connected with a second power supply voltage end;

the first noise reduction module comprises a tenth transistor; a control electrode of the tenth transistor is connected with the pull-down node, a first electrode of the tenth transistor is connected with the pull-up node, and a second electrode of the tenth transistor is connected with the second power supply voltage end;

the second noise reduction module comprises an eleventh transistor; and a control electrode of the eleventh transistor is connected with the pull-down node, a first electrode of the eleventh transistor is connected with the signal output end, and a second electrode of the eleventh transistor is connected with the second power supply voltage end.

Optionally, the shift register further includes: the device comprises a first reset module and a second reset module;

the first reset module is configured to reset the pull-up node by a second power supply voltage in response to a first reset signal;

the second reset module is configured to reset the signal output terminal by a second power supply voltage in response to a second reset signal.

Optionally, the first reset module comprises a second transistor; the control electrode of the second transistor is connected with a first reset signal end, the first electrode is connected with a pull-up node, and the second electrode is connected with a second power supply voltage end;

the second reset module comprises a fourth transistor; and a control electrode of the fourth transistor is connected with a second reset signal end, a first electrode of the fourth transistor is connected with a signal output end, and a second electrode of the fourth transistor is connected with a second power supply voltage end.

The technical scheme adopted for solving the technical problem of the invention is a gate drive circuit which comprises a plurality of cascaded shift registers.

The technical scheme adopted for solving the technical problem of the invention is a driving method of a shift register, which comprises the following steps:

in the first stage, an input unit responds to an input signal and pre-charges a pull-up node through the input signal; the pull-up node is a connection node between the input module and the output module;

the second stage, responding to the electric potential of the pull-up node and outputting a first clock signal through a signal output end; meanwhile, the pull-up node increasing unit responds to the first clock signal and outputs a second clock signal through a pull-up output end;

and in a third stage, the output unit responds to the potential of the pull-up node and maintains a fully-opened state.

Drawings

Fig. 1 is a schematic structural diagram of a shift register module according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a shift register in the prior art;

FIG. 3 is a timing diagram of a shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 5 is a flowchart illustrating a driving method of a shift register according to an embodiment of the present invention.

Wherein the reference numerals are: 101-Input module, 102-Output module, 103-pull-up node raising module, 104-pull-up control module, 105-pull-down control module, 106-pull-down module, 107-first noise reduction module, 108-second noise reduction module, 109-first Reset module, 110-second Reset module, Input-signal Input terminal, Output-signal Output terminal, PullPU-pull-up Output terminal, CLK-first clock signal terminal, CLK ii-second clock signal terminal, VDD-first power voltage terminal, VSS-second power voltage terminal, Reset PU-first Reset signal terminal, Reset Output-second Reset signal terminal, PU-pull-up node, PD-pull-down node, M1-first transistor, M2-second transistor, M3-third transistor, m4-fourth transistor, M5-fifth transistor, M6-sixth transistor, M7-seventh transistor, M8-eighth transistor, M9-ninth transistor, M10-tenth transistor and M11-eleventh transistor.

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The display panel in the prior art generally has a display area and a peripheral area surrounding the display area; a plurality of pixel units arranged in an array are arranged in the display area, and a pixel circuit is arranged in each pixel unit; the pixel units in the same row are connected with the same grid line, and the pixel units in the same column are connected with the same data line. The gate driving circuit is arranged in the peripheral region and comprises a plurality of cascaded shift registers, the shift registers are arranged in one-to-one correspondence with the gate lines, namely each shift register is connected with one gate line. When each frame of picture is displayed, the grid scanning signals are output to the grid lines corresponding to the grid lines through the step-by-step shift register so as to complete the line-by-line scanning of the pixel circuits, and the data voltage signals are written into the pixel circuits of the line by the data lines while each line of grid lines is scanned so as to light the pixel units of the line. And finally, the display of the whole display panel is realized.

It should be noted that the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used are symmetrical, the source and the drain are indistinguishable. In the embodiment of the present invention, to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N-type and P-type according to the characteristics of the transistors, and in the following embodiments, the N-type transistors are used for explanation, when the N-type transistors are used, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the gate electrode inputs a high level, the source electrode and the drain electrode are conducted, and the P-type is opposite. It is contemplated that implementation with P-type transistors will be readily apparent to those skilled in the art without inventive effort and, thus, are within the scope of the embodiments of the present invention.

In the embodiment of the present invention, since the transistor is an N-type transistor, the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal refers to a low level signal. In the embodiment of the present invention, the first power supply voltage written at the first power supply voltage terminal is higher than the second power supply voltage written at the second power supply voltage terminal.

Example one

Fig. 1 is a schematic structural diagram of a shift register module according to an embodiment of the present invention, as shown in fig. 1, the shift register module includes: an input module 101, an output module 102 and a pull-up node boosting module 103; the input module 101 is configured to respond to an input signal and pre-charge a pull-up node PU by the input signal; the pull-up node PU is a connection node between the input module 101 and the output module 102; the Output module 102 is configured to respond to the potential of the pull-up node PU and Output a first clock signal through a signal Output terminal Output; the Pull-up node boosting module 103 is configured to respond to the potential of the signal Output terminal Output and Output the second clock signal through the Pull-up Output terminal Pull PU.

In the shift register provided in the embodiment of the present invention, when the Input signal received by the Input module 101 is the first level signal VGH (the first level signal VGH is a high level signal), the Input signal is precharged to the pull-up node PU. When the pull-up node PU is at the first level signal VGH, the Output module 102 turns on the first clock signal terminal CLK connected to the Output module 102 and the signal Output terminal Output, and the first level signal VGH of the first clock signal terminal CLK starts to be Output. At this time, the pull-up node increasing module 103 receives the first level signal VGH from the signal Output terminal Output, transmits the second level signal HVGH (the second level signal HVGH is a high level signal and is higher than the first level signal VGH) of the second clock signal terminal CLK ii to the pull-up node PU of the cascaded shift register, and pre-charges the pull-up node PU of the cascaded shift register. When the Output module 102 receives a falling edge signal of the first clock signal terminal CLK (the signal of the first clock signal terminal CLK is reduced from the first level signal VGH to the third level signal VGL, and the third level signal VGL is a low level signal), the pull-up node PU receives the second level signal HVGH, and can maintain a high level state, so that the Output module 102 is kept in a fully opened state, and it is ensured that the falling edge signal can be rapidly transmitted to the signal Output terminal Output, and therefore, the falling time of the Output signal can be reduced, the distortion of the falling edge signal waveform can be greatly reduced, the charging efficiency is improved, the signal misoutput probability of the signal Output terminal Output can be reduced, and the reliability is improved.

Specifically, as shown in fig. 1, the input unit 101 includes: a first transistor M1; the control electrode and the first electrode of the first transistor M1 are connected to the signal Input end, and the second electrode is connected to the pull-up node PU; the output unit 102 includes: a third transistor M3; a control electrode of the third transistor M3 is connected to the pull-up node PU, a first electrode is connected to the first clock signal terminal CLK, and a second electrode is connected to the signal Output terminal Output; the upper node increasing unit includes: a seventh transistor M7; a control electrode of the seventh transistor M7 is connected to the signal Output terminal Output, a first electrode is connected to the second clock signal terminal CLK ii, and a second electrode is connected to the Pull-up Output terminal Pull PU.

It should be noted that, when the signal Input terminal Input receives the first level signal VGH, the first transistor M1 is turned on, and the first level signal VGH can precharge the pull-up node PU. After the pull-up node PU is at a high potential after being precharged, the third transistor M3 is turned on, the signal Output terminal Output outputs the first clock signal as the first level signal VGH, so that the control electrode of the seventh transistor M7 is at the high potential, the seventh transistor M7 is turned on, the second level signal HVGH of the second clock signal terminal CLK ii is Output to the pull-up node PU rising signal terminal, and the second level signal HVGH is Output to the pull-up node PU of the cascade shift register by the pull-up node PU rising signal terminal. It can be seen that, in the shift register provided in the embodiment of the present invention, the fast discharge can be realized by controlling the turn-on degree of the third transistor M3, so that the falling time of the output signal can be reduced, and the distortion of the waveform of the falling edge signal can be greatly reduced. In addition, the pull-up node boosting module 103 may be composed of a seventh transistor M7, and the circuit connection structure is simple, so that the manufacturing cost may be saved.

In some embodiments, as shown in fig. 1, the shift register further comprises: a pull-up control module 104; the pull-up control module 104 is configured to precharge the pull-up node PU by the input signal or the second clock signal when the input signal is input by the input unit 101 or the second clock signal is input by the pull-up node boosting unit 103.

Specifically, as shown in fig. 1, the pull-up control module 104 includes: a capacitor; one end of the capacitor is connected with the upper pull node PU, and the other end of the capacitor is connected with the signal Output end Output.

It should be noted that, when the signal Output end is at the third level potential and the signal Input end is the first level signal VGH, the potential of the pull-up node PU may be pulled high. When the signal Output terminal Output outputs the first level signal VGH, the potential of the pull-up node PU is pulled up again due to the capacitive coupling effect. When the first level signal VGH Output by the signal Output terminal Output becomes the third level signal VGL, the potential of the pull-up node PU is pulled down due to the capacitive coupling effect.

In some embodiments, as shown in fig. 1, the shift register further comprises: a pull-down control module 105, a pull-down module 106, a first noise reduction module 107, and a second noise reduction module 108; the pull-down control module 105 is configured to respond to the first power supply voltage and control the potential of the pull-down node PD by the first power supply voltage; the pull-down node PD is a connection node between the pull-down control module 105 and the pull-down module 106; the pull-down module 106 is configured to pull down the pull-down node PD in response to a potential of the pull-up node PU; the first noise reduction module 107 is configured to reduce noise of the pull-up node PU by the second power supply voltage in response to the potential of the pull-down node PD; the second noise reduction module 108 is configured to reduce noise of the signal Output terminal Output by the second power supply voltage in response to the potential of the pull-down node PD.

Specifically, as shown in fig. 1, the pull-down control module 105 includes a ninth transistor M9 and a fifth transistor M5; a control electrode of the ninth transistor M9 is connected to the first power voltage terminal VDD, a first electrode is connected to the first power voltage terminal VDD, and a second electrode is connected to a control electrode of the fifth transistor M5; a control electrode of the fifth transistor M5 is connected to a second electrode of the ninth transistor M9, a first electrode is connected to the first power voltage terminal VDD, and a second electrode is connected to the pull-down node PD; the pull-down module 106 includes a sixth transistor M6 and an eighth transistor M8; a control electrode of the sixth transistor M6 is connected to the pull-up node PU, a first electrode is connected to the pull-down node PD, and a second electrode is connected to the second power supply voltage terminal VSS; a control electrode of the eighth transistor M8 is connected to the pull-up node PU, a first electrode is connected to a second electrode of the ninth transistor M9, and the second electrode is connected to the second power voltage terminal VSS; the first noise reduction module 107 includes a tenth transistor M10; a control electrode of the tenth transistor M10 is connected to the pull-down node PD, a first electrode is connected to the pull-up node PU, and a second electrode is connected to the second power supply voltage terminal VSS; the second noise reduction module 108 includes an eleventh transistor M11; a control electrode of the eleventh transistor M11 is connected to the pull-down node PD, a first electrode thereof is connected to the signal Output terminal Output, and a second electrode thereof is connected to the second power supply voltage terminal VSS.

It should be noted that, when the first level signal VGH is inputted to the first power voltage terminal VDD, the ninth transistor M9 is turned on, and when the pull-up node PU is the first level signal VGH or the second level signal HVGH, the eighth transistor M8 is turned on, and the first level signal VGH transmitted by the ninth transistor M9 is outputted to the second power voltage terminal VSS through the eighth transistor M8. When the pull-up node PU is the third level signal VGL, the eighth transistor M8 is not turned on, the fifth transistor M5 is turned on by the first level signal VGH transmitted by the ninth transistor M9, and the fifth transistor M5 outputs the first level signal VGH. When the pull-up node PU is at the first level potential or the second level potential, the pull-down node PD and the second power voltage terminal VSS are turned on, so that the pull-down node PD is maintained at the third level signal VGL. The turn-on capability of the sixth transistor M6 is much larger than that of the fifth transistor M5, which pulls the pull-down node PD down to the third level signal VGL. When the pull-down node PD is at the first level potential, the pull-up node PU and the second power supply voltage terminal VSS are turned on, so that the pull-up node PU is maintained at the third level potential. When the pull-down node PD is at the first level potential, the signal Output terminal Output and the second power supply voltage terminal VSS are turned on, so that the signal Output terminal Output is maintained at the third level potential.

In some embodiments, as shown in fig. 1, the shift register further comprises: a first reset module 109 and a second reset module 110; the first reset module 109 is configured to reset the pull-up node PU by the second power supply voltage in response to the first reset signal; the second reset module 110 is configured to reset the signal Output terminal Output by the second power supply voltage in response to a second reset signal.

Specifically, the first reset module 109 includes a second transistor M2; a control electrode of the second transistor M2 is connected to the first Reset signal terminal Reset PU, a first electrode is connected to the pull-up node PU, and a second electrode is connected to the second power voltage terminal VSS; the second reset module 110 includes a fourth transistor M4; a control electrode of the fourth transistor M4 is connected to the second Reset signal terminal Reset Output, a first electrode is connected to the signal Output terminal Output, and a second electrode is connected to the second power supply voltage terminal VSS.

It should be noted that, when the first reset signal is input to the cascaded shift registers, the pull-up node PU and the second power supply voltage terminal VSS are turned on, so that the pull-up node PU is pulled down to the third level potential. When the second reset signal is input to the cascaded shift register, the signal Output terminal Output and the second power supply voltage terminal VSS are conducted, so that the signal Output terminal Output is pulled down to a third level potential. In this way, the pull-up node PU and the signal Output terminal Output can be reset by the first reset signal and the second reset signal, respectively, and preparation can be made for next signal transmission.

The operation of a shift register according to an embodiment of the present invention will be more clearly understood by referring to the timing diagrams shown in fig. 2 and 3.

Fig. 2 and fig. 3 are timing diagrams of a shift register in the prior art and a shift register according to an embodiment of the present invention, respectively. As shown in fig. 2 and 3, T1 is a charging phase of the shift register, T2 is an output phase of the shift register, T3 is an output signal falling phase of the shift register, and T4 is a reset phase of the shift register.

As shown in fig. 2 and fig. 3, in the period T1, the signal Input terminal Input of the shift register receives the first level signal VGH, the first transistor M1 is turned on, and the first level signal VGH can pre-charge the pull-up node PU, and pull up the potential of the pull-up node PU for the first time. When the pull-up node PU is at the high level potential, the third transistor M3 is turned on, and at this time, the first clock signal terminal CLK inputs the third level signal VGL, and the potential of the signal Output terminal Output is unchanged. When the control electrodes of the sixth transistor M6 and the eighth transistor M8 are both at the first level potential, the sixth transistor M6 and the eighth transistor M8 are turned on, so that the pull-down node PD is pulled down from the first level potential to the third level potential. When the pull-down node PD drops to the third level potential, the tenth transistor M10 and the eleventh transistor M11 are turned off, and the first noise reduction module and the second noise reduction module stop operating.

As shown in fig. 2 and fig. 3, at the stage T2, the potential of the signal Input terminal Input changes to the low level potential, the pull-up node PU maintains the high level potential, the first clock signal jumps from the third level signal VGL to the first level signal VGH, and the first level signal VGH is output from the third transistor M3, at this time, the pull-up node PU is pulled up to the second level potential for the second time due to the capacitive coupling effect.

As shown in fig. 2, at the stage T3, the first clock signal jumps from the first level signal VGH to the third level signal VGL, and at this time, due to the capacitive coupling, the pull-up node PU is pulled down from the second level potential to the first level potential, that is, the control electrode potential of the third transistor M3 is pulled down from the second level potential to the first level potential, so that the turn-on degree of the third transistor M3 becomes small, the pull-down signal is input, and the fourth transistor M4 is turned on. At this time, the output signal is pulled down from the first level signal VGH to a third level signal VGL through the third transistor M3 and the fourth transistor M4, wherein the third transistor M3 is dominant (the third transistor M3 has a larger width), and the falling time Tf of the output signal is lengthened due to the reduction of the control electrode potential of the third transistor M3, so that the falling edge is distorted.

As shown in fig. 3, during the period T3, the first clock signal jumps from the first level signal VGH to the third level signal VGL, at this time, the Pull-up node PU tends to be pulled down due to the capacitive coupling, at this time, the second clock signal (the second level signal HVGH) of the Pull-up output terminal Pull PU of the cascaded shift register is transmitted to the Pull-up node PU of the cascaded shift register, so that the Pull-up node PU is maintained at the second level signal HVGH, that is, the control electrode potential of the third transistor M3 is maintained at the second level potential, and the opening degree of the third transistor M3 is greater. The second Reset signal terminal Reset Output Reset signal is input, and the fourth transistor M4 is turned on. At this time, the output signal is pulled down from the first level signal VGH to the third level signal VGL through the third transistor M3 and the fourth transistor M4, and the falling time Tf of the output signal is greatly shortened due to the full swing output of the third transistor M3, and the falling edge approaches to a rectangular wave.

As shown in fig. 2 and 3, in the period T4, the first Reset signal terminal Reset PU receives the Reset signal, the potential of the control electrode of the second transistor M2 is at the first level potential, the pull-up node PU is conducted with the second power supply voltage terminal VSS, and the signal of the pull-up node PU is pulled down to the third level signal VGL by the second level signal HVGH. When the pull-up node PU is at the third level potential, the sixth transistor M6 and the eighth transistor M8 are turned off, and the potential of the pull-down node PD starts to charge to the first level signal VGH under the turning-on action of the fifth transistor M5, so that the control electrode potentials of the tenth transistor M10 and the eleventh transistor M11 are pulled high and turned on, and the pull-up node PU and the signal Output terminal Output are denoised.

Example two

Fig. 4 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention, and as shown in fig. 4, the gate driving circuit includes a plurality of cascaded shift registers according to any one of the embodiments. For simplicity and clarity of illustration, fig. 4 is only a representative cascade-relationship circuit diagram, and not all circuits are drawn. In order to increase the charging rate of the pixel region, the GOA architecture design introduces a pre-charging method, i.e. if the actual charging time of each row of pixels is 1H, the gate of each row of pixels is turned on for a time longer than 1H (e.g. 3H or 4H), in other words, the duration of the first level potential in the clock signal is longer than 1H (e.g. 3H or 4H), so that a certain pre-charging time is left before the row of pixels is actually charged. The clock signal adopted in the embodiment of the invention is a pulse signal with alternating circulation of a 3H time high level and a 3H time low level, and the duty ratio is 50%. The cascade relationship of the shift registers in the embodiment of the present invention is specifically described below with reference to fig. 4.

The signal Output terminal Output of the nth stage shift register is connected to the input unit of the (N + 3) th stage shift register through a cascade connection relationship, so that the input unit receives the first level signal VGH and charges the pull-up node PU, in other words, the input signal of the nth stage shift register is provided by the signal Output terminal Output of the N-3 th stage shift register.

The signal Output end Output of the nth stage shift register is connected to the second reset unit of the nth-3 stage shift register through a cascade connection relationship, so that the second reset signal end receives the first level signal VGH and conducts the signal Output end Output and the second power supply voltage terminal VSS, and the Output signal is pulled down to the third level signal VGL. In other words, the second reset signal of the nth stage shift register is provided by the signal Output terminal Output of the N +3 th stage shift register.

The signal Output end Output of the nth stage shift register is connected to the first reset module of the nth-4 th stage shift register through a cascade connection relationship, so that the first reset module receives the first level signal VHGH and conducts the pull-up node PU and the second power supply voltage terminal VSS, and the pull-up node PU is pulled down to the third level signal VGL. In other words, the first reset signal of the nth stage shift register is provided by the signal Output terminal Output of the N +4 th stage shift register.

The Pull-up output terminal Pull PU of the Nth-stage shift register is connected to the Pull-up node PU of the Nth-3-stage shift register through a cascade connection relationship, so that the Pull-up node PU of the Nth-3-stage shift register can maintain higher potential when the first clock signal jumps (from a high level signal to a low level signal). In other words, the Pull-up node up signal of the nth stage shift register is provided by the Pull-up output Pull PU of the N +3 th stage shift register.

Alternatively, the second clock signal mentioned in the embodiment of the present invention may be the second level signal HVGH, which is specifically the maximum potential reached when the pull-up node PU is pulled up twice by the capacitive coupling in the second stage. In addition, the duty cycle may be 33.3%, in other words, the high level for 1H time and the low level for 2H time are alternately cycled. In addition, the high level value and the duty ratio of the second level signal can be adjusted according to actual needs, and are not limited to the specific situations provided by the embodiments of the present invention.

It should be noted that the nth stage shift register, the N +3 th stage shift register, the N-3 rd stage shift register, the N +4 th stage shift register, and the N-4 th stage shift register are opposite to each other, and are determined according to the forward scanning and the reverse scanning of the gate driving circuit. The grid driving circuit is used for providing a shift register unit of a scanning signal for a first grid line according to the scanning sequence of the grid lines when the grid lines are scanned in the forward direction, and the shift register unit is a first-stage shift register; and the shift register unit for providing scanning signals to the Nth grid line is an Nth-stage shift register.

EXAMPLE III

Fig. 5 is a schematic flow chart of a driving method of a shift register according to an embodiment of the present invention, and as shown in fig. 5, the driving method of the shift register includes the following steps:

s501, in the first stage, an input unit responds to an input signal and pre-charges a pull-up node through the input signal; and the pull-up node is a connecting node between the input module and the output module.

S502, in the second stage, responding to the electric potential of the pull-up node, and outputting a first clock signal through a signal output end; meanwhile, the pull-up node increasing unit outputs a second clock signal through the pull-up output terminal in response to the first clock signal.

S503, the third stage, the output unit maintains the fully-on state in response to the potential of the pull-up node.

It is understood that the implementation principle of steps S501-S503 is the same as that of the shift register provided in the above embodiment, and is not described herein again.

It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims

1. A shift register, comprising: the system comprises an input module, an output module and a pull-up node lifting module;

2. The shift register of claim 1, wherein the input module comprises: a first transistor; the control electrode and the first electrode of the first transistor are connected with the signal input end, and the second electrode is connected with the pull-up node;

3. The shift register of claim 2, further comprising: a pull-up control module;

4. The shift register of claim 3, wherein the pull-up control module comprises: a capacitor;

5. The shift register of claim 4, further comprising: the device comprises a pull-down control module, a pull-down module, a first noise reduction module and a second noise reduction module;

6. The shift register of claim 5, wherein the pull-down control module comprises a ninth transistor and a fifth transistor; a control electrode of the ninth transistor is connected with a first power supply voltage end, a first electrode of the ninth transistor is connected with a first power supply voltage end, and a second stage of the ninth transistor is connected with a control electrode of the fifth transistor; a control electrode of the fifth transistor is connected with a second electrode of the ninth transistor, a first electrode of the fifth transistor is connected with a first power voltage end, and a second electrode of the fifth transistor is connected with a pull-down node;

7. The shift register of claim 6, further comprising: the device comprises a first reset module and a second reset module;

8. The shift register of claim 7, wherein the first reset module comprises a second transistor; the control electrode of the second transistor is connected with a first reset signal end, the first electrode is connected with a pull-up node, and the second electrode is connected with a second power supply voltage end;

9. A gate drive circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 8.

10. A method of driving a shift register, comprising: