CN111596934B - FPGA (field programmable Gate array) remote upgrading method and terminal for RRU (remote radio Unit) equipment of 5G (fourth Generation) distributed base station - Google Patents
FPGA (field programmable Gate array) remote upgrading method and terminal for RRU (remote radio Unit) equipment of 5G (fourth Generation) distributed base station Download PDFInfo
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Abstract
The invention discloses a method and a terminal for remotely upgrading an FPGA (field programmable gate array) of RRU (remote radio unit) equipment of a 5G distributed base station, which operate according to a basic version program of a first storage space; and receiving an upgrading instruction and a first upgrading program sent by the BBU remotely, transferring the first upgrading program to the second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading. The invention can ensure that technicians can remotely upgrade the FPGA of the RRU of several kilometers away through the BBU in a machine room, thereby improving the upgrading efficiency, reducing the operation and maintenance cost, reducing the hardware cost of an upgrading circuit, reducing the program development work of a peripheral CPU or a CPLD and ensuring the reliability of remote upgrading.
Description
Technical Field
The invention relates to the technical field of communication equipment, in particular to a method and a terminal for remotely upgrading FPGA (field programmable gate array) of RRU (radio remote unit) equipment of a 5G distributed base station.
Background
With the development of 4G and 5G mobile communication technologies, operators build more and more distributed base stations, which are a new generation of modern products for completing network coverage. The method is characterized in that a radio frequency processing unit (RRU) and a base station baseband processing unit (BBU) are connected through an optical fiber while being separated. When the network is deployed, the BBU, the core network and the wireless network control equipment are centralized in a machine room, and are connected with the RRU deployed on the planning station through the optical fiber to complete network coverage, so that the construction and maintenance cost is reduced, and the efficiency is improved. According to application scenarios, the RRU is generally far away from the BBU, and is often erected at a higher position from the ground in order to achieve a coverage effect. As a processor for radio frequency signals and digital baseband signals, the FPGA in the RRU is a core device. If the BUG modification and the function upgrade are required to be carried out on the RRU, the program of the FPGA needs to be upgraded.
The traditional FPGA upgrading is that a special JTAG cable is used for programming FLASH of the FPGA, and the method needs technicians to climb an iron tower on site and then upgrade the FPGA by using a computer, so that the upgrading method is low in efficiency and causes a large amount of labor waste.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method and the terminal for remotely upgrading the FPGA of the RRU equipment of the 5G distributed base station are provided, so that technicians can remotely upgrade the FPGA of the RRU of several kilometers away through the BBU in a machine room.
In order to solve the technical problems, the invention adopts the technical scheme that:
a FPGA remote upgrading method for RRU equipment of a 5G distributed base station comprises the following steps:
s1, operating according to the basic version program of the first storage space;
s2, receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
A5G distributed base station RRU equipment FPGA remote upgrade terminal comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, wherein the processor executes the computer program to realize the following steps:
s1, operating according to the basic version program of the first storage space;
s2, receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space, and after the transferring is finished, operating according to the first upgrading program of the second storage space to finish upgrading.
The invention has the beneficial effects that: A5G distributed base station RRU equipment FPGA remote upgrade method and terminal, when RRU equipment leaves factory and does not carry on any procedure upgrade, FPGA is according to the basic edition procedure operation of the first storage space, need to carry on the procedure upgrade to FPGA, receive BBU upgrade order and first upgrade procedure that send remotely, upgrade the procedure to transfer to the second storage space first, after finishing transferring and storing, operate according to the first upgrade procedure of the second storage space, finish upgrading, in order to guarantee the technician can carry on the remote upgrade to the FPGA of RRU several kilometers away through BBU in the computer lab, has raised the staging efficiency, has reduced the operation and maintenance cost; meanwhile, the upgrading program is directly transmitted to the FPGA end through the self-contained optical fiber of the distributed base station without data forwarding and control of the upgrading program through other CPUs or CPLDs. The upgrading process is completely operated by the FPGA independently, and only peripheral simple hardware circuits are matched, so that the upgrading efficiency is further improved, the hardware cost of the upgrading circuit is reduced, and the program development work of a peripheral CPU or CPLD is reduced; in addition, by mounting the two storage spaces and using the second storage space as an upgrading storage space, the FPGA operates according to the basic version program of the first storage space in the upgrading process, so that the influence of uncertain factors such as power failure, transmission faults, interference and the like on the upgrading is ensured in the upgrading process, the FPGA is not upgraded into bricks in the upgrading operation, and the reliability of remote upgrading is ensured.
Drawings
Fig. 1 is a schematic flowchart of a method for remotely upgrading an FPGA of a 5G distributed base station RRU device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a 5G distributed base station RRU device FPGA remote upgrade terminal according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an overall framework between the BBU and the RRU according to an embodiment of the present invention.
Description of reference numerals:
1. A5G distributed base station RRU equipment FPGA remote upgrade terminal; 2. a processor; 3. a memory; 4. BBU; 5. RRU; 6. an FPGA; 7. an analog switch; 8. an EEPROM; 9. FLASH 1; 10. FLASH 2; 11. a latch; 12. and a reset module.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
In order to ensure the comprehension of the present invention, some terms in the present invention are explained as follows:
(1) and RRU: the english abbreviation of Remote Radio Unit means a Radio frequency processing Unit, also called a Radio Remote Unit, belonging to a distributed base station architecture, and connected with the BBU through an optical fiber.
(2) And FPGA: the English abbreviation of Field Programmable Gate Array means Field Programmable logic Gate Array, which is a semi-custom circuit in application specific integrated circuit, is a Programmable logic Array, and can effectively solve the problem of less Gate circuits of the original devices. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core, a bottom layer embedded functional unit and the like.
(3) And BBU: the english abbreviation of Building Base band Unite means a Base station Base band processing unit, and belongs to a distributed Base station architecture.
(4) An EEPROM: the English abbreviation of Electrically Erasable Programmable read only memory means is a memory chip with no data loss after power failure.
(5) And IO: Input/Output (Input/Output).
(6) And FLASH: is a kind of memory chip, and the data in the memory chip can be modified by a specific program.
(7) And SPI: the English abbreviation of Serial Peripheral Interface means a Serial Peripheral Interface, which is a high-speed, full-duplex, synchronous communication bus, and the corresponding connection line is an SPI bus.
(8) I2C: the English abbreviation of Inter-Integrated Circuit means two-wire serial bus, and the corresponding I2C bus is a simple, bidirectional two-wire synchronous serial bus.
Referring to fig. 1, a method for remotely upgrading an FPGA of a 5G distributed RRU device includes the steps of:
s1, operating according to the basic version program of the first storage space;
s2, receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading.
From the above description, the beneficial effects of the present invention are: when the RRU equipment leaves a factory and is not subjected to any program upgrading, the FPGA operates according to a basic version program of a first storage space, when the FPGA needs to be subjected to program upgrading, an upgrading instruction and a first upgrading program sent remotely by a BBU are received, the first upgrading program is transferred to a second storage space, and after the transfer is finished, the FPGA operates according to the first upgrading program of the second storage space to complete upgrading, so that technicians can remotely upgrade the FPGA of RRUs within several kilometers through the BBU in a machine room, the upgrading efficiency is improved, and the operation and maintenance cost is reduced; meanwhile, the upgrading program is directly transmitted to the FPGA end through the self-contained optical fiber of the distributed base station without data forwarding and control of the upgrading program through other CPUs or CPLDs. The upgrading process is completely operated by the FPGA independently, and only peripheral simple hardware circuits are matched, so that the upgrading efficiency is further improved, the hardware cost of the upgrading circuit is reduced, and the program development work of a peripheral CPU or CPLD is reduced; in addition, by mounting the two storage spaces and using the second storage space as an upgrading storage space, the FPGA operates according to the basic version program of the first storage space in the upgrading process, so that the influence of uncertain factors such as power failure, transmission faults, interference and the like on upgrading is ensured in the upgrading process, the FPGA is ensured not to be upgraded into 'bricks' in the upgrading operation, and the reliability of remote upgrading is ensured.
Further, the step S2 specifically includes the following steps:
receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space through a second interface, and changing a first upgrading state value of an EEPROM into a second upgrading state value after the transfer is finished;
switching a first connection state value of a latch to a second connection state value, controlling an analog switch to disconnect a first interface from a first storage space and switch to connect to a second storage space, and disconnecting the second interface from the second storage space at the same time so that the first interface is connected with the second storage space;
sending a reset request signal to a reset module, enabling the reset module to carry out pull-down and pull-up operations on a reset pin according to the reset request signal to complete reset, and loading the first-time upgrading program in the second storage space after the reset is completed;
after normal starting, reading the second upgrading state value stored in the EEPROM, and running according to the first upgrading program of the second storage space to finish upgrading.
From the above description, it can be known that whether the upgrading is performed or not is judged through the upgrading state value of the EEPROM, the first interface for switching the reading program through the latch control analog switch is connected to the second storage space in which the first upgrading program is stored, and the first upgrading program in the second storage space is loaded after the resetting is completed, so that the influence of uncertain factors such as power failure, transmission failure, interference and the like on the upgrading is ensured in the upgrading process, the upgrading operation is ensured not to upgrade the FPGA into "bricks", and the reliability of the remote upgrading is ensured.
Further, the step S2 of changing the first upgrade status value of the EEPROM into the second upgrade status value specifically includes the following steps:
and checking the first-time upgrading program of the second storage space, generating and sending a check value to the BBU, changing the first upgrading state value of the EEPROM into a second upgrading state value if a confirmation upgrading instruction sent remotely by the BBU is received, wherein the confirmation upgrading instruction is sent by the BBU under the condition that the check value stored in the BBU is verified to be the same as the received check value.
From the above description, it can be known that the validity and integrity of the first-time upgrade program are ensured by checking the first-time upgrade program of the second storage space.
Further, the step S2 is followed by the following steps:
s3, if a power-off restart condition is met, reading an upgrade state value of the EEPROM, if the upgrade state value is the second upgrade state value, switching the first connection state value of the latch to the second connection state value, controlling the analog switch to disconnect the first interface from the first storage space and switch the first interface to the second storage space, simultaneously disconnecting the second interface from the second storage space, connecting the first interface with the second storage space, then sending a reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal, completing reset, loading the first upgrade program in the second storage space after reset is completed, and reading the second upgrade state value stored in the EEPROM after normal start, and running according to the first upgrading program of the second storage space to finish upgrading.
As can be seen from the above description, after the FPGA is upgraded, if the RRU device is powered off, the latch is restored to the initial state, and the analog switch is also restored to the default state, that is, the first interface of the FPGA is connected to the first storage space, the second interface is connected to the second storage space, and the FPGA loads the basic version program from the first storage space.
Further, the step S2 is followed by the following steps:
s4, receiving a new upgrade instruction remotely sent by the BBU, changing the second upgrade state value of the EEPROM into a third upgrade state value, resetting the latch to the first connection state value, controlling the analog switch to connect the first interface with the first storage space and the second interface with the second storage space, and then sending the reset request signal to the reset module, the reset module pulls down and pulls up the reset pin according to the reset request signal to complete the reset, after the reset is completed, loading the basic version program of the first storage space, reading the third upgrading state value stored in the EEPROM after the basic version program is normally started, erasing the first upgrading program stored in the second storage space through the second interface, and returning information that upgrading equipment is completed;
receiving a secondary upgrade program sent by the BBU, transferring the secondary upgrade program to the second storage space through the second interface, changing the third upgrade state value of the EEPROM into the second upgrade state value after the secondary upgrade program is verified, switching the latch into the second connection state value, controlling the analog switch to connect the first interface with the second storage space, then sending the reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal to complete reset, loading the secondary upgrade program of the second storage space after the reset is completed, and after the secondary upgrade program is normally started, reading the second upgrade state value stored in the EEPROM, and then operating according to the secondary upgrade program of the second storage space, and finishing the secondary upgrading.
As can be seen from the above description, after the FPGA is upgraded, the FPGA program needs to be upgraded subsequently, and the program loaded by the FPGA is switched back to the basic version program in the first storage space, so as to ensure normal use of the FPGA in the upgrading process; then clearing the first upgrading program stored in the second storage space to store a second upgrading program, and then carrying out inspection, upgrading state change, connection switching, resetting and restarting so that the FPGA loads the second upgrading program of the second storage space to operate to complete the continuous updating of the program of the FPGA; meanwhile, after each upgrade, the upgrade state value of the EEPROM is the second upgrade state value, so that the FPGA can judge whether to execute according to the basic version program of the first storage space or the latest version program of the second storage space by depending on the upgrade state value of the EEPROM under any condition.
Referring to fig. 2 and fig. 3, a 5G distributed base station RRU device FPGA remote upgrade terminal includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor implements the following steps when executing the computer program:
s1, operating according to the basic version program of the first storage space;
s2, receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading.
From the above description, the beneficial effects of the present invention are: when the RRU equipment leaves the factory and is not upgraded with any program, the FPGA operates according to a basic version program of the first storage space, when the FPGA needs to be upgraded with the program, an upgrade instruction and a first upgrade program sent remotely by the BBU are received, the first upgrade program is transferred to the second storage space, after the transfer is finished, the FPGA operates according to the first upgrade program of the second storage space, the upgrade is completed, so that technicians can remotely upgrade the FPGA of RRUs beyond a few kilometers through the BBU in a machine room, the upgrade efficiency is improved, and the operation and maintenance cost is reduced; meanwhile, the upgrading program is directly transmitted to the FPGA end through the self-contained optical fiber of the distributed base station without data forwarding and control of the upgrading program through other CPUs or CPLDs. The upgrading process is completely operated by the FPGA independently, and only peripheral simple hardware circuits are matched, so that the upgrading efficiency is further improved, the hardware cost of the upgrading circuit is reduced, and the program development work of a peripheral CPU or CPLD is reduced; in addition, by mounting the two storage spaces and using the second storage space as an upgrading storage space, the FPGA operates according to the basic version program of the first storage space in the upgrading process, so that the influence of uncertain factors such as power failure, transmission faults, interference and the like on the upgrading is ensured in the upgrading process, the FPGA is not upgraded into bricks in the upgrading operation, and the reliability of remote upgrading is ensured.
Further, when the processor executes the step S2 of the computer program, the following steps are specifically implemented:
receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space through a second interface, and changing a first upgrading state value of an EEPROM into a second upgrading state value after the transfer is finished;
switching a first connection state value of a latch to a second connection state value, controlling an analog switch to disconnect a first interface from a first storage space and switch to connect to a second storage space, and disconnecting the second interface from the second storage space at the same time so that the first interface is connected with the second storage space;
sending a reset request signal to a reset module, enabling the reset module to carry out pull-down and pull-up operations on a reset pin according to the reset request signal to complete reset, and loading the first-time upgrading program in the second storage space after the reset is completed;
after normal starting, reading the second upgrading state value stored in the EEPROM, and running according to the first upgrading program of the second storage space to finish upgrading.
From the above description, it can be known that whether the upgrading is performed or not is judged through the upgrading state value of the EEPROM, the first interface for switching the reading program through the latch control analog switch is connected to the second storage space in which the first upgrading program is stored, and the first upgrading program in the second storage space is loaded after the resetting is completed, so that the influence of uncertain factors such as power failure, transmission failure, interference and the like on the upgrading is ensured in the upgrading process, the upgrading operation is ensured not to upgrade the FPGA into "bricks", and the reliability of the remote upgrading is ensured.
Further, when the processor executes the step S2 of the computer program and changes the first upgrade status value of the EEPROM into the second upgrade status value, the following steps are specifically implemented:
and checking the first-time upgrading program of the second storage space, generating and sending a check value to the BBU, changing the first upgrading state value of the EEPROM into a second upgrading state value if a confirmation upgrading instruction sent remotely by the BBU is received, wherein the confirmation upgrading instruction is sent by the BBU under the condition that the check value stored in the BBU is verified to be the same as the received check value.
From the above description, it can be known that the validity and integrity of the first-time upgrade program are ensured by checking the first-time upgrade program of the second storage space.
Further, the processor after executing the step S2 of the computer program further realizes the following steps:
s3, if a power-off restart condition is met, reading an upgrade state value of the EEPROM, if the upgrade state value is the second upgrade state value, switching the first connection state value of the latch to the second connection state value, controlling the analog switch to disconnect the first interface from the first storage space and switch the first interface to the second storage space, simultaneously disconnecting the second interface from the second storage space, connecting the first interface with the second storage space, then sending a reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal, completing reset, loading the first upgrade program in the second storage space after reset is completed, and reading the second upgrade state value stored in the EEPROM after normal start, and running according to the first upgrading program of the second storage space to finish upgrading.
As can be seen from the above description, after the FPGA is upgraded, if the RRU device is powered off, the latch is restored to the initial state, and the analog switch is also restored to the default state, that is, the first interface of the FPGA is connected to the first storage space, the second interface is connected to the second storage space, and the FPGA loads the basic version program from the first storage space.
Further, the processor after executing the step S2 of the computer program further realizes the following steps:
s4, receiving a new upgrade instruction remotely sent by the BBU, changing the second upgrade state value of the EEPROM into a third upgrade state value, resetting the latch to the first connection state value, controlling the analog switch to connect the first interface with the first storage space and the second interface with the second storage space, and then sending the reset request signal to the reset module, the reset module pulls down and pulls up the reset pin according to the reset request signal to complete the reset, after the reset is completed, loading the basic version program of the first storage space, reading the third upgrading state value stored in the EEPROM after the basic version program is normally started, erasing the first upgrading program stored in the second storage space through the second interface, and returning information that upgrading equipment is completed;
receiving a secondary upgrade program sent by the BBU, transferring the secondary upgrade program to the second storage space through the second interface, changing the third upgrade state value of the EEPROM into the second upgrade state value after the secondary upgrade program is verified, switching the latch into the second connection state value, controlling the analog switch to connect the first interface with the second storage space, then sending the reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal to complete reset, loading the secondary upgrade program of the second storage space after the reset is completed, and after the secondary upgrade program is normally started, reading the second upgrade state value stored in the EEPROM, and then operating according to the secondary upgrade program of the second storage space, and finishing the secondary upgrading.
As can be seen from the above description, after the FPGA is upgraded, the FPGA program needs to be upgraded subsequently, and the program loaded by the FPGA is switched back to the basic version program in the first storage space, so as to ensure normal use of the FPGA in the upgrading process; then clearing the first upgrading program stored in the second storage space to store a second upgrading program, and then carrying out inspection, upgrading state change, connection switching, resetting and restarting so that the FPGA loads the second upgrading program of the second storage space to operate to complete the continuous updating of the program of the FPGA; meanwhile, after each upgrade, the upgrade state value of the EEPROM is the second upgrade state value, so that the FPGA can judge whether to execute according to the basic version program of the first storage space or the latest version program of the second storage space by depending on the upgrade state value of the EEPROM under any condition.
Referring to fig. 1, a first embodiment of the present invention is:
a FPGA remote upgrading method for RRU equipment of a 5G distributed base station comprises the following steps:
s1, operating according to the basic version program of the first storage space;
when RRU equipment leaves a factory, an EEPROM writes a first upgrading state value 1, a first storage space pre-records a basic version program, when a distributed base station is erected and switched on, the RRU equipment is started, an FPGA defaults to read the basic version program from the first storage space, when the FPGA is started, the upgrading state value of an EEPROM module is read to be the first upgrading state value 1, the FPGA does not upgrade the program, the RRU equipment operates according to the basic version program in the first storage space, and the RRU equipment normally works;
s2, receiving an upgrading instruction and a first upgrading program sent by the BBU remotely, transferring the first upgrading program to the second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading.
In this embodiment, step S2 specifically includes the following steps:
receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space through a second interface, verifying the first upgrading program of the second storage space after the transferring is finished, generating and sending a verification value to the BBU, changing a first upgrading state value of an EEPROM into a second upgrading state value if a confirmation upgrading instruction sent by the BBU remotely is received, and confirming that the upgrading instruction is sent by the BBU under the condition that the verification value stored by the BBU is verified to be the same as the received verification value;
switching the first connection state value of the latch to a second connection state value, controlling the analog switch to disconnect the first interface from the first storage space and switch to connect to the second storage space, and simultaneously disconnecting the second interface from the second storage space so as to connect the first interface with the second storage space;
sending a reset request signal to a reset module, enabling the reset module to carry out pull-down and pull-up operations on a reset pin according to the reset request signal to complete reset, and loading a first-time upgrading program in a second storage space after the reset is completed;
after normal starting, reading a second upgrading state value stored in the EEPROM, and running according to a first upgrading program of a second storage space to finish upgrading.
The method comprises the steps that program upgrading operation is needed to be carried out on FPGA, a BBU sends an upgrading instruction to FPGA, the FPGA receives a first upgrading program transmitted from the BBU after receiving the upgrading instruction and transfers the upgrading program to a second storage space through an SPI2 bus, the FPGA verifies the first upgrading program in the second storage space after completing transferring operation, after the verification is passed, the FPGA changes an upgrading state value of an EEPROM from a first upgrading state value 1 to a second upgrading state value 2, then the FPGA sends the instruction to a latch, the latch controls an analog switch to switch a first interface, used for loading the program, of the FPGA from the first storage space to the second storage space, and meanwhile, the second interface is disconnected from the second storage space.
And then, the FPGA sends a reset request signal to the reset module through the IO port, and after the reset module receives the reset request of the FPGA, the reset module performs reset operation on the FPGA by pulling down and then pulling up the reset pin of the FPGA. After the FPGA is reset, the latch continues to latch the current state value, the first interface of the FPGA can load a first upgrading program from the second storage space, the FPGA reads the upgrading state value of the EEPROM after being normally started, and if the upgrading state value is 2, the FPGA normally works according to the mode, and upgrading is completed. And if the read state value is 1, clearing the latch, recovering the initial state of the analog switch, sending a reset request signal, and resetting the FPGA by the reset module so that the FPGA is loaded to the factory-delivered basic version program.
After the FPGA is upgraded, if the RRU device is powered off, the latch recovers to an initial state, the analog switch also recovers to a default state, that is, the first interface of the FPGA is connected to the first storage space, the second interface is connected to the second storage space, and the FPGA loads the basic version program from the first storage space, and at this time, the method further includes the following steps:
s3, if the situation of power failure and restart is met, reading an upgrading state value of the EEPROM, if the situation of power failure and restart is met, switching the first connection state value of the latch to a second connection state value, controlling the analog switch to disconnect the first interface from the first storage space and switch the first interface to the second storage space, simultaneously disconnecting the second interface from the second storage space, connecting the first interface with the second storage space, then sending a reset request signal to the reset module, enabling the reset module to carry out pull-down and pull-up operations on the reset pin according to the reset request signal to complete reset, loading a first upgrading program in the second storage space after the reset is completed, reading the second upgrading state value stored in the EEPROM after normal start, and running according to the first upgrading program of the second storage space to complete upgrading.
After the FPGA is upgraded, the following steps are included when the FPGA program is required to be upgraded subsequently:
s4, receiving a new upgrade instruction sent by the BBU remotely, changing a second upgrade state value of the EEPROM into a third upgrade state value, resetting the latch into a first connection state value, controlling the analog switch to connect the first interface with the first storage space and connect the second interface with the second storage space, then sending a reset request signal to the reset module, enabling the reset module to carry out pull-down and pull-up operations on the reset pin according to the reset request signal, completing reset, loading a basic version program of the first storage space after the reset is completed, reading a third upgrade state value of the EEPROM after the normal start of the memory, erasing a first upgrade program stored in the second storage space through the second interface, and returning information that the upgrade equipment has been completed;
receiving a secondary upgrading program sent by the BBU, transferring the secondary upgrading program to a second storage space through a second interface, changing a third upgrading state value of the EEPROM into a second upgrading state value after the secondary upgrading program is verified, switching the latch into a second connection state value, controlling the analog switch to connect the first interface with the second storage space, and then sending a reset request signal to the reset module, so that the reset module performs pull-down and pull-up operations on the reset pin according to the reset request signal to complete reset, loading the secondary upgrading program of the second storage space after the reset is completed, reading the second upgrading state value stored in the EEPROM after the reset module is normally started, and then running according to the secondary upgrading program of the second storage space to complete secondary upgrading.
In each subsequent upgrading process, the latest upgrading program is equivalent to the secondary upgrading program in step S4, and the last upgrading program is equivalent to the primary upgrading program in step S4, so that the program of the FPGA is continuously updated.
Referring to fig. 2 and fig. 3, a second embodiment of the present invention is:
a 5G distributed base station RRU device FPGA remote upgrade terminal 1 includes a memory 3, a processor 2, and a computer program stored on the memory 3 and operable on the processor 2, where the processor 2 implements steps S1 to S4 in the first embodiment when executing the computer program.
As shown in fig. 3, in this embodiment, the processor 2 is equivalent to the FPGA6 in the RRU5, and the memory 3 is any storage device in the RRU5, so that the processor can also be regarded as a storage device including the FPGA6 in the RRU5 and a computer program including the steps S1 to S4 in the first embodiment.
In this embodiment, an overall architecture between the BBU4 and the RRU5 is as shown in fig. 3, and corresponds to the analog switch 7, the EEPROM8, the latch 11, and the RESET module 12 in the first embodiment, where FLASH19 is a first storage space used for storing a basic version program, FLASH210 is a second storage space used for storing a latest upgrade program, RESET is a RESET pin, SPI1 is a first interface, and SPI2 is a second interface.
In summary, according to the method and the terminal for remotely upgrading the FPGA of the RRU device of the 5G distributed base station provided by the present invention, when the RRU device leaves the factory and is not upgraded with any program, the FPGA operates according to the basic version program of the first storage space, when the program upgrading needs to be performed on the FPGA, the FPGA receives the upgrade instruction and the first upgrade program remotely sent by the BBU, the first upgrade program is transferred to the second storage space, and after the transfer, the FPGA operates according to the first upgrade program of the second storage space to complete the upgrade, so that a technician can remotely upgrade the FPGA of the RRU over several kilometers in a machine room through the BBU, the upgrade efficiency is improved, and the operation and maintenance cost is reduced; meanwhile, the upgrading program is directly transmitted to the FPGA end through the self-contained optical fiber of the distributed base station without data forwarding and control of the upgrading program through other CPUs or CPLDs. The upgrading process is completely operated by the FPGA independently, and only peripheral simple hardware circuits are matched, so that the upgrading efficiency is further improved, the hardware cost of the upgrading circuit is reduced, and the program development work of a peripheral CPU or CPLD is reduced; in addition, two storage spaces are mounted, the second storage space is used as an upgrading storage space, whether upgrading is conducted or not is judged through an upgrading state value of the EEPROM in the upgrading process, the first interface of the reading program is switched to the second storage space in which the first upgrading program is stored through the latch control analog switch, the first upgrading program in the second storage space is loaded after resetting is completed, the influence of uncertain factors such as power failure, transmission faults and interference on upgrading is guaranteed in the upgrading process, the FPGA is guaranteed not to be upgraded into 'bricks' in the upgrading operation, and reliability of remote upgrading is guaranteed. After the FPGA is upgraded, if the RRU equipment is powered off, connection switching, resetting and restarting are carried out according to the upgrade state value of the EEPROM, so that the FPGA loads the first upgrade program of the second storage space to operate, and the FPGA can still operate according to the upgraded program after the FPGA is powered off and restarted. And the continuous updating of the program of the FPGA is supported, so that an effective and reliable FPGA program upgrading mode with high upgrading efficiency and low cost is provided under the condition of not increasing a peripheral controller and only depending on the own programmable logic function of the FPGA.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (4)
1. A FPGA remote upgrading method for RRU equipment of a 5G distributed base station is characterized by comprising the following steps:
s1, operating according to the basic version program of the first storage space;
s2, receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading;
the step S2 specifically includes the following steps:
receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space through a second interface, and changing a first upgrading state value of the EEPROM into a second upgrading state value after the transferring is finished;
switching a first connection state value of a latch to a second connection state value, controlling an analog switch to disconnect a first interface from a first storage space and switch to connect to a second storage space, and disconnecting the second interface from the second storage space at the same time so that the first interface is connected with the second storage space;
sending a reset request signal to a reset module, enabling the reset module to carry out pull-down and pull-up operations on a reset pin according to the reset request signal to complete reset, and loading the first-time upgrading program in the second storage space after the reset is completed;
after normal starting, reading that the second upgrading state value is stored in the EEPROM, and running according to the first upgrading program of the second storage space to finish upgrading;
the step S2 is followed by the following steps:
s3, if a power-off restart condition is met, reading an upgrade state value of the EEPROM, if the upgrade state value is the second upgrade state value, switching the first connection state value of the latch to the second connection state value, controlling the analog switch to disconnect the first interface from the first storage space and switch the first interface to the second storage space, simultaneously disconnecting the second interface from the second storage space, connecting the first interface with the second storage space, then sending a reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal, completing reset, loading the first upgrade program in the second storage space after reset is completed, and reading the second upgrade state value stored in the EEPROM after normal start, the first upgrading program of the second storage space is operated to complete upgrading;
the step S2 is followed by the following steps:
s4, receiving a new upgrade instruction remotely sent by the BBU, changing the second upgrade state value of the EEPROM into a third upgrade state value, resetting the latch to the first connection state value, controlling the analog switch to connect the first interface with the first storage space and the second interface with the second storage space, and then sending the reset request signal to the reset module, the reset module pulls down and pulls up the reset pin according to the reset request signal to complete the reset, after the reset is completed, loading the basic version program of the first storage space, reading the third upgrading state value stored in the EEPROM after the basic version program is normally started, erasing the first upgrading program stored in the second storage space through the second interface, and returning information that upgrading equipment is completed;
receiving a secondary upgrade program sent by the BBU, transferring the secondary upgrade program to the second storage space through the second interface, changing the third upgrade state value of the EEPROM into the second upgrade state value after the secondary upgrade program is verified, switching the latch into the second connection state value, controlling the analog switch to connect the first interface with the second storage space, then sending the reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal to complete reset, loading the secondary upgrade program of the second storage space after the reset is completed, and after the secondary upgrade program is normally started, reading the second upgrade state value stored in the EEPROM, and then operating according to the secondary upgrade program of the second storage space, and finishing the secondary upgrading.
2. The method for remotely upgrading FPGA of RRU equipment in 5G distribution base station according to claim 1, wherein the step S2 of changing the first upgrade status value of the EEPROM into the second upgrade status value specifically includes the following steps:
and checking the first-time upgrading program of the second storage space, generating and sending a check value to the BBU, changing the first upgrading state value of the EEPROM into a second upgrading state value if a confirmation upgrading instruction sent remotely by the BBU is received, wherein the confirmation upgrading instruction is sent by the BBU under the condition that the check value stored in the BBU is verified to be the same as the received check value.
3. A5G distributed base station RRU equipment FPGA remote upgrade terminal, including the memorizer, processor and computer program stored in the memorizer and can run on the processor, characterized by that, the said processor implements the following steps when executing the said computer program:
s1, operating according to the basic version program of the first storage space;
s2, receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space, and after the transfer is finished, operating according to the first upgrading program of the second storage space to finish upgrading;
when the processor executes the step S2 of the computer program, the following steps are specifically implemented:
receiving an upgrading instruction and a first upgrading program sent by a BBU remotely, transferring the first upgrading program to a second storage space through a second interface, and changing a first upgrading state value of an EEPROM into a second upgrading state value after the transfer is finished;
switching a first connection state value of a latch to a second connection state value, controlling an analog switch to disconnect a first interface from a first storage space and switch to connect to a second storage space, and disconnecting the second interface from the second storage space to connect the first interface with the second storage space;
sending a reset request signal to a reset module, enabling the reset module to carry out pull-down and pull-up operations on a reset pin according to the reset request signal to complete reset, and loading the first-time upgrading program in the second storage space after the reset is completed;
after normal starting, reading the second upgrading state value stored in the EEPROM, and running according to the first upgrading program of the second storage space to finish upgrading;
the processor after executing the step S2 of the computer program further realizes the following steps:
s3, if a power-off restart condition is met, reading an upgrade state value of the EEPROM, if the upgrade state value is the second upgrade state value, switching the first connection state value of the latch to the second connection state value, controlling the analog switch to disconnect the first interface from the first storage space and switch the first interface to the second storage space, simultaneously disconnecting the second interface from the second storage space, connecting the first interface with the second storage space, then sending a reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal, completing reset, loading the first upgrade program in the second storage space after reset is completed, and reading the second upgrade state value stored in the EEPROM after normal start, the first upgrading program of the second storage space is operated to complete upgrading;
the processor after executing the step S2 of the computer program further realizes the following steps:
s4, receiving a new upgrade instruction remotely sent by the BBU, changing the second upgrade state value of the EEPROM into a third upgrade state value, resetting the latch to the first connection state value, controlling the analog switch to connect the first interface with the first storage space and the second interface with the second storage space, and then sending the reset request signal to the reset module, the reset module pulls down and pulls up the reset pin according to the reset request signal to complete the reset, after the reset is completed, loading the basic version program of the first storage space, reading the third upgrading state value stored in the EEPROM after the basic version program is normally started, erasing the first upgrading program stored in the second storage space through the second interface, and returning information that upgrading equipment is completed;
receiving a secondary upgrade program sent by the BBU, transferring the secondary upgrade program to the second storage space through the second interface, changing the third upgrade state value of the EEPROM into the second upgrade state value after the secondary upgrade program is verified, switching the latch into the second connection state value, controlling the analog switch to connect the first interface with the second storage space, then sending the reset request signal to the reset module, enabling the reset module to perform pull-down and pull-up operations on the reset pin according to the reset request signal to complete reset, loading the secondary upgrade program of the second storage space after the reset is completed, and after the secondary upgrade program is normally started, reading the second upgrade state value stored in the EEPROM, and then operating according to the secondary upgrade program of the second storage space, and finishing secondary upgrading.
4. The terminal of claim 3, wherein the processor executes the step S2 of the computer program to change the first upgrade status value of the EEPROM into the second upgrade status value, and specifically implements the following steps:
and checking the first-time upgrading program of the second storage space, generating and sending a check value to the BBU, changing the first upgrading state value of the EEPROM into a second upgrading state value if a confirmation upgrading instruction sent remotely by the BBU is received, wherein the confirmation upgrading instruction is sent by the BBU under the condition that the check value stored in the BBU is verified to be the same as the received check value.
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