CN1115893A

CN1115893A - Computer index memory with shared cache subsystem

Info

Publication number: CN1115893A
Application number: CN94109021A
Authority: CN
Inventors: 吴章隆; 刘秉章
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 1994-07-28
Filing date: 1994-07-28
Publication date: 1996-01-31
Anticipated expiration: 2014-07-28
Also published as: CN1049750C

Abstract

The said index memory includes several index address bits with several data bus, one change bit with several data bus positions and several processor state bits with several data bus positions. The said processor state bits can store the enquiry state of data bus in processor cache, record separately enquiry write hit state of every processor cache in computer system so as to reduce local enquiry period and raise efficiency of integrated system.

Description

The computer index memory device of shared cache subsystem

The invention relates to the cache subsystem of computer system, specific, the invention relates to the index storage structure of the cache subsystem of the computer system that can possess the multichannel processor, more particularly, the invention relates to the index storage structure of the cache subsystem of the computer system that possesses multichannel processor and shared secondary cache subsystem.

Along with the quick progress of microprocessor (microprocessor) technology, be computer system based with the microprocessor, also have same progressive fast application function miscellaneous thereupon.On the other hand, though the microprocessor function is progressive apace, not only geometric ratio ground does not improve its price along with the progress of function, shows the price/function ratio that progressively lowers on the contrary.A typical example is (the Apple Comput-ers of Apple Computer by the U.S., Inc), " Power PC " microprocessor (" PowerPC " processor) of the common release of institute of International Business Machines Corporation (International Businese Machin-es Corporation) and Motorola Semiconductor Inc (Motorola Semicoductor), Pentium microprocessor (" Pentium " processor) with Ying Daier company (Intel Corpration) on function belongs to same grade approximately, but price then cheap rough half.

CPU (central processing unit) (CPU as most computer systems, central process-ing unit) and microprocessor, because the trend that this function progress and price glide, bring some remarkable and important changes in the design of computer system with using.Wherein a kind of tangible trend is, though the function of microprocessor from strength to strength, for some purposes such as engineering calculation etc., the ability of its calculating still belongs to desirable not to the utmost.But, because aforesaid low-cost factor, a kind of way that increases the arithmetic capability of computer system promptly is the quantity that increases microprocessor in the computer system, and promptly so-called multichannel processor computer system (multiprocessor computer system) uses.

On the other hand, the technology of microprocessor now is though advancing fast really within the scope of reasonable price has the another kind of key element of equal importance with microprocessor among the computer system, that is the semiconductor memory device, its situation is really not so.The semiconductor memory that is suitable in the scope of reasonable price has two kinds basically at present, that is dynamic random access memory (DRAM, dynamic random access memory) with static random-access memory (SRAM, static random access memory).DRAM has sizable unit memory capacity, but its access speed, with now high-performance microprocessor by comparison, but seem and make us intolerable slow.Typical high-performance microprocessor is if will just may only bring into play being no more than its function of 20 percent with DRAM as the operation module, and remaining time all must be waited for the response of DRAM at a slow speed.On the other hand,, but still can't be fully be complementary, and its unit memory capacity and DRAM have been little also much by comparison with the fastest now microprocessor though SRAM has higher access speed.

Because the relation of aforementioned module the status of technology, high-performance microprocessor has now all adopted so-called cache store to dash the project organization of storage (cache memory), directly will be in a small amount but speed must be enough to the cache that mates fully with microprocessor itself soon, be called main hypervelocity buffer storage (primary cache), be made in microprocessor internal.Moreover, good Computer System Design also is arranged at the structure of cache between slower but the cheap and a large amount of DRAM main memory of microprocessor and computer system, be called secondary cache (secondary cache), so that the whole memory access speed of computer system is increased to the fastest possible speed (about seven to ninety percent of main cache speed, deciding on the project organization and the capacity of cache).

For adopting the modern high performance microprocessor as for the CPU multichannel processor computer system, itself promptly can have the main cache of its inside applied each microprocessor, so, in order to save cost, this multichannel microprocessor system is often only used one group of level cache subsystem.

Among the computer system of having used primary and secondary two-stage cache, very important main points in its hardware configuration design, be to keep by the high speed of microprocessor internal to store the main cache that is constituted, by the secondary cache that SRAM constituted, and by the data compatibility between the system hosts storage that DRAM constituted, be called cache store and dash the storage consistance, or cache store dashes storage compatibility (cache coherency or cache consistency).In order to keep the compatibility that cache store dashes storage, having each microprocessor in the computer system of multi-processor all needs to carry out some comparatively complicated time-consuming cache stores on the opportunity of necessity and dashes the action that the storage compatibility is checked.

To have adopted Intel Pentium microprocessor is that the multichannel processor computer system of primary processor is an example, in case there is the primary processor (bus master) on the bus to take after the resource of system, just must check immediately among whether the storage address of this bus primary processor institute access also is present in the main Pentium processor of system, if the words that have, the state of these data how, the state of these data after this bus primary processor used this storage address again should be how, or the like.This computer system is dashed the processing of storing compatibility to its cache store can be according to so-called MESI agreement (MESI protocol, Modified/Exclus-ive/Shared/Invalid protocol), utilize the inquiry cycle (inquire cycle or snoop cycle) of carrying out microprocessor to handle.Because the inquiry cycle that this microprocessor carried out need spend considerable CPU time, and can take the bus time in the computer system, therefore how computer system designs, minimize so that will carry out the chance of this inquiry action, become an important theme of design high-performance computer system.

Therefore, the objective of the invention is to be to provide multichannel processor index storage (tag RAM) structure of a kind of shared cache subsystem, go for the multichannel processor environment of computer system, at different processor for recording reaction individual data lines and the relation between the par-ticular processor.

Consisting of of the computer index memory structure of shared cache subsystem of the present invention: this device is installed in one and includes the primary processor that inner cache store dashes storage, the system hosts storage, and in computer system that is arranged at the secondary cache between this primary processor and this system hosts storage, the index storing apparatus that this shared cache store dashes the storage subsystem includes:

A plurality of index addresses position with many data lines;

A change bit with a plurality of linear position datas; With

A plurality of processor states position with a plurality of linear position datas;

The inquiry state of each bar data line in the cache that is stored in processor can be write down in this a plurality of processor states position.

Other purpose of the present invention and characteristics will be described in detail in conjunction with the accompanying drawings in the back.

Brief Description Of Drawings:

Fig. 1 is a synoptic diagram, shows the structure of the typical index storage of being adopted in the common technology; With

Fig. 2 is a synoptic diagram, shows multichannel processor computer system index storage (tag RAM) structure according to shared cache subsystem of the present invention.

At first with reference to figure 1, wherein shown is the typical index memory structure that computer system adopted in the common technology.Cache store with direct mapping is an example towards storage subsystem (direct-mapped cache memory subsystem), altogether each the

bar data line

31,32,33 in the hypervelocity buffered data memory 30 of n bar data line ... etc. stored position, at cache store among index memory 40, all respectively have a

correspondence index storage

41,42,43 ... the position.On the other hand, 40 of hypervelocity buffer index storages include index address (tag address) the position tag[MSB of a right quantity altogether] 61, tag[MSB-1] 62 ... TAG[LSB) m-1.Typical directly mapping cache store dashes the storage subsystem and may include 8 index address.Except this index address of 8, cache store with data write-back (write back) ability also can use an extra change bit (dirty bit or altered bit) 51 to write down towards storage control system, and the cache store that CPU revised of process computer system dashes the storage content, so that before this cache store will be capped towards stored position, write back among the main memory of system in advance.

Aforesaid common technology cache store is towards the index memory system, among its computer system, when having primary processor on the bus of being arranged to exist, can't write down relation between a certain particular data line and this par-ticular processor at each different processor.At this moment, with reference to figure 2, the present invention has expanded hypervelocity buffer index storage structure commonly used, except original hypervelocity buffered data memory 30, and dash outside storage index address position 40 and the change bit 51 at original cache store, gone up the relevant corresponding mode bit 70 of processor identical among the computer system more with the quantity of all processors, comprised P (m-1) CIN71, P (m-2) CIN 72 ... reach m bit such as POCIN 79 grades.Among this structure, each

processor state position

71,72 ... etc., all be used to store each processor CPU (m-1) 81, CPU (m-2) 82 among the computer system ... and the data mode of m processor such as CPU0 89 on this data line respectively.

Cache store in Fig. 2 is among storage structure, and whole cache store dashes the storage subsystem and held the n bar cache store of m processor of multichannel processor computer system towards the shared cache (shared cache memory) of access data line.P wherein (m-1) CIN 71, P (m-2) CIN 72 ... and the action of m bit part such as POCIN 79 describes in detail in the back.

Computer system supposes with CPU0 to start total system that the expansion part that has then comprised hypervelocity buffer index storage structure of the present invention promptly can be initialized to as following state when starting:

[P (m-1) CIN ... ..P1CIN, POCIN]=[0 ... 0,1] if CPU1 carries out the action of data read, and reach to read and hit (read hit), then

[P (m-1) CIN ... P1CIN, POCIN]=[0 ... 1,1] if the state that is reached is to inquire to write to hit (snoop write hit), then just be zero with all bit clears

[P(m-1)CIN、......P1CIN、POCIN]＝[0、......0、0]

Utilize this calculation rule (algorithm), the present invention is 0 o'clock being checked through a PxCIN, promptly can determine not include this cache store towards the stored data line among this x CPUx, when inquiring the cycle, can avoid this CPUx, save institute's time that must take inquiry cycle, and then the efficient of increase system.

So, the present invention utilizes the hypervelocity buffer index storage structure of expansion, the cache store of each processor dashes the storage inquiry and writes hit condition among the logger computer system respectively, just can among the situation of part, reduce or remit the carrying out in inquiry cycle, because the carrying out in inquiry cycle needs the more relatively cpu clock cycle of cost, therefore, the minimizing in inquiry cycle means that promptly the integral body of system effectiveness improves.

Claims

1. the shared cache store of computer system dashes the index storing apparatus that stores subsystem, this device is installed in one and includes the primary processor that inner cache store dashes storage, the system hosts storage, and in computer system that is arranged at the secondary cache between this primary processor and this system hosts storage, the index storing apparatus that this shared cache store dashes the storage subsystem includes:

A plurality of index addresses position with many data lines;

A change bit with a plurality of linear position datas; With

It is characterized in that this a plurality of processor states position can write down the inquiry state of each bar data line in the cache that is stored in processor.

2. the index storing apparatus of computer system shared cache subsystem as claimed in claim 1, wherein this computer system more includes a plurality of bus primary processors on the bus that is arranged on this computer system.

3. the index storing apparatus of computer system shared cache subsystem as claimed in claim 2, wherein this computer system more includes the secondary cache subsystem more than a group.

4. the index storing apparatus of computer system shared cache subsystem as claimed in claim 2, wherein this bus primary processor includes inner cache.

5. the index storing apparatus of computer system shared cache subsystem as claimed in claim 2, wherein this bus primary processor does not comprise inner cache.