CN111585607A - Demodulation method and device based on CFFH/DS system - Google Patents
Demodulation method and device based on CFFH/DS system Download PDFInfo
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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- H04L2027/0024—Carrier regulation at the receiver end
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Abstract
The embodiment of the invention provides a demodulation method and a device based on a CFFH/DS system, wherein the method comprises the steps of firstly carrying out code offset compensation and phase compensation on a target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization; then, respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value; and finally, performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value. And in the demodulation stage, the real-time code offset compensation and the phase compensation of the signals are realized, and the error rate of demodulation is reduced.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a demodulation method and apparatus based on a CFFH/DS system.
Background
Currently, the spread spectrum technique is to broaden the spectrum of a transmission signal with a specific spreading function to improve the reliability of a communication system, and commonly used spread spectrum techniques include direct sequence spread spectrum, frequency hopping spread spectrum, time hopping, and hybrid spread spectrum.
The single Direct Sequence has the disadvantages of limited spreading gain, severe near-far effect, poor narrowband interference resistance and poor aligned interference resistance, etc., the hybrid spreading is a spreading mode combining multiple spreading technologies, for example, a hybrid spreading technology combining a Direct Sequence-Spread Spectrum (DS) technology and a Coherent Fast Frequency Hopping (CFFH) technology, and a communication system formed based on the hybrid spreading technology is a Coherent Fast frequency hopping/Direct Sequence Spread Spectrum hybrid system (hereinafter, referred to as CFFH/DS system). The CFFH/DS system combines the characteristics of a direct sequence spread spectrum technology and a frequency hopping technology, can obviously improve the signal processing gain of the system, can effectively overcome the near-far effect, improves the narrowband interference resistance, has extremely strong anti-interference performance and low detection probability, and has extremely wide application in military communication.
Demodulation is a very critical step for a receiver of a CFFH/DS system and directly affects the bit error rate of a received signal. Under the conditions of large dynamics and non-zero second-order change rate of Doppler at the receiving and transmitting ends, frequency offset, time delay and code offset can be changed in real time, and the accuracy of demodulation cannot be guaranteed only by estimation in the processes of capturing, fine searching and the like in a frame synchronization stage. Therefore, it is desirable to provide a demodulation method and apparatus based on CFFH/DS system under large dynamic conditions.
Disclosure of Invention
To overcome the above problems or at least partially solve the above problems, embodiments of the present invention provide a demodulation method and apparatus based on a CFFH/DS system.
In a first aspect, an embodiment of the present invention provides a demodulation method based on a CFFH/DS system, including:
performing code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization;
respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value;
and performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value.
Preferably, the performing code offset estimation on the first type of signal specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data sampling rate of the second-class signals is one time of the chip rate;
carrying out coherent accumulation on data contained in each symbol of each path of the second-class signals in real time until the number of accumulated symbols reaches a first preset number to obtain a first-class sum data;
and taking a modulus of all the first class sum data, and determining the code bias estimated value based on the extraction position corresponding to the first class sum data with the maximum modulus.
Preferably, the phase estimation of the first type of signal specifically includes:
respectively carrying out residual frequency offset estimation, time delay estimation and initial phase estimation on the first type of signals to obtain a residual frequency offset estimation value, a time delay estimation value and an initial phase estimation value;
and determining the phase estimation value based on the residual frequency offset estimation value, the time delay estimation value and the initial phase estimation value.
Preferably, the performing residual frequency offset estimation on the first type of signal specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, and performing coherent accumulation on data contained in each symbol of the target second-class signal in real time to obtain a second-class sum data until the number of accumulated symbols reaches a second preset number;
and performing demodulation on all the second types and data, performing FFT operation on the second types and data of the second preset number after demodulation on the basis of FFT kernels of a third preset number of points to obtain values of the third preset number, performing modulus operation on all the values, and determining the estimated value of the residual frequency offset on the basis of the position corresponding to the maximum value of the modulus.
Preferably, the estimating the time delay of the first type of signal specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, and performing coherent accumulation on data belonging to the same frequency hopping point in each symbol of the target second-class signal in real time to obtain a third-class sum data until the number of accumulated symbols reaches a fourth preset number;
sequencing all third types and data in each symbol according to the size of a frequency hopping point, and performing FFT operation on the third types and data contained in each sequenced symbol once based on FFT kernels of a fifth preset number of points to obtain a value of the fifth preset number and perform modulus extraction;
and accumulating the moduli of the values of the same position in each symbol to obtain a fifth preset number of fourth types and data, and determining the time delay estimation value based on the position corresponding to the maximum fourth type and data.
Preferably, the initial phase estimation of the first type of signal specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, determining transmission information of each symbol in the target second-class signal, and performing demodulation on the target second-class signal;
and carrying out coherent accumulation on data contained in each symbol in the target second-class signal subjected to demodulation in real time until the number of accumulated symbols reaches a sixth preset number to obtain a fifth-class sum data, and determining the initial phase estimation value based on the fifth-class sum data.
Preferably, the determining the phase estimation value based on the residual frequency offset estimation value, the time delay estimation value and the initial phase estimation value specifically includes:
determining the phase estimate based on the following equation:
θi＝2πΔfi×(t+τ)+θ0
wherein, thetaiFor the phase estimate, Δ f, corresponding to the ith hopiIs the residual frequency offset estimation value corresponding to the ith frequency hopping point, t is the time corresponding to the ith frequency hopping point, τ is the time delay estimation value corresponding to the ith frequency hopping point, and θ0And the initial phase estimation value corresponding to the ith frequency hopping point is obtained.
In a second aspect, an embodiment of the present invention provides a demodulation apparatus based on a CFFH/DS system, including: a compensation module and an estimation module. Wherein the content of the first and second substances,
the compensation module is used for carrying out code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization;
the estimation module is used for respectively carrying out code bias estimation and phase estimation on the first type of signals and determining a code bias estimation value and a phase estimation value;
the compensation module is further configured to perform code offset compensation on the first type of signal based on the code offset estimation value, and perform phase compensation on the first type of signal based on the phase estimation value.
In a third aspect, an embodiment of the present invention provides an electronic device, including: memory, processor and computer program stored on the memory and executable on the processor, the processor implementing the steps of the demodulation method based on the CFFH/DS system according to the first aspect when executing the program.
In a fourth aspect, an embodiment of the present invention provides a non-transitory computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the CFFH/DS system-based demodulation method according to the first aspect.
The embodiment of the invention provides a demodulation method and a device based on a CFFH/DS system, wherein the method comprises the steps of firstly carrying out code offset compensation and phase compensation on a target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization; then, respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value; and finally, performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value. And in the demodulation stage, the real-time code offset compensation and the phase compensation of the signals are realized, and the error rate of demodulation is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a demodulation method based on a CFFH/DS system according to an embodiment of the present invention;
fig. 2(a) is a signal diagram of a signal transmitting end when there is a relative speed between the signal receiving end and the signal transmitting end of the CFFH/DS system in the embodiment of the present invention;
fig. 2(B) is a schematic signal diagram of a signal receiving end when there is a relative speed between the signal receiving end and the signal transmitting end of the CFFH/DS system in the embodiment of the present invention;
fig. 3 is a schematic diagram illustrating sampling of a first type of signal in a demodulation method based on a CFFH/DS system according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a demodulation apparatus based on a CFFH/DS system according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a complete structure of a demodulation apparatus based on a CFFH/DS system according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a demodulation method based on a CFFH/DS system, including:
s1, performing code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization;
s2, respectively carrying out code bias estimation and phase estimation on the first type of signals, and determining a code bias estimation value and a phase estimation value;
and S3, performing code offset compensation on the first class signals based on the code offset estimation value, and performing phase compensation on the first class signals based on the phase estimation value.
Specifically, in the demodulation method based on the CFFH/DS system provided in the embodiment of the present invention, the execution main body is a server, and the server may specifically be a computer server or a cloud server, which is not specifically limited in the embodiment of the present invention. Under the condition that the signal receiving end and the signal sending end of the CFFH/DS system have large dynamics, the signal receiving end of the CFFH/DS system is influenced by the fact that the period of the signal is stretched and shrunk in a time domain view, namely the period of the signal received by the signal receiving end is different from the period of the signal sent by the signal sending end due to the fact that the signal receiving end and the signal sending end have relative speeds. This leads to three problems, the first being that the frequency of the received signal changes, producing a frequency offset; the second problem is that the carrier period at the signal receiving end is changed; the third problem is that the spreading code period of direct sequence spreading is changed, causing code bias. Under the condition that the first-order change rate of the doppler is not zero, both the frequency offset and the code offset change in real time, so that the frequency offset and the code offset need to be estimated in real time. Fig. 2(a) is a schematic signal diagram of a signal transmitting end when a relative speed exists between the signal receiving end and the signal transmitting end of the CFFH/DS system in the embodiment of the present invention, and fig. 2(B) is a schematic signal diagram of the signal receiving end when a relative speed exists between the signal receiving end and the signal transmitting end of the CFFH/DS system in the embodiment of the present invention. As can be seen from comparison between fig. 2(a) and fig. 2(B), there is a relative velocity between the signal receiving end and the signal transmitting end, which causes a code offset and a phase offset between the signal received by the signal receiving end and the signal transmitted by the signal transmitting end. Therefore, the embodiment of the invention provides a demodulation method of a CFFH/DS system, aiming at carrying out code offset compensation and phase compensation on a target signal in a demodulation stage and ensuring the demodulation accuracy.
Step S1 is performed first. The target signal in step S1 is a signal subjected to frame synchronization, that is, the target signal is baseband data obtained after the target signal has undergone debounce, and also has undergone the stages of acquisition, tracking, frame synchronization, and the like, and the frequency offset and the time delay are compensated to some extent in the stages of acquisition, tracking, frame synchronization, and the like. Therefore, the target signal has an initial code offset estimation value and an initial phase estimation value, the code offset estimation value refers to an estimated value of a deviation between a local spreading code of the receiving end and a spreading code of a signal transmitted by the signal transmitting end, and the phase estimation value refers to an estimated value of a deviation between an actual phase of the target signal and an original phase of the signal transmitted by the phase transmitting end. The code offset compensation for the target signal may be implemented according to the initial code offset estimation value, for example, under the condition that the local spreading code is kept unchanged, if the code offset estimation value is positive, the actual sampling position of the target signal may be delayed, and if the code offset estimation value is negative, the actual sampling position of the target signal may be advanced, so as to implement the code offset compensation. After the code offset compensation, the spread spectrum code of the target signal is close to the spread spectrum code of the original signal sent by the signal sending end, and the subsequent phase compensation is not influenced. At this time, phase compensation of the target signal can be achieved based on the initial phase estimation value. For example, if the phase estimate is positive, the phase of the target signal may be decreased, and if the phase estimate is negative, the phase of the target signal may be increased to achieve phase compensation.
And carrying out code offset compensation and phase compensation on the target signal to obtain a first type of signal. However, since the first-order doppler change rate is not zero, the code offset and the phase offset may continue to occur during the transmission of the target signal, and therefore, the code offset estimation and the phase estimation of the first-class signal need to be performed in real time, i.e., step S2 is performed. And obtaining a code bias estimation value after code bias estimation is carried out, and obtaining a phase estimation value after phase estimation is carried out. The code offset estimation may first extract the first type of signal, search for the best extraction position, and determine the code offset estimation value according to the best extraction position. The best extraction position is usually determined by coherent accumulation of a certain symbol for data of one channel of signals corresponding to each extraction position, and taking a modulus for the accumulated value, wherein the extraction position corresponding to the maximum modulus is the best extraction position. The phase estimation may first perform residual frequency offset estimation, delay estimation, and initial phase estimation on the first type of signal, and then synthetically determine a phase estimation value according to respective estimation results.
Finally, step S3 is performed. According to the estimated code offset value and the estimated phase value obtained in step S2, code offset compensation and phase compensation are performed on the first type of signal, respectively, and the specific compensation manner is completely consistent with the manner of performing code offset compensation and phase compensation on the target signal in step S1, which is not described herein again in the embodiments of the present invention.
The demodulation method based on the CFFH/DS system provided by the embodiment of the invention comprises the steps of firstly carrying out code offset compensation and phase compensation on a target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization; then, respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value; and finally, performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value. And in the demodulation stage, the real-time code offset compensation and the phase compensation of the signals are realized, and the demodulation error rate is reduced.
On the basis of the foregoing embodiment, the demodulation method based on the CFFH/DS system provided in the embodiment of the present invention performs code offset estimation on the first-type signal, and specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data sampling rate of the second-class signals is one time of the chip rate;
carrying out coherent accumulation on data contained in each symbol of each path of the second-class signals in real time until the number of accumulated symbols reaches a first preset number to obtain a first-class sum data;
and taking a modulus of all the first class sum data, and determining the code bias estimated value based on the position corresponding to the first class sum data with the maximum modulus.
Specifically, when performing code offset estimation on a first type of signal, a plurality of second type of signals are first extracted from the first type of signal. Fig. 3 is a schematic diagram illustrating sampling of a first type of signal according to an embodiment of the present invention. The first kind of signals comprise Y frequency hopping points, each frequency hopping point is internally provided with Z chips, and the center frequency is fcAnd the frequency of each frequency hopping point is respectively
…，fc-3f0，fc-2f0，fc-f0，fc,fc+f0，fc+2f0，fc+3f0，…，
The frequency at the ith (i is more than or equal to 1 and less than or equal to Y) frequency hopping point in the embodiment of the invention can be recorded as fi，
The Data indicates rounding down, the chips in each frequency hopping point can be represented as Chip1, Chip2, … and Chip z, and each Chip can have G sampling points which are respectively marked as Data1, Data2, … and DataG. Let the data sampling rates of the target signal and the first type of signal be fsmp1Chip rate of RcThen there is fsmp1＝G*Rc. When multiple paths of second-type signals are extracted from the first-type signals, the extraction position of each path of second-type signal needs to be determined, as shown in fig. 3, N paths of second-type signals are set, and N extraction positions are set if the N paths of second-type signals are parallel signals. The interval between every two extraction positions is
I.e. the code bias search accuracy, TcIs one chip time. That is, the number of parallel paths N of the second type signal determines the accuracy of the code offset search
Meanwhile, when each path of the second-type signal is obtained, it is required to ensure that the data rate (i.e., the data sampling rate) of each path of the second-type signal is one-time chip rate. Let the data sampling rate of each path of the second type signal be fsmp2Chip rate of RcThen there is fsmp2＝Rc。
When code offset estimation is performed under low signal-to-noise ratio, accumulation of a plurality of symbols is often required to obtain a higher accuracy, so that a first preset number M of N second-type signals needs to be performed respectively1Coherent accumulation of one symbol, i.e. performing real-time coherent accumulation on each second type signal until a first preset number M is accumulated1After each symbol, a first type sum data is obtained. N paths of second class signals can be obtainedTo N first classes and data. Namely, for each path of second class signal, M is added1The data of each symbol are directly added to obtain a first type sum data. Then, taking the modulus of the N first-class sum data, and obtaining the maximum value of the modulus by a bubble sorting method, wherein the extraction position corresponding to the first-class sum data with the maximum modulus is the optimal extraction position, and the code offset estimation value is determined according to the optimal extraction position, so that one-time code offset estimation is completed. Then continuing to accumulate the next group of the first preset number M in each path of the second class signals1The symbols are subjected to code offset estimation.
When determining the code offset estimation value from the optimal extraction position, the code offset estimation value can be specifically determined by the following formula (1).
Where Δ C is the estimated value of code bias, N is the number of parallel-processed paths, i.e. the number of paths of the second type of signal, xmaxFor the best extraction position, the serial number corresponding to the best extraction position is usually used for characterizing, that is, all the extraction positions are numbered in sequence, and the serial number corresponding to the best extraction position. T iscIs a time of one chip,
to round up N/2.
On the basis of the foregoing embodiment, the demodulation method based on the CFFH/DS system provided in the embodiment of the present invention performs phase estimation on the first-type signal, and specifically includes:
respectively carrying out residual frequency offset estimation, time delay estimation and initial phase estimation on the first type of signals to obtain a residual frequency offset estimation value, a time delay estimation value and an initial phase estimation value;
and determining the phase estimation value based on the residual frequency offset estimation value, the time delay estimation value and the initial phase estimation value.
Specifically, in the embodiment of the present invention, since the phase offset of the signal is usually affected by the frequency offset, the time delay and the initial phase, in the embodiment of the present invention, first, the residual frequency offset estimation, the time delay estimation and the initial phase estimation may be performed on the first type of signal respectively, so as to obtain a residual frequency offset estimation value, a time delay estimation value and an initial phase estimation value, and then, the phase estimation value is determined by the following formula (2).
θi＝2πΔfi×(t+τ)+θ0(2)
Wherein, thetaiFor the phase estimate, Δ f, corresponding to the ith hopiThe residual frequency offset estimation value corresponding to the ith frequency hopping point is the frequency offset generated at the ith frequency hopping point corresponding to the relative speed of the signal receiving end and the signal sending end in executing receiving and sending actions, t is the time corresponding to the ith frequency hopping point, tau is the time delay estimation value corresponding to the ith frequency hopping point, and theta is0And the initial phase estimation value corresponding to the ith frequency hopping point, namely the initial phase difference between the signal receiving end and the signal transmitting end.
On the basis of the foregoing embodiment, the demodulation method based on the CFFH/DS system provided in the embodiment of the present invention performs residual frequency offset estimation on the first-type signal, and specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, and performing coherent accumulation on data contained in each symbol of the target second-class signal in real time to obtain a second-class sum data until the number of accumulated symbols reaches a second preset number;
and performing demodulation on all the second types and data, performing FFT operation on all the second types and data subjected to demodulation based on FFT kernels of a third preset number of points to obtain a third preset number of values, performing modulus operation on all the values, and determining the residual frequency offset estimation value based on the position corresponding to the maximum modulus value.
Specifically, in the embodiment of the present invention, when performing residual frequency offset estimation on the first type of signal, first, extraction is performed from the first type of signalAnd taking a plurality of second-class signals, wherein the data rate of the second-class signals is one time of the chip rate. And setting the number of the second-class signals as N, wherein the N second-class signals are parallel signals. Then, a target second-class signal is selected from the N paths of second-class signals, the target second-class signal can be selected according to needs, and in order to ensure the accuracy of the residual frequency offset estimation, in the embodiment of the invention, all the second-class signals can be sequenced according to the sequence of the extraction positions, and then the second-class signal in the N paths is selected
And taking the second-class signal as a target second-class signal. When the residual frequency offset estimation is carried out under the low signal-to-noise ratio, a higher residual frequency offset estimation precision can be obtained only by using a plurality of symbols, and the number of the symbols used in the residual frequency offset estimation is set as a second preset number M2With K data in each symbol, K being determined based on the sampling rate and the spreading code length, M2The setting may be performed as needed, and this is not particularly limited in the embodiment of the present invention. And performing real-time coherent accumulation on the target second-class signal, and performing coherent accumulation on K data contained in each symbol to obtain a second-class sum data. Coherent accumulation is the direct addition of the K data contained in each symbol, each symbol corresponding to a second type sum data. Thus, M can be obtained altogether2A second class and data.
Since the information transmitted on each symbol is modulated, M needs to be modulated2A second class and data are separately de-modulated, i.e. M2The second class and the data are squared separately. Then the M after modulation is removed2The second type and data are input to a third preset number L1L in FFT Kernel of points1FFT operation of the points to obtain L1Value of, to L1Each value is subjected to modulus taking, and the position l corresponding to the maximum value of the modulus is determined by using a bubble sorting methodmaxUsually characterised by the position-corresponding sequence number, i.e. L1The positions of the values are numbered in sequence, and the position with the maximum module corresponds to the number. Finally according to lmaxDetermining residual frequenciesAnd the offset estimation value is used for finishing one-time residual offset estimation. Then continuing to accumulate the next group of second preset number M in the target second type signal2And carrying out residual frequency offset estimation on each symbol. In the embodiment of the present invention, the residual frequency offset estimation value may be specifically determined by the following formula (3).
Wherein, Δ fiIs the residual frequency deviation estimated value, R, of the ith frequency hopping pointsIs the symbol rate, fcAt radio frequency, fiThe frequency at the ith hop point.
On the basis of the foregoing embodiment, the demodulation method based on the CFFH/DS system provided in the embodiment of the present invention performs delay estimation on the first type of signal, and specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, and performing coherent accumulation on data which belong to the same frequency hopping point in each symbol of the target second-class signal in real time to obtain a third-class sum data;
sequencing all third types and data in each symbol according to the size of a frequency hopping point, and performing FFT operation on all the sequenced third types and data based on FFT kernels of a fifth preset number of points to obtain a fifth preset number of values and modulus;
and accumulating the moduli of the values of the same position in each symbol to obtain a fifth preset number of fourth types and data, and determining the time delay estimation value based on the position corresponding to the maximum fourth type and data.
Specifically, in the embodiment of the present invention, when performing delay estimation on a first type of signal, multiple second type of signals are first extracted from the first type of signal, and a data rate of the second type of signal is one time of a chip rate. And setting the number of the second-class signals as N, wherein the N second-class signals are parallel signals. Then from N way to the second classThe target second-class signal is selected from the signals, the target second-class signal can be selected according to requirements, and in order to ensure the accuracy of time delay estimation, the second-class signal in N paths can be selected in the embodiment of the invention
And taking the second-class signal as a target second-class signal. When the time delay estimation is carried out under the low signal-to-noise ratio, a higher estimation correct rate can be obtained only by using a plurality of symbols, and the number of the symbols used in the time delay estimation is set as a fourth preset number M3. And carrying out coherent accumulation on the data belonging to the same frequency hopping point in each symbol of the target second-class signal to obtain a third-class sum data. Because the first type of signal comprises Y frequency hopping points, the target second type of signal also comprises Y frequency hopping points, so that each symbol has Y frequency hopping points, and for each symbol, all data at each frequency hopping point in the symbol are subjected to coherent accumulation to obtain a third type of sum data. Each symbol corresponds to Y third type sum data, each third type sum data represents one-hop information, and the target second type signal corresponds to M3× Y third classes and data.
And sequencing the Y third types and data in each symbol according to the size of the frequency hopping point, and specifically sequencing in an ascending order. Inputting the sorted Y third types and data into a fifth preset number L2L in FFT Kernel of points2FFT operation of the points to obtain L2And (4) taking values. Each symbol results in L2Obtaining M by taking values and obtaining the target second-class signal3×L2And (4) taking values. To M3×L2And taking the module of each value. Then, M is added3Coherent accumulation is carried out on the modulus of the values of the same position in each symbol to obtain L2A fourth class and data. The maximum fourth class and the position corresponding to the data are determined by using a bubble sorting method, and are generally characterized by a sequence number corresponding to the position, namely L2The positions of the fourth class and the data are numbered in sequence, and the position corresponding to the largest fourth class and the data is numbered. Finally, the time delay estimated value can be determined according to the maximum fourth class and the position corresponding to the data, and the method is completedOne time delay estimation is performed. Then continuing to accumulate the next group of the fourth preset number M in the target second type signal3And performing time delay estimation on each symbol.
On the basis of the foregoing embodiment, the demodulation method based on the CFFH/DS system provided in the embodiment of the present invention performs initial phase estimation on the first-type signal, and specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, determining transmission information of each symbol in the target second-class signal, and performing demodulation on the target second-class signal;
and carrying out coherent accumulation on data contained in each symbol in the target second-class signal subjected to demodulation in real time until the number of accumulated symbols reaches a sixth preset number to obtain a fifth-class sum data, and determining the initial phase estimation value based on the fifth-class sum data.
Specifically, in the embodiment of the present invention, when performing initial phase estimation on the first type of signal, first, multiple paths of second type of signals are extracted from the first type of signal, and a data rate of the second type of signals is one time of a chip rate. And setting the number of the second-class signals as N, wherein the N second-class signals are parallel signals. Then, a target second-class signal is selected from the N paths of second-class signals, the target second-class signal can be selected according to needs, and in order to ensure the accuracy of initial phase estimation, the embodiment of the invention can select the N paths of second-class signals
And taking the second-class signal as a target second-class signal.
And determining the transmission information of each symbol in the target second-class signal, performing coherent accumulation on each K data of the target signal once by taking the symbol as a unit because each symbol has K data, and if the real part of the value after the coherent accumulation is greater than zero, indicating the first information of the transmission information of the symbol, otherwise indicating that the transmission information of the symbol is the second information. The first information and the second information may be specifically represented as needed, for example, the first information is represented as 1, and the second information is represented as-1.
After the transmission information for each symbol in the target second type signal is determined, the target second type signal is unmodulated. When the initial phase estimation is performed under the condition of low signal-to-noise ratio, a higher estimation accuracy rate can be obtained only by using a plurality of symbols, and the number of the symbols used in the initial phase estimation is set as a sixth preset number M4. Carrying out real-time coherent accumulation on data contained in the target second-class signal subjected to demodulation until the number of accumulated symbols reaches M4A fifth class and data are obtained, which may be represented by a complex number a + b x j. The fifth class and data are then converted into the form of amplitude phase angle
Among them, there is formula (4).
Wherein, the initial phase estimation values of the carriers of the signal receiving end and the signal transmitting end
This completes one initial phase estimation. Then continuing to accumulate the next group of sixth preset number M in the target second type signal4Initial phase estimation is performed for each symbol.
On the basis of the above embodiment, in the embodiment of the present invention, a specific value of Y may be 64, a specific value of Z may be 16, a length of the spreading code may be 1024, that is, 1024 data are provided in each symbol, N may be 9, and a signal oversampling multiple may be 64. M1、M2、M3、M4May be 64 each, which is not particularly limited in the embodiments of the present invention.
As shown in fig. 4, on the basis of the above embodiments, an embodiment of the present invention provides a demodulation apparatus based on a CFFH/DS system, including: a compensation module 41 and an estimation module 42.
The compensation module 41 is configured to perform code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization;
the estimation module 42 is configured to perform code offset estimation and phase estimation on the first type of signal, respectively, and determine a code offset estimation value and a phase estimation value;
the compensation module 41 is further configured to perform code offset compensation on the first type of signal based on the code offset estimation value, and perform phase compensation on the first type of signal based on the phase estimation value.
Specifically, the functions of the modules in the demodulation apparatus based on the CFFH/DS system provided in the embodiment of the present invention correspond to the operation flows of the steps in the embodiments of the methods one to one, and the implementation effects are also consistent.
As shown in fig. 5, on the basis of the above embodiment, the compensation module may specifically include a code offset compensation module 411 and a phase compensation module 412. The code offset compensation module 411 is configured to perform code offset compensation on the target signal, and the phase compensation module 412 is configured to perform phase compensation on the target signal, where the target signal may be input to the code offset compensation module 411 first, and the code offset compensation module 411 is connected to the phase compensation module 412. The estimation module may specifically include a code offset estimation module 421 and a phase estimation module, and the phase estimation module may further include a residual frequency offset estimation submodule 4221, a delay estimation submodule 4222, an initial phase estimation submodule 4223, an information identification submodule 4224, and a phase conversion submodule 4225. The phase compensation module 412 may be connected to the code offset estimation module 421, the code offset estimation module 421 is connected to each sub-module in the phase estimation module, and may also be connected to each sub-module in the phase estimation module, and each sub-module in the phase estimation module is connected to the code offset estimation module 411. The code offset estimation module 421 is connected to the code offset compensation module 411, and the phase estimation module is connected to the phase compensation module. In the phase estimation module, a residual frequency offset estimation submodule 4221, a delay estimation submodule 4222 and an initial phase estimation submodule 4223 are all connected with a phase conversion submodule 4225, and the phase conversion submodule 4225 is connected with a phase compensation module. The initial phase estimation submodule 4223 is connected to the code offset estimation module 421 through an information identification submodule 4224. The target signal is output by the information identifier 4224 after being subjected to code offset compensation and phase compensation. This is not particularly limited in the embodiment of the present invention, and only one case is shown in fig. 5.
As shown in fig. 6, on the basis of the above embodiment, an embodiment of the present invention provides an electronic device, including: a processor (processor)601, a memory (memory)602, a communication Interface (Communications Interface)603, and a communication bus 604; wherein the content of the first and second substances,
the processor 601, the memory 602, and the communication interface 603 complete communication with each other through the communication bus 604. The memory 602 stores program instructions executable by the processor 601, and the processor 601 is configured to call the program instructions in the memory 602 to perform the methods provided by the above-mentioned method embodiments, for example, including: performing code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization; respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value; and performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value.
It should be noted that, when being implemented specifically, the electronic device in this embodiment may be a server, a PC, or another device, as long as the structure includes the processor 601, the communication interface 603, the memory 602, and the communication bus 604 shown in fig. 6, where the processor 601, the communication interface 603, and the memory 602 complete mutual communication through the communication bus 604, and the processor 601 may call a logic instruction in the memory 602 to execute the above method. The embodiment does not limit the specific implementation form of the electronic device.
The logic instructions in memory 602 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone article of manufacture. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Further, embodiments of the present invention disclose a computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, which when executed by a computer, the computer is capable of performing the methods provided by the above-mentioned method embodiments, for example, comprising: performing code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization; respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value; and performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value.
On the basis of the foregoing embodiments, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, the computer program being implemented to perform the method provided by the foregoing embodiments when executed by a processor, and the method includes: performing code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization; respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value; and performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A demodulation method based on CFFH/DS system is characterized by comprising the following steps:
performing code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization;
respectively carrying out code bias estimation and phase estimation on the first type of signals to determine a code bias estimation value and a phase estimation value;
and performing code offset compensation on the first type of signals based on the code offset estimation value, and performing phase compensation on the first type of signals based on the phase estimation value.
2. The CFFH/DS system-based demodulation method of claim 1, wherein the performing code offset estimation on the first type of signal specifically includes:
extracting a plurality of second-class signals from the first-class signals, wherein the data sampling rate of the second-class signals is one time of the chip rate;
carrying out coherent accumulation on data contained in each symbol of each path of the second-class signals in real time until the number of accumulated symbols reaches a first preset number to obtain a first-class sum data;
and taking a modulus of all the first class sum data, and determining the code bias estimated value based on the extraction position corresponding to the first class sum data with the maximum modulus.
3. The CFFH/DS system based demodulation method of claim 1, wherein the phase estimation of said first type of signal comprises:
respectively carrying out residual frequency offset estimation, time delay estimation and initial phase estimation on the first type of signals to obtain a residual frequency offset estimation value, a time delay estimation value and an initial phase estimation value;
and determining the phase estimation value based on the residual frequency offset estimation value, the time delay estimation value and the initial phase estimation value.
4. The CFFH/DS-based demodulation method of claim 3, wherein the residual frequency offset estimation of the first type of signal specifically comprises:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, and performing coherent accumulation on data contained in each symbol of the target second-class signal in real time to obtain a second-class sum data until the number of accumulated symbols reaches a second preset number;
and performing demodulation on all the second types and data, performing FFT operation on the second types and data of the second preset number after demodulation on the basis of FFT kernels of a third preset number of points to obtain values of the third preset number, performing modulus operation on all the values, and determining the estimated value of the residual frequency offset on the basis of the position corresponding to the maximum value of the modulus.
5. The CFFH/DS-based demodulation method of claim 3, wherein the time delay estimation of the first type of signal specifically comprises:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, and performing coherent accumulation on data belonging to the same frequency hopping point in each symbol of the target second-class signal in real time to obtain a third-class sum data until the number of accumulated symbols reaches a fourth preset number;
sequencing all third types and data in each symbol according to the size of a frequency hopping point, and performing FFT operation on the third types and data contained in each sequenced symbol based on FFT kernels of a fifth preset number of points, wherein each symbol obtains values of the fifth preset number and takes a modulus;
and accumulating the moduli of the values of the same position in each symbol to obtain a fifth preset number of fourth types and data, and determining the time delay estimation value based on the position corresponding to the maximum fourth type and data.
6. The CFFH/DS-based demodulation method of claim 3, wherein said initial phase estimation of said first type of signal comprises:
extracting a plurality of second-class signals from the first-class signals, wherein the data rate of the second-class signals is one time of the chip rate;
selecting a target second-class signal from all second-class signals, determining transmission information of each symbol in the target second-class signal, and performing demodulation on the target second-class signal;
and carrying out coherent accumulation on data contained in each symbol in the target second-class signal subjected to demodulation in real time until the number of accumulated symbols reaches a sixth preset number to obtain a fifth-class sum data, and determining the initial phase estimation value based on the fifth-class sum data.
7. The CFFH/DS-based demodulation method of claim 3, wherein said determining the phase estimate based on the residual frequency offset estimate, the time delay estimate, and the initial phase estimate comprises:
determining the phase estimate based on the following equation:
θi＝2πΔfi×(t+τ)+θ0
wherein, thetaiFor the phase estimate, Δ f, corresponding to the ith hopiIs the residual frequency offset estimation value corresponding to the ith frequency hopping point, t is the time corresponding to the ith frequency hopping point, τ is the time delay estimation value corresponding to the ith frequency hopping point, and θ0And the initial phase estimation value corresponding to the ith frequency hopping point is obtained.
8. A demodulation apparatus based on a CFFH/DS system, comprising:
the compensation module is used for carrying out code offset compensation and phase compensation on the target signal to obtain a first type of signal; the target signal is a signal subjected to frame synchronization;
the estimation module is used for respectively carrying out code bias estimation and phase estimation on the first type of signals and determining a code bias estimation value and a phase estimation value;
the compensation module is further configured to perform code offset compensation on the first type of signal based on the code offset estimation value, and perform phase compensation on the first type of signal based on the phase estimation value.
9. An electronic device, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the CFFH/DS system based demodulation method according to any one of claims 1 to 7 when executing said program.
10. A non-transitory computer readable storage medium, on which a computer program is stored, wherein the computer program, when being executed by a processor, implements the steps of the CFFH/DS system based demodulation method according to any one of claims 1 to 7.
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