CN111584498B - Method for forming three-dimensional structure in CMOS chip - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
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- 239000011229 interlayer Substances 0.000 claims abstract description 18
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H01L27/11807—CMOS gate arrays
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Abstract
The invention discloses a method for forming a three-dimensional structure in a CMOS chip, which comprises the following steps: forming a ring-shaped protruded monocrystalline silicon seed layer region on a silicon substrate; forming a first layer of CMOS transistors in the non-seed layer region; forming a first interlayer dielectric layer and exposing the monocrystalline silicon seed layer region; covering a polysilicon layer on the first interlayer dielectric layer, and enabling the surfaces of the first interlayer dielectric layer and the second interlayer dielectric layer to be flush; heating to melt and recrystallize the polycrystalline silicon layer, and converting the polycrystalline silicon into monocrystalline silicon by using monocrystalline silicon surrounding the polycrystalline silicon to form a monocrystalline silicon layer; forming a second layer of CMOS transistors on the monocrystalline silicon layer; forming a second interlayer dielectric layer; interconnections between the first layer of CMOS transistors and the second layer of CMOS transistors are formed. The invention can increase the density of CMOS transistor in chip, reduce the needed interconnection length, improve the performance of product and reduce the cost of single chip.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for forming a three-dimensional structure in a CMOS chip.
Background
With the development of semiconductor very large scale integrated circuits, the prior art processes have approached physical limits. Driven by the purpose of further miniaturization and multi-functionalization of electronic products, other new technologies, new materials, and new technologies are being explored. One of the limitations of two dimensions of the chip is to remove the chip structure and develop the chip structure into three dimensions. The existing methods for manufacturing three-dimensional structures can be roughly divided into two methods, one is to stack silicon wafers by a bonding technology to realize a metal interconnection structure on a three-dimensional layer; and the other method is to manufacture a plurality of layers of CMOS transistors in a chip to realize a three-dimensional structure in the chip.
The existing technology for forming a three-dimensional structure by bonding silicon wafers generally needs to be completed through the following steps: bonding (Bonding) of the silicon chip, grinding and thinning (Grinding) of the back of the silicon chip, wet etching (Wet) of the back of the silicon chip, planarization (CMP) of the back of the silicon chip and other processes on the back of the silicon chip. Among them, other processes on the back refer to various featured processes such as backside illumination (BSI) process, and bonding of silicon wafer to planarization process is a measure to be taken in almost all three-dimensional stacking processes.
During back grinding thinning, the silicon wafer is thinned from about 775 microns (12 "silicon wafer) to the desired thickness of the device, typically a few microns. The thinned and removed part is ground into chips or corroded by a wet method, so that the chip is difficult to recycle, and the silicon chip is wasted in resource utilization. Meanwhile, the back grinding process has many problems including generation of a large amount of particles and impurities, easy cracking of a silicon wafer, difficulty in controlling of Total Thickness Variation (TTV), and the like. These problems affect the yield of the subsequent process, thereby affecting the efficiency of the process and the quality of the product.
The technical method for realizing the three-dimensional structure in the chip is not commonly used in the current production line. The main problem is that the on-chip three-dimensional structure requires the formation of multiple layers of single crystal silicon layers to fabricate the CMOS device. However, the conventional methods, such as the single crystal silicon epitaxy, are time-consuming, difficult to control the process at the interface between the dielectric and the single crystal silicon, and prone to defect formation, and thus are rarely used.
Laser crystallization technology is currently mainly applied to Thin Film Transistors (TFTs). By the melting-recrystallization process in a short time caused by laser, a polycrystalline and single crystal film with good quality can be obtained.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a method for forming a three-dimensional structure in a CMOS chip.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a method for forming a three-dimensional structure in a CMOS chip comprises the following steps:
the method comprises the following steps: providing a silicon substrate and removing part of the silicon substrate material, and forming a monocrystalline silicon seed layer region of an annular protrusion on the silicon substrate;
step two: forming a first layer of CMOS transistors on the silicon substrate in a non-seed layer region outside the monocrystalline silicon seed layer region;
step three: forming a first interlayer dielectric layer covering the first CMOS transistor on the silicon substrate, and exposing the monocrystalline silicon seed layer region;
step four: covering a polysilicon layer on the first interlayer dielectric layer, and carrying out a planarization process to enable the surface of the polysilicon layer to be flush with the surface of the monocrystalline silicon seed layer region;
step five: heating to melt and recrystallize the polycrystalline silicon layer, and converting the polycrystalline silicon into monocrystalline silicon by using monocrystalline silicon surrounding the polycrystalline silicon to form a monocrystalline silicon layer;
step six: forming a second layer of CMOS transistors on the single crystal silicon layer;
step seven: forming a second interlayer dielectric layer, and covering the second CMOS transistor layer;
step eight: and forming interconnection between the first layer of CMOS transistors and the second layer of CMOS transistors.
Further, in the first step, before forming the single crystal silicon seed layer region of the annular protrusion, the method further includes: and forming shallow trench isolation on the silicon substrate, and forming a first protective layer on the silicon substrate after the shallow trench isolation is formed.
Further, in the first step, a plurality of annular protrusions are connected to form the monocrystalline silicon seed layer region of the planar network structure.
Further, in the second step, before forming the first layer of CMOS transistors, the method further includes: and forming a second protective layer on the silicon substrate including the monocrystalline silicon seed layer region.
Further, when forming the first layer of CMOS transistors in the second step and/or forming the second layer of CMOS transistors in the sixth step, the method includes: well injection, gate oxide deposition, polysilicon deposition, photoetching and etching, polycrystal gate side wall deposition and etching, source and drain injection and rapid annealing.
Further, in the second step, after the first layer of CMOS transistors is formed, the method further includes: and removing the polysilicon, the oxide layer and the nitride layer materials remained on the side wall of the monocrystalline silicon seed layer region.
Further, in the fifth step, laser heating is adopted to melt and recrystallize the polycrystalline silicon layer.
Furthermore, when laser heating is carried out, a photomask is adopted, so that the size of a laser irradiation area is matched with the ring shape of the monocrystalline silicon seed layer area.
Further, in the eighth step, the interconnection between the first layer of CMOS transistors and the second layer of CMOS transistors is formed by forming contact holes on the first layer of CMOS transistors and the second layer of CMOS transistors, respectively, and connecting the contact holes to the metal layer formed on the second layer of interlayer dielectric layer.
Further, the diameter or the side length of the annular protrusion is 1 to 10 micrometers.
The invention has the following advantages:
(1) Compared with the CMOS traditional process, the invention integrates two layers of CMOS transistor structures in a single chip, so that the number of transistors in the same area is more, and the effects of saving the chip area and reducing the cost are achieved. Meanwhile, due to the design of the transistors on the upper layer and the lower layer, structural forms which cannot be achieved by a single-layer transistor can be obtained, and therefore product capability is improved.
(2) Compared with a conventional three-dimensional structure formed by bonding two silicon wafers, the novel design of the monolithic multilayer transistor only needs one silicon wafer, so that the cost is reduced, and the process steps are simplified; on the other hand, the electrical interconnection distance between the transistors is shorter, the parasitic of the routing is reduced, and the product performance is improved.
(3) Compared with a monolithic internal three-dimensional structure formed by silicon wafer epitaxy, the method for forming the monocrystalline silicon layer by using the laser crystallization technology saves time and cost, is mature in process and easy to control, reduces the defect level in the monocrystalline silicon layer and improves the product performance.
Drawings
Fig. 1-9 are schematic process steps of a method for forming a three-dimensional structure in a CMOS chip according to a preferred embodiment of the invention.
Detailed Description
The core idea of the invention is to combine the laser crystallization technology into the CMOS process, provide a brand-new technical method for forming the three-dimensional structure in the CMOS chip, and realize the three-dimensional stacking of the CMOS structure in the chip by a feasible and reliable technological method, thereby increasing the density of the CMOS transistor in the chip, reducing the required interconnection length, improving the performance of the product and reducing the cost of a single chip.
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following embodiments of the present invention, please refer to fig. 1-9, and fig. 1-9 are process steps of a method for forming a three-dimensional structure in a CMOS chip according to a preferred embodiment of the present invention. As shown in fig. 1 to 9, a method for forming a three-dimensional structure in a CMOS chip of the present invention includes the following steps:
the method comprises the following steps: providing a silicon substrate and removing part of the silicon substrate material, and forming a monocrystalline silicon seed layer region of an annular protrusion on the silicon substrate.
Please refer to fig. 1. The invention provides a process for forming a three-dimensional structure in a CMOS chip, which is started after a Shallow Trench Isolation (STI) process of a normal CMOS process is carried out on a silicon chip substrate. At this time, the structure of the silicon wafer substrate includes a silicon substrate layer 100, a surface oxide layer (first protective layer) 200 and an STI region 300.
Please refer to fig. 2. And photoetching and etching processes are carried out on the silicon substrate layer 100 to form the structure of the monocrystalline silicon seed layer region 101. Then, an oxide layer (second protective layer) 201 is grown on the entire device surface.
In the photolithography process, it is necessary to control the shape of the single crystal silicon seed layer region 101 to be annular or to form the single crystal silicon seed layer region 101 (in a plan view) having a planar network structure by connecting a plurality of annular protrusions. The line width (line CD) of the structure of the monocrystalline silicon seed layer region 101 can be made as small as possible so as to reduce the occupation of the area of the silicon substrate layer 100; the spacing (space CD) of the structure of the single crystal silicon seed layer region 101 (i.e., the diameter or side length of each annular protrusion) needs to be within a certain range to meet the process requirements of the subsequent laser crystallization. For example, the pitch of the structures of the single crystal silicon seed layer region 101 is not less than 1 micron and not more than 10 microns. If the space CD is too large, polysilicon may be generated in a region far away from the seed layer structure; conversely, if the space CD is too small, the subsequent polysilicon area will be smaller than the minimum coverage area achievable by the laser.
During the etching process, the original oxide layer 200 is removed, and the silicon substrate layer 100 is continuously etched, so that the monocrystalline silicon seed layer region 101 reaches a desired height, for example, a preferred height is 250-350 nm, and most preferably about 300nm. Other heights are possible, however, particularly in view of the thickness requirements of the single crystal silicon substrate for subsequent CMOS devices. In this process, due to the existence of STI, the etching process needs to simultaneously etch the STI region, so that the depth of the STI region is reduced, as shown by the STI region 301 in fig. 2.
Step two: and forming a first layer of CMOS transistors on the silicon substrate in the non-seed layer region outside the monocrystalline silicon seed layer region.
Please refer to fig. 3. Conventional CMOS transistor process steps are performed on the silicon substrate layer 100 in areas other than the seed layer. Such as well implantation, gate oxide deposition, polysilicon deposition, photolithography and etching, poly sidewall deposition and etching, source drain implantation and rapid annealing steps, etc., to form CMOS transistor structure 400 in the non-seed layer region. The process steps related to these transistors are substantially the same as those of the current large-scale mass production process, and only some optimization needs to be performed on the sidewalls of the monocrystalline silicon seed layer region 101, such as etching to remove the polysilicon, oxide layer, nitride layer, etc. remaining on the sidewalls of the seed layer.
Step three: and forming a first interlayer dielectric layer covering the first CMOS transistor on the silicon substrate, and exposing the monocrystalline silicon seed layer area.
Please refer to fig. 4. An oxide layer is deposited as a first interlayer dielectric (ILD) 500. A second polysilicon layer thickness is required to be reserved between the ILD layer 500 and the seed layer 101, i.e. the seed layer 101 is required to be higher than the ILD layer 500. The specific height difference is determined depending on the desired thickness of the single crystal silicon layer, and for example, the height difference is preferably 50 to 150nm, and more preferably about 100nm. But other heights are possible.
The deposition process at this step tends to fill better performing processes, such as HARP, FCVD, etc., because of the need to fill the height differences caused by the CMOS transistor step.
Step four: and covering a polycrystalline silicon layer on the first interlayer dielectric layer, and carrying out a planarization process to enable the surface of the polycrystalline silicon layer to be flush with the surface of the monocrystalline silicon seed layer region.
Please refer to fig. 5. A polysilicon layer 600 is deposited and a silicon CMP process is performed such that the polysilicon layer 600 and the seed layer 101 reach the same height. Since the monocrystalline silicon seed layer regions 101 are arranged in a ring shape or a net shape, a structure in which polycrystalline silicon and monocrystalline silicon are alternated is formed when viewed from a cross-sectional view. The thickness of the finally formed polysilicon layer 600 is the thickness of the finally required single crystal silicon layer, and is determined according to the specific requirement, for example, the preferable thickness is 50-150 nm, and the most preferable thickness is about 100nm. But other heights are possible.
Step five: heating to melt and recrystallize the polycrystalline silicon layer, and converting the polycrystalline silicon into single crystal silicon by using single crystal silicon surrounding the polycrystalline silicon to form a single crystal silicon layer.
Please refer to fig. 6. A laser heating recrystallization process is performed to convert a region of the polycrystalline silicon layer 600 into single crystal silicon through melting and recrystallization processes, and finally the single crystal silicon layer 700 is formed.
In this step, when performing the laser heating recrystallization process, a specific photomask is required to be used so that the size of the laser irradiation region matches the shape of the monocrystalline silicon seed layer region 101. For example, assuming that the shape of the monocrystalline silicon seed layer region 101 is a ring, the self-line CD is 500nm, and the space CD is 5 μm in both X/Y directions (i.e., the region of the polycrystalline silicon layer 600 enclosed by the monocrystalline silicon seed layer region 101 is a rectangle of 5 μm × 5 μm), the laser mask can be designed to be a rectangle of 5.25 μm in both X/Y directions. When laser crystallization is carried out, the area covered by the laser completely covers the polysilicon area, and the edge of the laser is in the seed layer area. Thereby ensuring that when melting occurs, the periphery of the melting area is monocrystalline silicon, and the monocrystalline silicon grows when recrystallization occurs.
Upon laser irradiation, a melted region 601 is formed. After the laser crystallization process is performed on all desired regions, the polycrystalline silicon is converted into single crystal silicon, thereby forming a single crystal silicon layer 700, as shown in fig. 7.
Step six: a second layer of CMOS transistors is formed on the single crystal silicon layer.
Please refer to fig. 8. An oxide layer 202 is grown on the single crystal silicon layer 700 as a protective layer, and then conventional CMOS transistor processing steps, such as well implantation, gate oxide deposition, polysilicon deposition, photolithography, etching, poly-gate sidewall deposition, etching, source-drain implantation, rapid annealing, etc., are performed to form a second layer CMOS transistor structure 401. These steps are substantially identical to conventional CMOS transistor steps, and there is no concern about the effects of ion implantation, etching, etc. processes on the underlying CMOS transistors due to the blocking of the ILD layer.
Step seven: and forming a second interlayer dielectric layer to cover the second CMOS transistor layer.
Please refer to fig. 9. A dielectric layer is deposited as a second ILD501. This step is substantially identical to conventional ILD process steps such as filling using HARP, FCVD processes, protection using BSG, BPSG, NSG processes, planarization using CMP processes, etc.
Step eight: and forming interconnection between the first layer of CMOS transistors and the second layer of CMOS transistors.
Please refer to fig. 9. A contact hole (CT) process is performed to connect the upper and lower CMOS transistors 400, 401 through the contact hole to the circuit (metal layer) 800 formed on the second interlayer dielectric layer 501. The contact hole process herein entails etching a portion of the contact hole to the first layer CMOS transistor structure on the silicon substrate layer 100.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that any equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for forming a three-dimensional structure in a CMOS chip is characterized by comprising the following steps:
the method comprises the following steps: providing a silicon substrate and removing part of the silicon substrate material, and forming a monocrystalline silicon seed layer region of an annular protrusion on the silicon substrate;
step two: forming a first layer of CMOS transistors on the silicon substrate in a non-seed layer region outside the monocrystalline silicon seed layer region;
step three: forming a first interlayer dielectric layer covering the first CMOS transistor on the silicon substrate, and exposing the monocrystalline silicon seed layer region;
step four: covering a polysilicon layer on the first interlayer dielectric layer, and carrying out a planarization process to enable the surface of the polysilicon layer to be flush with the surface of the monocrystalline silicon seed layer region;
step five: heating to melt and recrystallize the polycrystalline silicon layer, and converting the polycrystalline silicon into monocrystalline silicon by using monocrystalline silicon surrounding the polycrystalline silicon to form a monocrystalline silicon layer;
step six: forming a second layer of CMOS transistors on the monocrystalline silicon layer;
step seven: forming a second interlayer dielectric layer, and covering the second CMOS transistor layer;
step eight: and forming interconnection between the first layer of CMOS transistors and the second layer of CMOS transistors.
2. The method of claim 1, wherein before forming the ring-shaped raised single-crystal-silicon seed layer region in the first step, the method further comprises: and forming shallow trench isolation on the silicon substrate, and forming a first protective layer on the silicon substrate after the shallow trench isolation is formed.
3. The method of claim 1, wherein in step one, a plurality of annular protrusions are connected to form a planar network of regions of the single crystal silicon seed layer.
4. The method of claim 1, wherein in step two, before forming the first layer of CMOS transistors, further comprising: and forming a second protective layer on the silicon substrate including the monocrystalline silicon seed layer region.
5. The method for forming a three-dimensional structure in a CMOS chip according to claim 1, wherein the step of forming the first layer of CMOS transistors in the step two and/or the step of forming the second layer of CMOS transistors in the step six comprises: well injection, gate oxide deposition, polysilicon deposition, photoetching and etching, polycrystal gate side wall deposition and etching, source and drain injection and rapid annealing.
6. The method for forming a three-dimensional structure in a CMOS chip as claimed in claim 5, wherein in the second step, after forming the first layer of CMOS transistors, the method further comprises: and removing the polysilicon, the oxide layer and the nitride layer materials remained on the side wall of the monocrystalline silicon seed layer region.
7. The method of claim 1, wherein in step five, the polysilicon layer is melted and recrystallized by laser heating.
8. The method of claim 7, wherein the laser heating is performed by using a mask to match the size of the laser irradiation region with the ring shape of the single crystal silicon seed layer region.
9. The method of claim 1, wherein in step eight, the interconnection between the first layer of CMOS transistors and the second layer of CMOS transistors is formed by forming contact holes in the first layer of CMOS transistors and the second layer of CMOS transistors, respectively, and connecting the metal layer formed on the second layer of interlayer dielectric layer.
10. The method of claim 1, wherein the annular protrusion has a diameter or side length of 1 to 10 μm.
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