CN111584457A - TSV-based nested magnetic core inductor - Google Patents
TSV-based nested magnetic core inductor Download PDFInfo
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- CN111584457A CN111584457A CN202010255600.8A CN202010255600A CN111584457A CN 111584457 A CN111584457 A CN 111584457A CN 202010255600 A CN202010255600 A CN 202010255600A CN 111584457 A CN111584457 A CN 111584457A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 105
- 239000002184 metal Substances 0.000 claims abstract description 105
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 81
- 239000010703 silicon Substances 0.000 claims abstract description 81
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 63
- 239000002356 single layer Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0086—Printed inductances on semiconductor substrate
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Coils Or Transformers For Communication (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a TSV (through silicon via) -based nested magnetic core inductor which comprises a silicon substrate layer, wherein the upper surface and the lower surface of the silicon substrate layer are respectively provided with a dielectric layer, a strip-shaped magnetic core is arranged in the silicon substrate layer, the periphery of the magnetic core is concentrically nested with two spiral inductors along the length direction of the magnetic core, and the two spiral inductors are respectively formed by connecting metal interconnection lines respectively positioned in the two dielectric layers and metal columns in silicon through holes which vertically penetrate through the silicon substrate layer. According to the TSV-based nested magnetic core inductor, the nested structure of the two spiral inductors can adapt to the existing integrated circuit process, so that the occupied area of the inductor is halved, and the density of the inductor is doubled; in addition, the inductance value of unit area is effectively improved and the inductance value is adjustable by arranging the magnetic core, so that the utilization rate of the inductor is greatly improved.
Description
Technical Field
The invention belongs to the technical field of three-dimensional integrated circuits, and particularly relates to a TSV (through silicon via) -based nested magnetic core inductor.
Background
Through silicon via technology is a key technology for implementing three-dimensional integrated circuits. In three-dimensional integrated circuits, through-silicon vias are used to fabricate integrated passive devices, in addition to vertical interconnection between chips, and three-dimensional inductors are one of their applications. Inductors are considered important components in analog, radio frequency, and microwave circuits, such as low noise amplifiers, power amplifiers, filters, oscillators, impedance matching networks, and DC-DC converters. The traditional two-dimensional planar spiral inductor has high loss, difficult improvement of quality factor and large occupied area, and is difficult to meet the requirements of high-integration integrated circuits. The three-dimensional spiral inductor based on the TSV has higher inductance density and smaller occupied area, and can effectively solve the problem faced by a two-dimensional inductor. The general three-dimensional spiral inductor is mostly of a single-layer structure, and the inductance value needs to be increased by increasing the number of turns of the coil or the height of the TSV, which results in larger chip area and occupied space volume, and is disadvantageous to a high-concentration integrated circuit.
Disclosure of Invention
The invention aims to provide a TSV (through silicon via) -based nested magnetic core inductor, which solves the problem that the inductance density of the existing inductor is low.
The technical scheme adopted by the invention is as follows: the utility model provides a nested magnetic core inductor based on TSV, includes the silicon substrate layer, and the upper and lower surface of silicon substrate layer respectively is provided with a dielectric layer, is provided with banding magnetic core in the silicon substrate layer, and the periphery of magnetic core has two spiral inductors along its length direction concentric nestification, and two spiral inductors are formed by the metal interconnect line that is located two dielectric layers respectively and the metal post in the silicon through-hole that passes the silicon substrate layer from top to bottom connected.
The present invention is also characterized in that,
the dielectric layer arranged on the upper surface of the silicon substrate layer is a top dielectric layer, and the dielectric layer arranged on the lower surface of the silicon substrate layer is a bottom dielectric layer.
The through silicon via has been seted up two respectively from top to bottom in the silicon substrate layer of its length direction both sides at the magnetic core, the magnetic core is every side and its through silicon via who is close to one are the second through silicon via, the magnetic core is every side and its through silicon via who keeps away from one are first through silicon via, the upper and lower both ends of first through silicon via and the upper and lower both ends of second through silicon via all outwards extend to in the top dielectric layer and the bottom dielectric layer respectively, the upper and lower both ends of second through silicon via respectively in the top dielectric layer with the bottom dielectric layer extend the length that the upper and lower both ends of first through silicon via extended in the top dielectric layer and the bottom dielectric layer respectively.
The metal column comprises a first metal column filled in the first silicon through hole and a second metal column filled in the second silicon through hole, and insulating layers are arranged between the first metal column and the silicon substrate layer and between the second metal column and the silicon substrate layer.
The insulating layer, the top dielectric layer and the bottom dielectric layer are made of one of silicon dioxide, silicon nitride or silicon oxynitride.
The two spiral inductors comprise a first spiral inductor and a second spiral inductor close to the magnetic core, the first spiral inductor comprises a plurality of top first metal interconnection lines arranged in a top dielectric layer in parallel and a plurality of bottom first metal interconnection lines arranged in a bottom dielectric layer in parallel, the bottom first metal interconnection lines and the top first metal interconnection lines form an included angle in a horizontal plane, and the heads and the tails of the two adjacent top first metal interconnection lines and the bottom first metal interconnection lines are connected sequentially through a first metal column; the second spiral inductor comprises a plurality of top second metal interconnection lines arranged in a top dielectric layer in parallel and a plurality of bottom second metal interconnection lines arranged in a bottom dielectric layer in parallel, the bottom second metal interconnection lines and the top second metal interconnection lines form an included angle in a horizontal plane, and the head and the tail of two adjacent top second metal interconnection lines and the head and the tail of two adjacent bottom second metal interconnection lines are connected through second metal columns in sequence.
The top first metal interconnection line, the bottom first metal interconnection line, the top second metal interconnection line, the bottom second metal interconnection line, the first metal pillar and the second metal pillar are all made of one of copper or aluminum.
The two ends of the first spiral inductor are respectively provided with a first input end and a first output end, and the two ends of the second spiral inductor are respectively provided with a second input end and a second output end.
The invention has the beneficial effects that: according to the TSV-based nested magnetic core inductor, the nested structure of the two spiral inductors can adapt to the existing integrated circuit process, so that the occupied area of the inductor is halved, and the density of the inductor is doubled; in addition, the inductance value of unit area is effectively improved and the inductance value is adjustable by arranging the magnetic core, so that the utilization rate of the inductor is greatly improved.
Drawings
FIG. 1 is a top view of a TSV based nested core inductor of the present invention with the silicon substrate layer and dielectric layer removed;
fig. 2 is a cross-sectional view of a TSV based nested core inductor of the present invention.
In the figure, 1, a silicon substrate layer, 2, a magnetic core, 3, a top dielectric layer, 4, a bottom dielectric layer, 5, a second through silicon via, 6, a first through silicon via, 7, a first metal pillar, 8, a second metal pillar, 9, an insulating layer, 10, a top first metal interconnection line, 11, a bottom first metal interconnection line, 12, a top second metal interconnection line, 13, a bottom second metal interconnection line, 14, a first input terminal, 15, a first output terminal, 16, a second input terminal, 17, and a second output terminal.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention provides a TSV (through silicon via) -based nested magnetic core inductor which comprises a silicon substrate layer 1, wherein the upper surface and the lower surface of the silicon substrate layer 1 are respectively provided with a dielectric layer, the dielectric layer arranged on the upper surface of the silicon substrate layer 1 is a top dielectric layer 3, the dielectric layer arranged on the lower surface of the silicon substrate layer 1 is a bottom dielectric layer 4, a strip-shaped magnetic core 2 is arranged in the silicon substrate layer 1, the periphery of the magnetic core 2 is concentrically nested with two spiral inductors along the length direction of the magnetic core, and the two spiral inductors are respectively formed by connecting metal interconnection lines positioned in the two dielectric layers and metal columns in silicon through holes penetrating through the silicon substrate layer from top to bottom.
Wherein, the through-silicon via has respectively seted up two in the silicon substrate layer 1 of magnetic core 2 along its length direction both sides from top to bottom, 2 every sides of magnetic core are the second through-silicon via 5 rather than being close to a through-silicon via of a column, 2 every sides of magnetic core are first through-silicon via 6 rather than keeping away from a through-silicon via of a column, the upper and lower both ends of first through-silicon via 6 and the upper and lower both ends of second through-silicon via 5 are all outwards extended respectively in top dielectric layer 3 and bottom dielectric layer 4, the length that the upper and lower both ends of second through-silicon via 5 extended respectively in top dielectric layer 3 and bottom dielectric layer 4 all is not more than the upper and lower both ends of first through-silicon via 6 and extends in top dielectric layer 3 and bottom. The metal columns comprise first metal columns 7 and second metal columns 8, the first metal columns 7 are filled in the first silicon through holes 6, the second metal columns 8 are filled in the second silicon through holes 5, and insulating layers 9 are arranged between the first metal columns 7 and the silicon substrate layer 1 and between the second metal columns 8 and the silicon substrate layer 1. The insulating layer 9, the top dielectric layer 3 and the bottom dielectric layer 4 are made of one of insulating materials such as silicon dioxide, silicon nitride or silicon oxynitride.
The two spiral inductors comprise a first spiral inductor and a second spiral inductor close to the magnetic core 2, the first spiral inductor comprises a plurality of top first metal interconnection lines 10 arranged in the top dielectric layer 3 in parallel and a plurality of bottom first metal interconnection lines 11 arranged in the bottom dielectric layer 4 in parallel, the bottom first metal interconnection lines 11 and the top first metal interconnection lines 10 form an included angle in the horizontal plane, and the heads and the tails of two adjacent top first metal interconnection lines 10 and bottom first metal interconnection lines 11 are connected sequentially through the first metal columns 7; the second spiral inductor comprises a plurality of top second metal interconnection lines 12 arranged in the top dielectric layer 3 in parallel and a plurality of bottom second metal interconnection lines 13 arranged in the bottom dielectric layer 4 in parallel, the bottom second metal interconnection lines 13 and the top second metal interconnection lines 12 form an included angle in the horizontal plane, and the heads and the tails of two adjacent top second metal interconnection lines 12 and bottom second metal interconnection lines 13 are connected in sequence through the second metal columns 8. The top first metal interconnection line 10, the bottom first metal interconnection line 11, the top second metal interconnection line 12, the bottom second metal interconnection line 13, the first metal pillar 7 and the second metal pillar 8 are all made of one of conductive materials such as copper or aluminum.
The two ends of the first spiral inductor are respectively provided with a first input end 14 and a first output end 15, the first input end 14 and the first output end 15 are respectively connected to the top of the last row in the left column of the first metal posts 7 and the top of the first row in the right column of the first metal posts 7, the two ends of the second spiral inductor are respectively provided with a second input end 16 and a second output end 17, and the second input end 16 and the second output end 17 are respectively connected to the top of the last row in the left column of the second metal posts 8 and the top of the first row in the right column of the second metal posts 8.
During operation, as shown in fig. 1, a second spiral inductor formed by connecting a bottom second metal interconnection line 13, a second metal column 8, a top second metal interconnection line 12, a second metal column 8 and a bottom second metal interconnection line 13 … is nested in a first spiral inductor formed by connecting a bottom first metal interconnection line 11, a first metal column 7, a top first metal interconnection line 10, a first metal column 7 and a bottom first metal interconnection line 11 …, so that the occupied area of the inductor is reduced by half; and through adding the electric current at first input 14 or second input 16, the electric field that inductance coils produced arouses the change of magnetic core 2 magnetic permeability, and then arouses the change of first spiral inductor and second spiral inductor inductance value, can carry out quantitative adjustment to the inductance value according to actual demand.
Through the mode, the TSV-based nested magnetic core inductor can adapt to the existing integrated circuit process through the nested structure of the two spiral inductors, so that the occupied area of the inductor is halved, and the density of the inductor is doubled, which means that the area of a chip used by the two spiral inductors is only the occupied area of a traditional single-layer spiral inductor; in addition, the inductance value of unit area is effectively improved and the inductance value is adjustable by arranging the magnetic core, so that the utilization rate of the inductor is greatly improved.
Claims (8)
1. The utility model provides a nested magnetic core inductor based on TSV, its characterized in that includes silicon substrate layer (1), and the upper and lower surface of silicon substrate layer (1) respectively is provided with a dielectric layer, is provided with banding magnetic core (2) in the silicon substrate layer (1), and the periphery of magnetic core (2) has two spiral inductors along its length direction concentric nestification, and two spiral inductors are formed by the metal interconnect line that is located two dielectric layers respectively and the metal post in the silicon through-hole that passes the silicon substrate layer from top to bottom connecting.
2. The TSV-based nested core inductor of claim 1, wherein the dielectric layer disposed on the upper surface of the silicon substrate layer (1) is a top dielectric layer (3) and the dielectric layer disposed on the lower surface of the silicon substrate layer (1) is a bottom dielectric layer (4).
3. The TSV-based nested core inductor of claim 2, two columns are respectively arranged on the upper portion and the lower portion of the silicon through hole in a silicon substrate layer (1) of a magnetic core (2) along two sides of the length direction of the magnetic core, each side of the magnetic core (2) and the silicon through holes close to one column are second silicon through holes (5), each side of the magnetic core (2) and the silicon through holes far away from one column are first silicon through holes (6), the upper ends and the lower ends of the first silicon through holes (6) and the upper ends and the lower ends of the second silicon through holes (5) respectively extend outwards into a top dielectric layer (3) and a bottom dielectric layer (4), and the lengths of the upper ends and the lower ends of the second silicon through holes (5) respectively extending in the top dielectric layer (3) and the bottom dielectric layer (4) are not more than the lengths of the upper ends and the lower ends of the first silicon through holes (6) respectively extending in the top dielectric layer (.
4. A TSV-based nested core inductor according to claim 3, wherein the metal posts comprise a first metal post (7) filled in the first through silicon via (6) and a second metal post (8) filled in the second through silicon via (5), and insulating layers (9) are arranged between the first metal post (7) and the silicon substrate layer (1) and between the second metal post (8) and the silicon substrate layer (1).
5. A TSV-based nested core inductor according to claim 4, wherein the insulating layer (9), the top dielectric layer (3) and the bottom dielectric layer (4) are each made of one of silicon dioxide, silicon nitride or silicon oxynitride.
6. A TSV-based nested magnetic core inductor according to claim 4, wherein the two spiral inductors comprise a first spiral inductor and a second spiral inductor close to the magnetic core (2), the first spiral inductor comprises a plurality of top first metal interconnection lines (10) arranged in parallel in the top dielectric layer (3) and a plurality of bottom first metal interconnection lines (11) arranged in parallel in the bottom dielectric layer (4), the bottom first metal interconnection lines (11) and the top first metal interconnection lines (10) form an included angle in a horizontal plane, and the head and the tail of two adjacent top first metal interconnection lines (10) and bottom first metal interconnection lines (11) are connected sequentially through the first metal columns (7); the second spiral inductor comprises a plurality of top second metal interconnection lines (12) arranged in the top dielectric layer (3) in parallel and a plurality of bottom second metal interconnection lines (13) arranged in the bottom dielectric layer (4) in parallel, the bottom second metal interconnection lines (13) and the top second metal interconnection lines (12) form an included angle in a horizontal plane, and the heads and the tails of two adjacent top second metal interconnection lines (12) and bottom second metal interconnection lines (13) are connected sequentially through second metal columns (8).
7. A TSV-based nested magnetic core inductor according to claim 6, wherein the top first metal interconnect line (10), the bottom first metal interconnect line (11), the top second metal interconnect line (12), the bottom second metal interconnect line (13), the first metal pillar (7) and the second metal pillar (8) are all made of one of copper or aluminum.
8. A TSV-based nested core inductor according to claim 6, wherein the first spiral inductor has a first input terminal (14) and a first output terminal (15) at each end, and the second spiral inductor has a second input terminal (16) and a second output terminal (17) at each end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010255600.8A CN111584457B (en) | 2020-04-02 | 2020-04-02 | Nested magnetic core inductor based on TSV |
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| CN202010255600.8A CN111584457B (en) | 2020-04-02 | 2020-04-02 | Nested magnetic core inductor based on TSV |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113410033A (en) * | 2021-05-31 | 2021-09-17 | 西安理工大学 | TSV-based full-symmetry three-dimensional transformer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1610112A (en) * | 2003-10-24 | 2005-04-27 | 罗姆股份有限公司 | Semiconductor device |
| JP2007150024A (en) * | 2005-11-29 | 2007-06-14 | Seiko Epson Corp | Electronic substrate, manufacturing method thereof and electronic equipment |
| TW201331964A (en) * | 2012-01-19 | 2013-08-01 | Ind Tech Res Inst | Inductor structure |
| CN109755224A (en) * | 2018-11-27 | 2019-05-14 | 西安电子科技大学 | A kind of compact nested induction structure and preparation method thereof based on through silicon via |
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- 2020-04-02 CN CN202010255600.8A patent/CN111584457B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1610112A (en) * | 2003-10-24 | 2005-04-27 | 罗姆股份有限公司 | Semiconductor device |
| JP2007150024A (en) * | 2005-11-29 | 2007-06-14 | Seiko Epson Corp | Electronic substrate, manufacturing method thereof and electronic equipment |
| TW201331964A (en) * | 2012-01-19 | 2013-08-01 | Ind Tech Res Inst | Inductor structure |
| CN109755224A (en) * | 2018-11-27 | 2019-05-14 | 西安电子科技大学 | A kind of compact nested induction structure and preparation method thereof based on through silicon via |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113410033A (en) * | 2021-05-31 | 2021-09-17 | 西安理工大学 | TSV-based full-symmetry three-dimensional transformer |
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