CN111584421A - Interconnection structure and forming method thereof - Google Patents
Interconnection structure and forming method thereof Download PDFInfo
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- CN111584421A CN111584421A CN201910116088.6A CN201910116088A CN111584421A CN 111584421 A CN111584421 A CN 111584421A CN 201910116088 A CN201910116088 A CN 201910116088A CN 111584421 A CN111584421 A CN 111584421A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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Abstract
The invention provides a forming method of an interconnection structure, which comprises the following steps: providing a substrate, and forming an auxiliary layer with a reverse filling groove on the substrate; depositing a back filling material in the back filling groove; removing the contact part of the auxiliary layer and the back filling material to form a film groove; depositing a thin film layer on the side wall of the thin film groove; and removing the back filling material to form the interconnection trench. The forming method of the interconnection structure adopted by the invention is simple, and the interconnection structure manufactured by the method has higher alignment precision with the metal wire or the semiconductor device. In addition, the invention also provides an interconnection structure. Compared with the prior art, the interconnection structure provided by the invention solves the problems that in the prior art, when the size of a semiconductor device is smaller and smaller, the possibility of misalignment between a through hole in the interconnection structure and a metal wire or the semiconductor device is higher, and short circuit, opening or other problems can be caused by the misalignment.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an interconnection structure and a forming method thereof.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced multiple IC generations, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per unit of chip area) generally increases, while the geometry (i.e., the smallest component that can be fabricated using a fabrication process) decreases.
As the semiconductor industry moves to nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from fabrication and design have led to the development of multilayer (or three-dimensional) integrated devices. A multilayer device may include a plurality of interconnect layers, each interconnect layer including one or more wires interconnected with wires from other interconnect layers by vias. However, as scaling continues, vias become smaller and wires become smaller. Thus, it becomes more challenging to form vias to their desired conductive lines from different interconnect layers and to align the vias with the desired conductive lines.
In semiconductor processing, integrated circuit patterns may be defined on a substrate using a photolithographic process. Dual damascene processes are used to form multi-level copper interconnects including vertical interconnect vias/contacts and horizontal interconnect metal lines. During the dual damascene process, a plug fill material is employed to fill in the via (or contact) and then the material is polished back. However, the vias (or contacts) are defined by different photolithography processes and may cause misalignment between the underlying metal lines and the vias. In particular, as semiconductor technology rapidly advances, the feature sizes of semiconductors become smaller and smaller, and the possibility of misalignment of vias in interconnect structures with metal lines or other semiconductor devices, which may lead to shorts, openings, or other problems, increases. In addition, in the prior art, a spacer (spacer) is usually used to define the pitch or width of the via holes of the interconnect structure to prevent short circuit. The interconnection structure manufactured by the method has a high possibility of misalignment between the through hole and the metal wire or other semiconductor devices.
As in patent document No. 201810149531.5, an interconnect structure, a method of manufacturing the same, and an electronic device including such an interconnect structure are disclosed. According to an embodiment, an interconnect structure may include: a first interconnect line at a first height including at least a first portion extending in a first direction; a second interconnection line at a second height higher than the first height, including at least a second portion extending in a second direction crossing the first direction; and a via plug disposed between the first portion of the first interconnect line and the second portion of the second interconnect line for electrically connecting the first interconnect line and the second interconnect line, wherein the via plug includes a first pair of sidewalls extending substantially parallel to opposing sidewalls of the first portion, respectively, and a second pair of sidewalls extending substantially parallel to opposing sidewalls of the second portion, respectively.
However, in the interconnect structure disclosed in the above patent document, the via plug may have a non-uniform gap between the first pair of sidewalls and the second pair of sidewalls, and the alignment accuracy between the interconnect structure and the electronic device is not high, which may cause a short circuit, an opening, or other problems between the electronic device and the interconnect structure.
Disclosure of Invention
The invention aims to provide an interconnection structure and a forming method thereof, which solve the problems that in the prior art, as the size of a semiconductor component is smaller and smaller, the possibility of misalignment between a through hole in the interconnection structure and a semiconductor device is higher, and the misalignment can cause short circuit, opening or other problems.
The invention provides a forming method of an interconnection structure, which comprises the following steps: providing a substrate, and forming an auxiliary layer with a reverse filling groove on the substrate; depositing a back filling material in the back filling groove; removing the contact part of the auxiliary layer and the back filling material to form a film groove; depositing a thin film layer on the side wall of the thin film groove; and removing the back filling material to form the interconnection trench.
By adopting the technical scheme, the auxiliary layer with the reverse filling groove is formed in the substrate, the reverse filling material is deposited in the reverse filling groove, and the reverse filling material has a memory function, so that the patterns of the semiconductor device or the metal wire connected with the interconnection structure can be memorized, and a self-aligned interconnection structure matched with the profile of the semiconductor device or the metal wire to be connected with the interconnection structure can be formed in the subsequent process.
According to another embodiment of the present invention, an auxiliary layer having a backfill trench formed on a substrate, comprises: depositing an auxiliary layer on the substrate; and etching the auxiliary layer to form a back-filled trench.
According to another embodiment of the present invention, the auxiliary layer includes a dielectric layer and an oxide film layer, one side of the dielectric layer is in contact with the substrate, and the oxide film layer is disposed on a side of the dielectric layer away from the substrate.
According to another embodiment of the present invention, before removing the portion of the auxiliary layer contacting the backfill material, the method further comprises: and removing the oxide film layer.
According to another embodiment of the present invention, the method further comprises, while depositing the backfill material in the backfill trench: depositing an underfill material on the side of the auxiliary layer away from the substrate;
before removing the part of the auxiliary layer contacting with the backfill material, the method further comprises the following steps: and removing the back filling material on the side of the auxiliary layer far away from the substrate.
According to another embodiment of the present invention, before removing the backfill material, the method further comprises: etching the dielectric layer; or etching the dielectric layer and the backfill material.
According to another embodiment of the present invention, removing a portion of the auxiliary layer in contact with the backfill material includes: etching the auxiliary layer, and removing the part of the auxiliary layer, which is in contact with the back filling material, to form a thin film groove; or photoetching the back filling material, and removing the part of the back filling material, which is in contact with the auxiliary layer, to form a film groove; and etching the auxiliary layer, removing the part of the auxiliary layer, which is in contact with the back filling material, photoetching the back filling material, and removing the part of the back filling material, which is in contact with the auxiliary layer, to form a film groove.
According to another embodiment of the present invention, L1 ═ L2+ L3+ L4;
wherein, L1 is the width of the film trench in the substrate length direction, L2 is the width of the backfill material after removing the contact part of the auxiliary layer and the backfill material, and L3 and L4 are the widths of the film layers on both sides of the film trench in the substrate length direction, respectively.
According to another embodiment of the present invention, the dielectric layer is made of amorphous silicon doped with boron, and the backfill material is undoped amorphous silicon.
The invention also provides an interconnection structure, and the interconnection structure is manufactured based on the formation method of the interconnection structure.
The invention has the beneficial effects that:
the invention provides a forming method of an interconnection structure, which comprises the following steps: providing a substrate, and forming an auxiliary layer with a reverse filling groove on the substrate; depositing a back filling material in the back filling groove; removing the contact part of the auxiliary layer and the back filling material to form a film groove; depositing a thin film layer on the side wall of the thin film groove; and removing the back filling material to form the interconnection trench. By forming an auxiliary layer with an anti-filling groove in the substrate and depositing anti-filling material in the anti-filling groove, the anti-filling material has a memory function, so that the patterns of the semiconductor devices or metal wires connected with the interconnection structure can be memorized, and a self-aligned interconnection structure matched with the profile of the semiconductor devices or the metal wires to be connected with the interconnection structure can be formed subsequently.
In addition, the invention also provides an interconnection structure. Compared with the prior art, the interconnection structure provided by the invention solves the problems that in the prior art, when the size of a semiconductor device is smaller and smaller, the possibility of misalignment between a through hole in the interconnection structure and a metal wire or the semiconductor device is higher, and short circuit, opening or other problems can be caused by the misalignment.
Drawings
Fig. 1 is a flowchart illustrating a method for forming an interconnect structure according to an embodiment of the invention;
FIGS. 2a-12a are schematic side views of a process flow for fabricating an interconnect structure according to a second embodiment of the present invention;
fig. 2b-12b are schematic top views corresponding to fig. 2a-12a, respectively, illustrating a process flow for fabricating an interconnect structure according to a second embodiment of the present invention.
Reference numerals:
1: a substrate; 2: an auxiliary layer; 21: a dielectric layer; 22: oxidizing the film layer; 3: reversely filling the groove; 4: back-filling material; 5: a thin film trench; 6: a thin film layer; 7: an interconnection trench; 8: an interconnect structure.
Detailed Description
The technical solutions of the present invention are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or through an intermediate medium, or both elements may be interconnected. The meaning of the above terms in the present invention can be specifically understood by those of ordinary skill in the art.
In order to solve the problem that the misalignment between the through holes in the interconnection structure and the semiconductor device is more likely to occur when the size of the semiconductor component is smaller and smaller in the prior art, and the misalignment can cause short circuit, opening or other problems.
As shown in fig. 1, the present invention provides a method for forming an interconnect structure, comprising the steps of:
step S11: providing a substrate, and forming an auxiliary layer with a reverse filling groove on the substrate.
Specifically, as shown in fig. 3a and 3b, a substrate 1 is provided, and an auxiliary layer 2 having a backfill trench 3 is formed on the substrate 1. The backfill trench 3 on the substrate 1 is used for depositing a backfill material 4 in the next step, and the backfill material 4 has a memory function, so that patterns of semiconductor devices or metal lines connected with the interconnect structure manufactured by the interconnect structure forming method provided by the embodiment can be memorized, and the interconnect structure matched with the patterns can be precisely etched in the next step. The substrate 1 is made of a semiconductor material, the substrate 1 has a two-layer structure as shown in fig. 3a and 3b, the material of a layer remote from the auxiliary layer 2 may be silicon nitride, silicon oxide, or the like, and the material of a layer between the auxiliary layer 2 and a layer remote from the auxiliary layer 2 may be silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or the like. The material of the substrate 1 may be selected according to actual needs, and this embodiment is not limited to this.
Further, an auxiliary layer 2 having a backfill trench 3 is formed on the substrate 1, comprising: as shown in fig. 2a and 2b, an auxiliary layer 2 is deposited on a substrate 1; as shown in fig. 3a and 3b, the auxiliary layer 2 is etched to form a back-filled trench 3. Specifically, an auxiliary layer 2 may be deposited on the substrate 1, and then the auxiliary layer 2 is etched to form the auxiliary layer 2 with the inversely filled trenches 3.
It will be appreciated that in practice it is possible to select an already etched auxiliary layer 2 with a back-filled trench 3, the auxiliary layer 2 being provided on the substrate 1 and then carrying out the subsequent etching operation. Or selecting the auxiliary layer 2 tiled on the substrate 1, etching the auxiliary layer 2 to form the back-filled trench 3, and then performing the following etching operation. The selection is specifically performed according to actual needs, and this embodiment is not particularly limited in this respect.
Still further, as shown in fig. 2a, 2b, 3a, and 3b, the auxiliary layer 2 may include a dielectric layer 21 and an oxide film layer 22. The dielectric layer 21 is in contact with the substrate 1, and the oxide film layer 22 is arranged on one side of the dielectric layer 21 far away from the substrate 1. The material of the dielectric layer 21 may be amorphous silicon doped with dopant particles, or silicon nitride or silicon oxide doped with dopant particles, and the dopant particles may be phosphorus, arsenic, boron, or the like. The oxide film layer 22 may be specifically silicon oxide, silicon nitride, or the like. The materials of the dielectric layer 21 and the oxide film layer 22 are specifically selected according to actual needs, and this embodiment is not particularly limited in this respect.
Step S12: depositing an underfill material in the underfill trench.
Specifically, as shown in fig. 6a and 6b, the backfill material 4 is deposited in the backfill trench 3. The backfill material 4 has a memory function, and can remember the pattern of the semiconductor device or the metal line connected with the interconnection structure manufactured by the method for forming the interconnection structure provided by the embodiment, so that the interconnection structure matched with the pattern can be precisely etched in the next step without depending on a spacer to define the width of the groove of the interconnection structure.
Further, depositing the backfill material 4 in the backfill trench 3 can be further decomposed into the following steps:
step S121: depositing an underfill material on a side of the auxiliary layer away from the substrate, and depositing the underfill material in the underfill trench.
Specifically, as shown in fig. 4a and 4b, the backfill material 4 is deposited on the side of the auxiliary layer 2 away from the substrate 1, and the backfill material 4 is deposited in the backfill trench 3. I.e. depositing the backfill material 4 both over the auxiliary layer 2 and within the backfill trenches 3, as shown in fig. 4a, results in a higher backfill material 4 than the auxiliary layer 2, as shown in fig. 4 a.
Further, as described above, the auxiliary layer 2 may include the dielectric layer 21 and the oxide film layer 22. Therefore, when depositing the backfill material 4 on the side of the auxiliary layer 2 away from the substrate 1 and depositing the backfill material 4 in the backfill trench 3, the backfill material 4 may be deposited on the oxide film layer 22 on the side of the auxiliary layer 2 away from the substrate 1 and then depositing the backfill material 4 in the backfill trench 3.
Step S122: and depositing an anti-filling material on one side of the etching auxiliary layer far away from the substrate until the side is approximately flush with the anti-filling material in the anti-filling groove.
Specifically, the side of the etching auxiliary layer 2 away from the substrate 1 deposits the backfill material 4 to be approximately flush with the backfill material 4 in the backfill trench 3. As described in the previous step S121, the backfill material 4 is deposited both over the auxiliary layer 2 and in the backfill trenches 3, resulting in a higher backfill material 4 than the auxiliary layer 2 as shown in fig. 4 a. Therefore, in this step, as shown in fig. 5a and 5b, the backfill material 4 is deposited by etching the side of the auxiliary layer 2 away from the substrate 1 to be approximately flush with the backfill material 4 in the backfill trench 3. It should be understood that when the etching assistant layer 2 is deposited with the backfill material 4 on the side away from the substrate of the substrate 1 until the etch assistant layer is approximately flush with the backfill material 4 in the backfill trench 3, the amorphous silicon planarization process may be adopted, and the method process of this embodiment is not limited thereto, as long as the deposition backfill material 4 on the side away from the substrate of the assistant layer 2 is etched until the etch assistant layer is approximately flush with the backfill material 4 in the backfill trench 3, which is not specifically limited in this embodiment.
Further, as described above, the auxiliary layer 2 may include the dielectric layer 21 and the oxide film layer 22. Therefore, when the etching auxiliary layer 2 is away from the substrate of the substrate 1 and the backfill material 4 is deposited until the etching auxiliary layer is approximately flush with the backfill material 4 in the backfill trench 3, the oxide film layer 22 deposited on the side of the etching auxiliary layer 2 away from the substrate 1 can be removed first, and then the etching auxiliary layer 2 is away from the substrate of the substrate 1 and the backfill material 4 is deposited until the etching auxiliary layer is approximately flush with the backfill material 4 in the backfill trench 3. Alternatively, the backfill material 4 deposited on the side of the auxiliary layer 2 away from the substrate 1 is etched until the backfill material 4 is approximately flush with the backfill material 4 in the backfill trench 3, and then the oxide film 22 deposited on the side of the auxiliary layer 2 away from the substrate 1 is removed.
Step S123: and depositing an anti-filling material on one side of the etching auxiliary layer far away from the substrate until the side is approximately flush with the anti-filling material in the anti-filling groove.
Specifically, as shown in fig. 6a and 6b, the backfill material 4 is deposited on the side of the etch assisting layer 2 away from the substrate 1 to be flush with the backfill material 4 in the backfill trench 3. As described above, the etch assisting layer 2 is etched on the side away from the substrate 1 to deposit the backfill material 4 to be approximately flush with the backfill material 4 in the backfill trench 3, and at this step, the backfill material 4 deposited on the assisting layer 2 is further etched to be flush with the backfill material 4 in the backfill trench 3.
Further, as described above, the auxiliary layer 2 may include the dielectric layer 21 and the oxide film layer 22. Therefore, in step S123: and depositing the back filling material 4 on the side of the etching auxiliary layer 2 away from the substrate 1, and removing the oxide film layer 22 deposited on the side of the etching auxiliary layer 2 away from the substrate 1 until the side is flush with the back filling material 4 in the back filling groove 3. Specifically, which step is removed before step S123, which is not specifically limited in this embodiment as the case may be.
Step S13: and removing the contact part of the auxiliary layer and the backfill material to form a film groove.
Specifically, as shown in fig. 7a and 7b, the portion of the auxiliary layer 2 in contact with the backfill material 4 is removed to form the thin film trench 5. The thin film trenches 5 formed in this step are used for the subsequent formation of interconnect trenches parallel and juxtaposed to each other.
It should be understood that the process flow of forming the thin film trench 5 by removing the portion of the auxiliary layer 2 in contact with the backfill material 4 may be the process flow shown in fig. 4a, 5a, 6a, and 7a, or the process flow shown in fig. 11a and 7 a.
Specifically, the process flow of removing the portion of the auxiliary layer 2 in contact with the backfill material 4 to form the thin film trench 5 may be as shown in fig. 4a, 5a, 6a, and 7 a: firstly depositing a back filling material 4 above the auxiliary layer 2 and in the back filling groove 3, then carrying out a planarization operation on the back filling material 4 deposited above the auxiliary layer 2, so that the back filling material 4 is deposited on one side of the auxiliary layer 2 away from the substrate 1 until the side is approximately level with the back filling material 4 in the back filling groove 3, then etching the side of the auxiliary layer 2 away from the substrate 1 to deposit the back filling material 4 until the side is level with the back filling material 4 in the back filling groove 3, and then removing the contact part of the auxiliary layer 2 and the back filling material 4 to form a film groove 5. In this successive step, the width of the last formed film trench 5 coincides with the width of the starting backfill trench 3. While the auxiliary layer 2 and the underfill material 4 deposited in the underfill trench 3 are etched during the formation of the thin film trench 5, more precisely, the auxiliary layer 2 and the underfill material 4 deposited in the underfill trench 3 are etched to half of the original width during the formation of the thin film trench 5, thereby forming the subsequent thin film trench 5.
In addition to the flows shown in fig. 4a, 4b, 5a, 5b, 6a, 6b, 7a, and 7b, fig. 11a, 11b, and 7a may also be referred to, that is, the width of the backfill trench 3 in fig. 11a is half of the backfill trench 3 in fig. 4a, the thickness of the backfill material 4 deposited in the backfill trench 3 in fig. 11a is also half of the thickness of the backfill material 4 deposited in the backfill trench 3 in fig. 4a, and the backfill material 4 deposited in the backfill trench 3 in fig. 11a is flush with the auxiliary layer 2. Then, the following etching is performed, and at this time, it is only necessary to etch the auxiliary layer 2 so that the width of the thin film trench 5 formed by the etched auxiliary layer 2 is consistent with the width of the thin film trench 5 formed by the process shown in fig. 4a, 5a, 6a, and 7 a.
Similarly, according to the same principle as the process shown in fig. 11a and fig. 7a, the back filling material 4 may be only photo-etched, and the portion of the back filling material 4 contacting the auxiliary layer 2 is removed to form the thin film trench 5, which is not described herein again.
Step S14: and depositing a thin film layer on the side wall of the thin film groove.
Specifically, as shown in fig. 8a and 8b, the thin film layer 6 is deposited on the side wall of the thin film trench 5. After the thin film layers 6 are deposited on the side walls of the thin film trenches 5, the distance between the thin film layers 6 is the width of the interconnection trench to be subsequently formed. And it is ensured that the width between the film layers 6 is uniform along the length extension of the auxiliary layer 2.
Further, L1 ═ L2+ L3+ L4; l1 is the width of the thin film trench 5 in the longitudinal direction of the substrate 1, L2 is the width of the backfill material 4 in the longitudinal direction of the substrate 1 after removing the portion of the auxiliary layer 2 in contact with the backfill material 4, and L3 and L4 are the widths of the thin film layers 6 on both sides of the thin film trench 5 in the longitudinal direction of the substrate 1, respectively. It should be understood that, preferably, in the present embodiment, L3 ═ L4.
Specifically, as shown in fig. 4a, 4b, 7a, 7b, 8a, and 8b, L1 is the width of the thin film trench 5 in the longitudinal direction of the substrate 1, L2 is the width of the backfill material 4 after removing the portion of the auxiliary layer 2 in contact with the backfill material 4 in the longitudinal direction of the substrate 1, wherein the width of the backfill material 4 after removing the portion of the auxiliary layer 2 in contact with the backfill material 4 in the longitudinal direction of the substrate 1 is equal to the gap width between the thin film layers 6, L3 and L4 are the widths of the thin film layers 6 on both sides of the thin film trench 5 in the longitudinal direction of the substrate 1, and L1 is L2+ L3+ L4, preferably, in this embodiment, L3 is L4.
The material of the thin film layer 6 may be silicon, silicon nitride, aluminum oxide, or the like, and is specifically selected according to actual needs, and this embodiment is not particularly limited thereto.
Step S15: and removing the back filling material to form the interconnection trench.
Specifically, as shown in fig. 10a and 10b, the backfill material 4 is removed to form the interconnection trench 7. After removing the underfill material 4, interconnection trenches 7 with uniform width are formed between the thin film layers 6 on both sides of the underfill material 4 and are parallel to each other. Compared with the prior art, the forming method of the interconnection structure provided by the embodiment effectively solves the problem that when the size of the semiconductor component is smaller and smaller, the possibility that the through hole in the interconnection structure is misaligned with the semiconductor device is higher, and the misalignment can cause short circuit, opening or other problems.
Further, step S15 can also be decomposed into the following steps:
step S151: after step S14, the underfill material between the thin film layers is directly removed to form the interconnect trench.
Specifically, as shown in fig. 12a and 12b, after step S14, the backfill material 4 between the thin film layers 6 is directly removed to form the interconnection trench 7.
Step S152: after step S14, the underfill material and the auxiliary layer are etched, and then the underfill material is removed to form the interconnect trench.
Specifically, as shown in fig. 9a and 9b, after step S14, the backfill material 4 and the auxiliary layer 2 are etched, and then the backfill material 4 is removed to form the interconnection trench 7. Further, as shown in fig. 9a, the backfill material 4 and the auxiliary layer 2 are etched to a half of the original thickness, and then the backfill material 4 is removed to form the interconnection trench 7.
Step S153: after step S14, the underfill material is removed, and the auxiliary layer is etched to form the interconnect trench.
Specifically, as shown in fig. 12a, 12b, 10a, and 10b, the backfill material 4 is removed, and then the auxiliary layer 2 is etched to form the interconnection trench 7.
The embodiment provides a forming method of an interconnection structure, which comprises the following steps: providing a substrate, and forming an auxiliary layer with a reverse filling groove on the substrate; depositing a back filling material in the back filling groove; removing the contact part of the auxiliary layer and the back filling material to form a film groove; depositing a thin film layer on the side wall of the thin film groove; and removing the back filling material to form the interconnection trench. Compared with the prior art, the forming method of the interconnection structure adopted by the embodiment does not depend on a spacer to define the width of the interconnection trench, but forms an auxiliary layer with an inverse filling trench in the substrate, deposits an inverse filling material in the inverse filling trench, and the inverse filling material has a memory function, so that the patterns of the semiconductor devices or the metal lines connected with the interconnection structure can be memorized, and the interconnection structure which is matched with the contours of the semiconductor devices or the metal lines to be connected with the interconnection structure and has higher alignment precision can be formed subsequently.
Further, in order to solve the problem in the prior art that as the size of the semiconductor component is smaller and smaller, the possibility of misalignment between the via in the interconnect structure and the semiconductor device is higher, and the misalignment may cause short circuit, opening or other problems, the present embodiment provides an interconnect structure that is manufactured based on the foregoing method for forming the interconnect structure.
Further, the manufacturing process flow diagram of the interconnection structure is as follows:
as shown in fig. 2a and 2b, an auxiliary layer 2 having a backfill trench 3 is formed on a substrate 1, including: an auxiliary layer 2 is deposited on the substrate 1.
The auxiliary layer 2 is etched as shown in fig. 3a, 3b to form a back-filled trench 3. Specifically, an auxiliary layer 2 may be deposited on the substrate 1, and then the auxiliary layer 2 is etched to form the auxiliary layer 2 with the inversely filled trenches 3.
Specifically, the backfill trench 3 on the substrate 1 is used for depositing a backfill material 4 in the next step, and the backfill material 4 has a memory function, so that patterns of a semiconductor device or a metal line connected with the interconnect structure manufactured by the interconnect structure forming method provided by the embodiment can be memorized, and the interconnect structure matched with the patterns can be precisely etched in the next step. The structure and material of the substrate 1 may refer to the structure and material of the substrate 1 described in the first embodiment, and are not described herein again.
It will be appreciated that in practice it is possible to select an already etched auxiliary layer 2 with a back-filled trench 3, the auxiliary layer 2 being provided on the substrate 1 and then carrying out the subsequent etching operation. Or selecting the auxiliary layer 2 tiled on the substrate 1, etching the auxiliary layer 2 to form the back-filled trench 3, and then performing the following etching operation. The selection is specifically performed according to actual needs, and this embodiment is not particularly limited in this respect.
Further, as shown in fig. 2a, 2b, 3a, and 3b, the auxiliary layer 2 may include a dielectric layer 21 and an oxide film layer 22. The dielectric layer 21 is in contact with the substrate 1, and the oxide film layer 22 is arranged on one side of the dielectric layer 21 far away from the substrate 1. The material of the dielectric layer 21 may be amorphous silicon doped with boron, or may be doped with other materials such as phosphorus and arsenic. The oxide layer 22 may be specifically an oxide such as silicon oxide, silicon nitride, or the like. The materials of the dielectric layer 21 and the oxide film layer 22 are specifically selected according to actual needs, and this embodiment is not particularly limited in this respect.
Further, as shown in fig. 4a and 4b, a backfill material 4 is deposited on the side of the auxiliary layer 2 away from the substrate 1, and a backfill material 4 is also deposited in the backfill trench 3. I.e. depositing the backfill material 4 both over the auxiliary layer 2 and within the backfill trenches 3, as shown in fig. 4a, results in a higher backfill material 4 than the auxiliary layer 2, as shown in fig. 4 a.
Further, as described above, the auxiliary layer 2 may include the dielectric layer 21 and the oxide film layer 22. Therefore, when depositing the backfill material 4 on the side of the auxiliary layer 2 away from the substrate 1 and depositing the backfill material 4 in the backfill trench 3, the backfill material 4 may be deposited on the oxide film layer 22 on the side of the auxiliary layer 2 away from the substrate 1 and then depositing the backfill material 4 in the backfill trench 3.
Specifically, the side of the etching auxiliary layer 2 away from the substrate 1 deposits the backfill material 4 to be approximately flush with the backfill material 4 in the backfill trench 3. As described above, the backfill material 4 is deposited both over the auxiliary layer 2 and within the backfill trenches 3, resulting in a higher backfill material 4 than the auxiliary layer 2, as shown in fig. 4 a. Therefore, at this step, as shown in fig. 5a, the backfill material 4 is deposited by etching the side of the auxiliary layer 2 away from the substrate 1 to be approximately flush with the backfill material 4 in the backfill trench 3. It should be understood that when the etching assistant layer 2 is deposited with the backfill material 4 on the side away from the substrate of the substrate 1 to be approximately flush with the backfill material 4 in the backfill trench 3, the amorphous silicon planarization process as shown in fig. 5a may be adopted, and the method process of this embodiment is not limited thereto, as long as the deposition backfill material 4 on the side away from the substrate of the assistant layer 2 is etched to be approximately flush with the backfill material 4 in the backfill trench 3, which is not specifically limited in this embodiment.
Further, as described above, the auxiliary layer 2 may include the dielectric layer 21 and the oxide film layer 22. Therefore, when the etching auxiliary layer 2 is away from the substrate of the substrate 1 and the backfill material 4 is deposited until the etching auxiliary layer is approximately flush with the backfill material 4 in the backfill trench 3, the oxide film layer 22 deposited on the side of the etching auxiliary layer 2 away from the substrate 1 can be removed first, and then the etching auxiliary layer 2 is away from the substrate of the substrate 1 and the backfill material 4 is deposited until the etching auxiliary layer is approximately flush with the backfill material 4 in the backfill trench 3. Alternatively, the backfill material 4 deposited on the side of the auxiliary layer 2 away from the substrate 1 is etched until the backfill material 4 is approximately flush with the backfill material 4 in the backfill trench 3, and then the oxide film 22 deposited on the side of the auxiliary layer 2 away from the substrate 1 is removed.
As shown in fig. 6a and 6b, the backfill material 4 is deposited on the side of the etch-assist layer 2 away from the substrate 1 to be flush with the backfill material 4 in the backfill trench 3. As described above, the etch assisting layer 2 is etched on the side away from the substrate 1 to deposit the backfill material 4 to be approximately flush with the backfill material 4 in the backfill trench 3, and at this step, the backfill material 4 deposited on the assisting layer 2 is further etched to be flush with the backfill material 4 in the backfill trench 3.
Further, as described above, the auxiliary layer 2 may include the dielectric layer 21 and the oxide film layer 22. Therefore, the oxide film layer 22 deposited on the side of the auxiliary layer 2 away from the substrate 1 can be removed before the etching of the side of the auxiliary layer 2 away from the substrate 1 to be flush with the backfill material 4 in the backfill trench 3. The present embodiment is not particularly limited to this, as the case may be, in which step is removed.
As shown in fig. 7a and 7b, the contact portion of the auxiliary layer 2 and the backfill material 4 is removed to form the thin film trench 5. The thin film trenches 5 formed in this step are used for the subsequent formation of interconnect trenches parallel and juxtaposed to each other.
It should be understood that the process flow of forming the thin film trench 5 by removing the portion of the auxiliary layer 2 in contact with the backfill material 4 may be the process flow shown in fig. 4a, 5a, 6a, and 7a, or the process flow shown in fig. 11a and 7 a.
Specifically, the process flow of removing the portion of the auxiliary layer 2 in contact with the backfill material 4 to form the thin film trench 5 may be as shown in fig. 4a, 5a, 6a, and 7 a: firstly depositing a back filling material 4 above the auxiliary layer 2 and in the back filling groove 3, then carrying out a planarization operation on the back filling material 4 deposited above the auxiliary layer 2, so that the back filling material 4 is deposited on one side of the auxiliary layer 2 away from the substrate 1 until the side is approximately level with the back filling material 4 in the back filling groove 3, then etching the side of the auxiliary layer 2 away from the substrate 1 to deposit the back filling material 4 until the side is level with the back filling material 4 in the back filling groove 3, and then removing the contact part of the auxiliary layer 2 and the back filling material 4 to form a film groove 5. In this successive step, the width of the last formed film trench 5 coincides with the width of the starting backfill trench 3. While the auxiliary layer 2 and the underfill material 4 deposited in the underfill trench 3 are etched during the formation of the thin film trench 5, more precisely, the auxiliary layer 2 and the underfill material 4 deposited in the underfill trench 3 are etched to half of the original width during the formation of the thin film trench 5, thereby forming the subsequent thin film trench 5.
In addition to the flows shown in fig. 4a, 5a, 6a and 7a, reference may also be made to the flows shown in fig. 11a and 7a, i.e. the width of the backfill trench 3 in fig. 11a is half of the backfill trench 3 in fig. 4a, the thickness of the backfill material 4 deposited in the backfill trench 3 in fig. 11a is also half of the thickness of the backfill material 4 deposited in the backfill trench 3 in fig. 4a, and the backfill material 4 deposited in the backfill trench 3 in fig. 11a is flush with the auxiliary layer 2. Then, the following etching is performed, and at this time, it is only necessary to etch the auxiliary layer 2 so that the width of the thin film trench 5 formed by the etched auxiliary layer 2 is consistent with the width of the thin film trench 5 formed by the process shown in fig. 4a, 5a, 6a, and 7 a.
Similarly, according to the same principle as the process shown in fig. 11a and fig. 7a, the back filling material 4 may be only photo-etched, and the portion of the back filling material 4 contacting the auxiliary layer 2 is removed to form the thin film trench 5, which is not described herein again.
As shown in fig. 8a and 8b, a thin film layer 6 is deposited on the side wall of the thin film trench 5. After the thin film layers 6 are deposited on the side walls of the thin film trenches 5, the distance between the thin film layers 6 is the width of the interconnection trench to be subsequently formed. And it is ensured that the width between the film layers 6 is uniform along the length extension of the auxiliary layer 2.
Further, L1 ═ L2+ L3+ L4; l1 is the width of the thin film trench in the substrate length direction, L2 is the width of the etched backfill material in the substrate length direction, and L3 and L4 are the widths of the thin film layers on both sides of the thin film trench in the substrate length direction, respectively. It should be understood that, preferably, in the present embodiment, L3 ═ L4.
Specifically, as shown in fig. 4a, fig. 7a, and fig. 8a, L1 is the width of the thin film trench in the substrate length direction, L2 is the width of the partially etched underfill material in which the auxiliary layer is removed to contact the underfill material in the substrate length direction, L3 and L4 are the widths of the thin film layers on both sides of the thin film trench in the substrate length direction, respectively, and L1 is L2+ L3+ L4, preferably, in this embodiment, L3 is L4.
The material of the thin film layer 6 may be silicon, silicon nitride, aluminum oxide, or the like, and is specifically selected according to actual needs, and this embodiment is not particularly limited thereto.
Further, as shown in fig. 12a and 12b, the backfill material 4 between the thin film layers 6 is directly removed to form the interconnection trench 7.
As shown in fig. 9a, after step S14, the backfill material 4 and the auxiliary layer 2 are etched, and then the backfill material 4 is removed to form the interconnection trench 7. Further, as shown in fig. 9a, the backfill material 4 and the auxiliary layer 2 are etched to a half of the original thickness, and then the backfill material 4 is removed to form the interconnection trench 7.
As shown in fig. 12a and 10a, the backfill material 4 is removed, and the auxiliary layer 2 is etched to form the interconnection trench 7.
Further, as shown in fig. 10a and 10b, the interconnection trench 7 and the substrate 1 together form an interconnection structure 8, and compared with the prior art, the interconnection structure 8 provided in this embodiment effectively solves the problem that, as the size of the semiconductor component is smaller and smaller, the possibility of misalignment between the interconnection trench 7 in the interconnection structure 8 and the semiconductor device is higher in the prior art, and such misalignment may cause short circuit, opening or other problems.
The interconnection structure provided by the embodiment comprises a substrate, wherein interconnection grooves are distributed on the substrate along the length direction of the substrate, and the outlines of the interconnection grooves are adapted to semiconductor devices. The problem that in the prior art, when the size of a semiconductor component is smaller and smaller, the possibility that a through hole (or an interconnection groove) in an interconnection structure is misaligned with a semiconductor device is higher, and the misalignment can cause short circuit, opening or other problems is solved.
The foregoing is a more detailed description of the present invention that is presented in conjunction with specific embodiments, and the practice of the invention is not to be considered limited to those descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A method for forming an interconnection structure, comprising the steps of:
providing a substrate, and forming an auxiliary layer with a reverse filling groove on the substrate;
depositing a back filling material in the back filling groove;
removing the contact part of the auxiliary layer and the back filling material to form a film groove;
depositing a thin film layer on the side wall of the thin film groove;
and removing the backfill material to form an interconnection trench.
2. The method of claim 1, wherein forming an auxiliary layer having a backfill trench on the substrate comprises:
depositing an auxiliary layer on the substrate;
and etching the auxiliary layer to form the back filling groove.
3. The method as claimed in claim 1 or 2, wherein the auxiliary layer comprises a dielectric layer and an oxide film layer, one side of the dielectric layer is in contact with the substrate, and the oxide film layer is disposed on one side of the dielectric layer away from the substrate.
4. The method of claim 3, further comprising, before removing the portion of the auxiliary layer in contact with the backfill material: and removing the oxide film layer.
5. The method of claim 1, wherein depositing a backfill material in the backfill trench further comprises: depositing the backfill material on the side of the auxiliary layer away from the substrate;
before removing the part of the auxiliary layer contacting with the backfill material, the method further comprises the following steps:
and removing the backfill material on the side of the auxiliary layer far away from the substrate.
6. The method of claim 3, wherein removing the backfill material further comprises:
etching the dielectric layer; or
And etching the dielectric layer and the back filling material.
7. The method of claim 1, wherein removing the portion of the auxiliary layer in contact with the backfill material comprises:
etching the auxiliary layer, and removing a part of the auxiliary layer, which is in contact with the back filling material, to form the film groove; or
Photoetching the back filling material, and removing parts, which are in contact with the auxiliary layer, on the back filling material to form the film groove; or
And etching the auxiliary layer, removing the part of the auxiliary layer, which is in contact with the back filling material, photoetching the back filling material, and removing the part of the back filling material, which is in contact with the auxiliary layer, to form the film groove.
8. The method of claim 1, wherein the step of forming the interconnect structure comprises the step of forming the interconnect structure,
L1＝L2+L3+L4；
wherein L1 is the width of the thin film trench in the substrate length direction, L2 is the width of the backfill material after removing the contact portion between the auxiliary layer and the backfill material, and L3 and L4 are the widths of the thin film layers on both sides of the thin film trench in the substrate length direction, respectively.
9. The method as claimed in claim 2, wherein the dielectric layer is formed of amorphous silicon doped with boron, and the backfill material is formed of undoped amorphous silicon.
10. An interconnect structure, characterized in that it is made on the basis of the method for forming an interconnect structure according to any one of claims 1 to 9.
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