CN111584349A - Filling method of SiC epitaxial deep groove - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000002019 doping agent Substances 0.000 claims description 20
- 239000000460 chlorine Substances 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 14
- 239000012159 carrier gas Substances 0.000 claims description 13
- 239000011261 inert gas Substances 0.000 claims description 13
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052801 chlorine Inorganic materials 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 11
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000036961 partial effect Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 10
- 230000000149 penetrating effect Effects 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910003826 SiH3Cl Inorganic materials 0.000 description 1
- 229910003822 SiHCl3 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Abstract
The invention provides a method for filling a SiC epitaxial deep groove, which comprises the following steps: etching a groove on an N-type 4H-SiC epitaxial layer growing on the substrate, wherein the etching depth is more than 10 mu m; partially filling the etched groove, and forming a SiC epitaxial layer with a V-shaped pit on the surface in the groove; filling and leveling the V-shaped pit; repeating the steps for many times until the growth is less than 5 microns away from the top of the groove; filling a SiC epitaxial layer with a smooth surface in the groove until the groove is filled; the invention reduces the transverse size of the V-shaped pit by controlling the growth condition, so that the V-shaped pit longitudinally grows at the initial stage, at the moment, the area of <0001> is reduced, the defect can be fully bent, and the probability of dislocation penetrating to the surface is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a method for filling a SiC epitaxial deep trench, in particular to a method for filling a SiC epitaxial deep trench with the depth of more than 10 mu m.
Background
As a typical representative third-generation wide bandgap semiconductor material, SiC has characteristics of wide bandgap, high critical breakdown field strength, high thermal conductivity, high carrier saturation rate, and the like. The method has wide application prospect in the fields of energy conservation and emission reduction, new energy automobiles and smart power grids.
One of the important directions in the advancement of optimization of SiC devices is to continuously decrease the specific on-resistance of the devices. The super junction technology is undoubtedly the most effective means to reduce the drift region specific on-resistance. The super junction technology is a technology which adopts an alternate P-type doped region structure and an N-type doped region structure to realize charge compensation and serve as a voltage-resistant layer so as to obtain low specific on-resistance and high voltage-resistant capability at the same time. Theoretically, it has been proved that the super junction device can convert Ron, sp ^ BV of theoretical limit of semiconductor material2.3～2.5Decrease to Ron, sp ^ BV1.32。
In the design of a super junction groove cellular structure, the depth of a groove and the doping concentration of an epitaxial layer determine the reverse voltage-resisting capacity of a device; the smaller the proportion of the trench width to the device surface area, the smaller the negative influence on the forward specific on-resistance; the inclination angle of the side wall is gradually close to 90 degrees, and the voltage resistance of the device is gradually improved. In the super junction third-generation groove, the groove is wider, the groove has a certain angle (88.6 degrees), on the basis of the fourth-generation process, the deep groove is optimized to 90 degrees from the original 88.6 degrees, the critical dimension of the groove such as the groove depth is deepened, the width of the groove is obviously reduced, and the performance of the device is obviously improved. But at the same time, the optimization of the trench morphology will increase the difficulty of deep trench etching and epitaxial filling.
In the aspect of SiC groove etching, a great number of research targets are to explore the relationship between the plasma dry etching rate and etching process conditions (such as reaction gas, ICP power, RF bias voltage, cavity pressure, cavity temperature and the like), and through a series of adjustment and optimization, the 4H-SiC plasma dry etching rate can reach the level of 1 μm/min, so that the etching of deep grooves larger than 50 μm is possible.
However, in the conventional SiC epitaxial growth process, interface dislocations formed from the substrate to the epitaxial layer and defects on the substrate extend all the way to the surface of the epitaxial layer, as shown in fig. 2, and seriously affect the leakage current and breakdown voltage of the device.
Disclosure of Invention
In order to solve the technical problem, the invention provides a filling method of a SiC epitaxial deep groove, which reduces the transverse size of a V-shaped pit by controlling the growth condition, so that the V-shaped pit grows longitudinally at the initial stage, at the moment, the area of <0001> is reduced, the interface dislocation and the defect on a substrate can turn fully, the probability of the interface dislocation and the defect on the substrate penetrating to the surface is reduced, and the crystal quality of SiC is improved.
The technical scheme adopted by the invention is as follows:
a filling method of a SiC epitaxial deep groove comprises the following steps:
(1) etching a groove on an N-type 4H-SiC epitaxial layer growing on the substrate, wherein the etching depth is more than 10 mu m;
(2) partially filling the etched groove, and forming a SiC epitaxial layer with a V-shaped pit on the surface in the groove;
(3) filling and leveling the V-shaped pit in the step (2);
(4) repeating the step (2) and the step (3) for multiple times until the growth is less than 5 microns away from the top of the groove;
(5) and filling the SiC epitaxial layer with a smooth surface into the groove until the groove is filled.
Further, before the step (2), a step of filling the etched trench with an intrinsic 4H-SiC buffer layer is further included. Intrinsic 4H-SiC with the lattice constant between the N-type 4H-SiC epitaxial layer and the P-type 4H-SiC epitaxial layer is inserted between the N-type 4H-SiC epitaxial layer and the P-type 4H-SiC epitaxial layer, so that lattice mismatch is relieved, and the crystal quality is improved;
the thickness of the intrinsic 4H-SiC buffer layer is 10-100 nm, if the thickness is less than 10nm, lattice mismatch is difficult to buffer effectively, and if the thickness is more than 100nm, the on-resistance of the device can be increased;
and (5) polishing the overgrown 4H-SiC on the top of the table top to obtain P-type and N-type regions which are smoothly and alternately arranged on the upper surface, thereby obtaining the super junction structure.
In the step (1), the thickness of the N-type 4H-SiC epitaxial layer is 40-50 mu m, and the doping concentration is 3 × 1014cm-3～9×1016cm-3(ii) a The method for etching the groove comprises the following steps<11-20>And etching the crystal direction, wherein the inclination angle of the side wall of the groove is 90 degrees, the width of the bottom of the groove is consistent with that of the top of the table top and is 1.5-2 mu m, and the depth of the groove is preferably 40-50 mu m.
In the step (2), the partial filling conditions are as follows: introducing chlorine-containing silicon source gas, carbon source, HCl and Al dopant into the epitaxial chamber, and introducing H2And inert gas is taken as carrier gas, the Cl/Si is controlled to be 20-50, the filling rate is 6-10 mu m/h, the temperature is 1580-1650 ℃, and the temperature is 400 DEGGrowing for 5-10 min under the pressure of-600 mbar.
Further, the inert gas is helium or argon; said H2The flow rate of the inert gas is 1/1 to 1/3; the total amount of the carrier gas is 150 to 300 slm. Because the diffusion length of atoms in the inert atmosphere is obviously less than that of H2Atmosphere, therefore, if H2When the flow rate of the inert gas is more than 1, the atomic diffusion distance increases, and it becomes difficult to form V-shaped pits if H is present2The flow rate of the inert gas is less than 1/3, the cracking speed is reduced, and the long speed is reduced.
Furthermore, the flow rates of the chlorine-containing silicon source gas, the carbon source, the HCl and the Al dopant are respectively 100-200 sccm, 1000-5000 sccm and 20-50 sccm, and the diffusion length of atoms is reduced and the growth of V-shaped pits is promoted by using relatively low-temperature, high-pressure and high-length-speed growth conditions.
In the step (3), keeping other conditions in the step (2) unchanged, closing the inert gas and carrying the gas H2The flow rate of the Al dopant and the flow rate of the Al dopant are both increased to 1.5-2 times, the V-shaped pit is filled and leveled up by growing for 20-30 min at 1650-1750 ℃ and under 50-200 mbar pressure, the reaction source can be fully diffused in the reaction chamber by increasing the flow rate of the carrier gas, the partial pressure of the reaction source is reduced, the growth speed is reduced, and the reduction of the growth speed is beneficial to increasing the atom migration distance to fill up the V-shaped pit; and the carrier gas flow is increased, the partial pressure of the Al dopant is reduced, the C/Si ratio is unchanged, and the doping concentration is reduced according to the competitive position principle, so that the flow of the Al dopant is increased by 1.5-2 times of the flow of the Al dopant in the last step by compensating the flow of the Al in proportion, the doping concentration in the groove is kept consistent, and the diffusion length of atoms is increased by using the relatively high-temperature, low-pressure and low-long-speed growth conditions, so that the filling efficiency of the V-shaped pit is promoted.
In the step (7), the filling conditions are as follows: introducing chlorine-containing silicon source gas, carbon source, HCl and Al dopant into the epitaxial chamber, and introducing H2And (3) as a carrier gas, controlling the Cl/Si ratio to be 20-50, and filling the groove at the temperature of 1580-1750 ℃ and under the pressure of 100-600 mbar.
Further, the chlorine-containing silicon source gas, a carbon source, HCl, an Al dopant and H2Respectively at a flow rate of 100～500sccm、100～500sccm、1000～5000sccm、20～100sccm、150～300slm。
The chlorine-containing silicon source gas is SiCl4，SiHCl3，SiH2C12Or SiH3Cl。
Compared with the prior art, the invention has the following advantages:
1) the invention realizes the filling of the SiC epitaxial deep groove, promotes the interface dislocation and the defect on the substrate to be capable of turning fully through the processes of V-shaped pit growth and V-shaped pit filling for many times in the groove, and reduces the probability of the interface dislocation and the defect penetrating to the surface as shown in figures 3-5, thereby obviously reducing the density of the penetrating dislocation, reducing the leakage current and improving the crystal quality of the filled groove;
2) before forming the V-shaped pit, an intrinsic 4H-SiC buffer layer with a certain thickness and a lattice constant between the N-type 4H-SiC epitaxial layer and the P-type 4H-SiC epitaxial layer is continuously grown in the groove to relieve lattice mismatch and further improve the crystal quality;
3) the growth and filling process of the V-shaped pit is repeatedly carried out until the distance from the top of the groove is less than 5 microns, so that the depth of the final groove is shallow, the surface of the epitaxial layer filled in the groove finally is flat, the groove is directly filled, the filling time is shortened, the growth benefit is improved, and the production cost is reduced;
4) when the V-shaped pit is filled and leveled, the flow of the Al is compensated in proportion while the flow of the carrier gas is increased, so that the doping concentration in the groove is consistent.
Drawings
Fig. 1 is a schematic view of a process flow of filling the SiC epitaxial deep trench in embodiment 1;
FIG. 2 is a schematic view of conventional interface dislocation and defect propagation;
FIG. 3 is a schematic diagram of V-pit growth in the present invention;
FIG. 4 is a schematic view of the interface dislocation and defect propagation of the present invention;
FIG. 5 is a schematic diagram of the interface dislocation and defect self-annihilation mechanism of the present invention.
Detailed Description
The present invention will be described in detail with reference to examples.
Example 1
A filling method of a SiC epitaxial deep groove comprises the following steps:
(1) growing the silicon nitride in an epitaxial furnace with the doping concentration of 3 × 10 and the thickness of 40-50 mu m14cm-3～9×1016cm-3Taking out and cleaning the N-type 4H-SiC epitaxial layer; etching the groove of the N-type 4H-SiC epitaxial layer grown on the substrate<11-20>The crystal orientation etching depth is larger than 10 mu m, the inclination angle of the side wall of the groove is 90 degrees, the bottom width is consistent with the top width of the table top and is 1.5-2 mu m, and the mask is removed after etching; cleaning again, drying and feeding into an epitaxial furnace;
(2) partially filling the etched groove, introducing chlorine-containing silicon source gas, carbon source, HCl and Al dopant at the flow rates of 100-200 sccm, 1000-5000 sccm and 20-50 sccm respectively, and introducing H2And an inert gas such as helium or argon as a carrier gas, H21-1/3 parts of inert gas, 150-300 slm parts of carrier gas, 20-50 parts of Cl/Si, 6-10 mu m/h of filling rate, and 5-10 min of growth time at 1580-1650 ℃ and 400-600 mbar pressure to form a SiC epitaxial layer with a V-shaped pit on the surface in the groove;
(3) closing the flow of the inert gas, keeping the flow of the chlorine-containing silicon source gas, the flow of the carbon source and the flow of the HCl unchanged, and carrying the gas H2And the flow rate of the Al dopant is increased to 1.5-2 times, the growth time is 20-30 min at 1650-1750 ℃ and 50-200 mbar pressure, and the groove is filled so as to fill and level the V-shaped pit in the step (2);
(4) repeating the step (2) and the step (3) for multiple times until the growth is less than 5 microns away from the top of the groove;
(5) introducing a chlorine-containing silicon source gas, a carbon source, HCl and an Al dopant at flow rates of 100-500 sccm, 1000-5000 sccm and 20-100 sccm, respectively, and introducing a carrier gas H at a flow rate of 150-300 slm2Controlling Cl/Si to be 20-50, and filling the groove at 1580-1750 ℃ and under the pressure of 100-600 mbar;
(6) polishing, using standard process to make chemical mechanical polishing, and removing overgrown 4H-SiC on the top of the mesa to obtain the p-type and n-type regions which are alternately arranged and have smooth upper surfaces.
Example 2
A method for filling a deep trench in SiC epitaxy, which is otherwise the same as in embodiment 1 except that a step of filling an intrinsic 4H-SiC buffer layer into the etched trench is further included between the steps (1) and (2), and the specific method is as follows: turning off N2And the dopant is an intrinsic SiC epitaxial layer with the thickness of 10-100 nm grown under the condition of growing the N-type epitaxial layer and is used as a buffer layer.
Comparative example 1
A filling method of a SiC epitaxial trench is otherwise the same as that of the embodiment 1, except that the step (5) filling is directly carried out after the step (1), and the characteristic data of the epitaxy of the SiC epitaxial trench is shown in Table 1.
TABLE 1
| Epitaxial surface roughness Ra (nm) (10 um) | Epitaxial surface defect density (cm)-2) | |
| Comparative example 1 | ≥0.68 | ≥0.62 |
| Example 1 | ≤0.31 | ≤0.25 |
The above detailed description of the filling method of the SiC epitaxial deep trench with reference to the embodiments is illustrative and not restrictive, and several embodiments may be enumerated within the scope of the limitations, so that variations and modifications thereof may fall within the scope of the present invention without departing from the general inventive concept.
Claims (10)
1. A filling method of a SiC epitaxial deep groove is characterized by comprising the following steps:
(1) etching a groove on an N-type 4H-SiC epitaxial layer growing on the substrate, wherein the etching depth is more than 10 mu m;
(2) partially filling the etched groove, and forming a SiC epitaxial layer with a V-shaped pit on the surface in the groove;
(3) filling and leveling the V-shaped pit in the step (2);
(4) repeating the step (2) and the step (3) for multiple times until the growth is less than 5 microns away from the top of the groove;
(5) and filling the SiC epitaxial layer with a smooth surface into the groove until the groove is filled.
2. The filling method according to claim 1, wherein the step (2) is preceded by a step of filling the etched trench with an intrinsic 4H-SiC buffer layer.
3. The filling method according to claim 1, wherein the step (5) is followed by a step of polishing off overgrown 4H-SiC on top of the mesa.
4. The filling method according to any one of claims 1 to 3, wherein in the step (1), the thickness of the N-type 4H-SiC epitaxial layer is 40 to 50 μm, and the doping concentration is 3 × 1014cm-3～9×1016cm-3(ii) a The method for etching the groove comprises the following steps<11-20>And etching the crystal direction, wherein the inclination angle of the side wall of the groove is 90 degrees, and the width of the bottom of the groove is consistent with that of the top of the table board and is 1.5-2 mu m.
5. The filling method according to any one of claims 1 to 3, wherein in the step (2), the conditions for the partial filling are: introducing chlorine-containing silicon source gas, carbon source, HCl and Al dopant into the epitaxial chamber, and introducing H2And taking inert gas as carrier gas, controlling the Cl/Si ratio to be 20-50, controlling the filling rate to be 6-10 mu m/h, and growing for 5-10 min at the temperature of 1580-1650 ℃ and under the pressure of 400-600 mbar.
6. The filling method according to claim 5, wherein the inert gas is helium or argon; said H2The flow rate of the inert gas is 1/1 to 1/3; the total amount of the carrier gas is 150 to 300 slm.
7. The filling method according to claim 5, wherein the flow rates of the chlorine-containing silicon source gas, the carbon source, the HCl and the Al dopant are 100 to 200sccm, 1000 to 5000sccm and 20 to 50sccm, respectively.
8. The filling method according to any one of claims 1 to 3 or 6 to 7, wherein in the step (3), the inert gas and the carrier gas H are turned off while keeping the other conditions in the step (2) unchanged2The flow rate of the Al dopant and the flow rate of the Al dopant are both improved to 1.5-2 times, and the Al dopant grows for 20-30 min at 1650-1750 ℃ and under the pressure of 50-200 mbar to fill and level the V-shaped pit.
9. The filling method according to any one of claims 1 to 3, wherein in step (7), the filling conditions are: introducing chlorine-containing silicon source gas, carbon source, HCl and Al dopant into the epitaxial chamber, and introducing H2And (3) as a carrier gas, controlling the Cl/Si ratio to be 20-50, and filling the groove at the temperature of 1580-1750 ℃ and under the pressure of 100-600 mbar.
10. The filling method according to claim 9, wherein the chlorine-containing silicon source gas, the carbon source, the HCl, the Al dopant, the H2The flow rates of the flow rate control agent are 100 to 500sccm, 1000 to 5000sccm, 20 to 100sccm, and 150 to 300slm, respectively.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002220299A (en) * | 2001-01-19 | 2002-08-09 | Hoya Corp | SINGLE CRYSTAL SiC AND METHOD OF PRODUCING THE SAME AND SiC SEMI CONDUCTOR DEVICE AND SiC COMPOSITE MATERIAL |
| CN105140111A (en) * | 2015-08-11 | 2015-12-09 | 中国科学院半导体研究所 | Method for removing punch-through defects on silicon carbide epitaxial surface |
| CN106048716A (en) * | 2016-06-30 | 2016-10-26 | 山东天岳先进材料科技有限公司 | Optimization method of silicon carbide substrate |
| CN106876463A (en) * | 2016-12-28 | 2017-06-20 | 全球能源互联网研究院 | A kind of superjunction silicon carbide device and preparation method thereof |
| CN110112057A (en) * | 2019-04-28 | 2019-08-09 | 台州市一能科技有限公司 | A kind of silicon carbide epitaxial wafer and production method and the chip with silicon carbide epitaxial wafer |
-
2020
- 2020-05-25 CN CN202010450739.8A patent/CN111584349A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002220299A (en) * | 2001-01-19 | 2002-08-09 | Hoya Corp | SINGLE CRYSTAL SiC AND METHOD OF PRODUCING THE SAME AND SiC SEMI CONDUCTOR DEVICE AND SiC COMPOSITE MATERIAL |
| CN105140111A (en) * | 2015-08-11 | 2015-12-09 | 中国科学院半导体研究所 | Method for removing punch-through defects on silicon carbide epitaxial surface |
| CN106048716A (en) * | 2016-06-30 | 2016-10-26 | 山东天岳先进材料科技有限公司 | Optimization method of silicon carbide substrate |
| CN106876463A (en) * | 2016-12-28 | 2017-06-20 | 全球能源互联网研究院 | A kind of superjunction silicon carbide device and preparation method thereof |
| CN110112057A (en) * | 2019-04-28 | 2019-08-09 | 台州市一能科技有限公司 | A kind of silicon carbide epitaxial wafer and production method and the chip with silicon carbide epitaxial wafer |
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