CN111584347B - GaN-Si heteroepitaxial structure and preparation method thereof - Google Patents

GaN-Si heteroepitaxial structure and preparation method thereof Download PDF

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CN111584347B
CN111584347B CN202010477741.4A CN202010477741A CN111584347B CN 111584347 B CN111584347 B CN 111584347B CN 202010477741 A CN202010477741 A CN 202010477741A CN 111584347 B CN111584347 B CN 111584347B
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layer
groove
gan
soi substrate
transition layer
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CN111584347A (en
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莫炯炯
王志宇
陈华
刘家瑞
郁发新
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Abstract

According to the GaN-Si hetero-epitaxial structure and the preparation method, the groove is formed in the Si substrate, and the local SOI substrate is formed at the bottom of the groove, so that the stress generated in the GaN layer epitaxial process can be absorbed through the local SOI substrate, and the Al is reducedxGa1‑xThe thickness of the N transition layer reduces the growth process time, reduces the process cost, improves the heat-conducting property, and simultaneously, the partial SOI buried oxide layer can improve the breakdown voltage of the GaN device and can reduce the loss and crosstalk in the RF application process; the GaN layer grown by epitaxy can be effectively isolated through the insulating side wall covering the side wall of the groove, so that the process difficulty is reduced; in the groove of the Si substrate, a GaN layer is epitaxially grown in a region selective manner, so that the process difficulty can be reduced; thus, the present invention can heteroepitaxially form a uniform high-quality GaN layer on a large-sized Si substrate.

Description

GaN-Si heteroepitaxial structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a GaN-Si hetero-epitaxial structure and a preparation method thereof.
Background
As a representative of the third generation semiconductor materials, gallium nitride (GaN) has many excellent characteristics such as a high critical breakdown electric field, high electron mobility, a high two-dimensional electron gas concentration, and good high-temperature operation ability. Therefore, third generation GaN-based semiconductor devices, such as High Electron Mobility Transistors (HEMTs), Heterojunction Field Effect Transistors (HFETs), etc., have been used, which have significant advantages especially in the fields of radio frequency, microwave, etc., where high power and high frequency are required.
GaN epitaxial thin film growth typically uses SiC, sapphire, GaN as substrates, but these substrates are expensive and difficult to form into large-sized wafers, e.g., 8-12 inches. Therefore, based on cost performance considerations, and the development of large-scale integrated circuits, Si substrates are undoubtedly the first substrate for GaN epitaxial thin film growth.
At present, the epitaxy of GaN thin film on Si substrate can be realized, but due to the lattice mismatch and large thermal runaway between GaN material and Si material, by first extending AlGaN transition layer with thickness of 2 μm-5 μm on Si substrate, it is necessary to adjust stress, release stress, and limit the defects and dislocations generated during the epitaxy process in the AlGaN transition layer, but at the same time, when GaN thin film is extended on Si substrate with large size (such as 12 inch Si wafer, etc.), the uniformity of GaN thin film is also a big challenge.
Therefore, it is necessary to provide a GaN-Si heteroepitaxial structure and a method of fabrication to heteroepitaxially form a uniform, high quality GaN thin film on a large Si substrate.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a GaN-Si heteroepitaxial structure and a fabrication method for solving the problem of the prior art that it is difficult to heteroepitaxially a uniform, high-quality GaN thin film on a large-sized Si substrate.
To achieve the above and other related objects, the present invention provides a method for fabricating a GaN-Si hetero-epitaxial structure, comprising the steps of:
providing a Si substrate;
forming a groove in the Si substrate;
forming a local SOI substrate at the bottom of the groove by oxygen ion implantation;
forming an insulating medium layer covering the bottom and the side wall of the groove in the groove;
removing the insulating medium layer at the bottom of the groove to form an insulating side wall covering the side wall of the groove;
forming an AlN layer and Al in the groove in a stacked mannerxGa1-xAn N transition layer and a GaN layer, wherein Al is in the layerxGa1-xIn the N transition layer, the value range of x is more than 0 and less than 1.
Optionally, the step of forming a local SOI substrate at the bottom of the recess by oxygen ion implantation comprises:
forming SiO covering the bottom of the groove2A layer;
oxygen ion implantation is carried out, wherein the oxygen ion implantation conditions comprise implantation energy of 50 keV-100 keV and implantation dosage of 10 keV17～1018ions/cm2；
And annealing, wherein the annealing conditions comprise that the annealing temperature is 1300-1400 ℃, and the annealing time is 1-2 h.
Optionally, the step of forming the local SOI substrate by oxygen ion implantation further includes forming the insulating dielectric layer and before forming the insulating sidewall.
Optionally, an AlN layer and Al stacked in sequence are formed in the recessxGa1-xThe N transition layer and the GaN layer comprise the following steps:
forming an AlN nucleating layer in the groove at 900-980 ℃, and then raising the temperature to 1000-1085 ℃ to convert the AlN nucleating layer into the AlN layer;
forming the Al under the condition of 1000-1060 DEG CxGa1-xAn N transition layer;
under the condition of 1000-1040 deg.C in the described AlxGa1-xAnd forming the GaN layer on the N transition layer.
Optionally, the AlN layer and the Al layer are formed and sequentially stacked under the condition that the pressure in the cavity is 100mbarxGa1-xN transition layer and bottom GaN layer, and under the condition that the pressure in the cavity is 400mbar, top GaN layer is formed.
Optionally, before forming the insulating dielectric layer, performing a surface oxidation treatment and a cleaning treatment; wherein the surface oxidation treatment method comprises H2O2One or a combination of surface oxidation, ozone surface oxidation and oxygen plasma oxidation, and the cleaning solution of the cleaning treatment comprises BOE cleaning solution.
Optionally, the Si base includes a Si (111) substrate or an SOI substrate, and when the Si base is the SOI substrate, the groove penetrates through a buried oxide layer in the SOI substrate.
The invention provides a GaN-Si hetero-epitaxial structure, which comprises:
a Si substrate;
a groove in the Si substrate;
a local SOI substrate located at the bottom of the groove;
the insulating side wall is positioned in the groove and covers the side wall of the groove;
an AlN layer and Al layer sequentially stacked in the groovexGa1-xAn N transition layer and a GaN layer, wherein Al is in the layerxGa1-xIn the N transition layer, the value range of x is more than 0 and less than 1.
Optionally, the GaN layer includes a bottom GaN layer and a top GaN layer.
Optionally, the Si base includes a Si (111) substrate or an SOI substrate, and when the Si base is the SOI substrate, the groove penetrates a buried oxide layer in the SOI substrate.
As described above, according to the GaN-Si hetero-epitaxial structure and the fabrication method of the present invention, the groove is formed in the Si substrate, and the partial SOI substrate is formed at the bottom of the groove by oxygen ion implantation, so that the stress generated during the epitaxy of the GaN layer can be absorbed by the partial SOI substrate, and the GaN layer is grown in the groove on the partial SOI substrate, thereby reducing the Al requiredxGa1-xThe thickness of the N transition layer can reduce the growth process time and the process cost, and the thinner AlxGa1-xThe N transition layer can also improve the heat conduction performance, and meanwhile, the local SOI oxygen buried layer formed in the local SOI substrate can improve the breakdown voltage of a GaN device and can reduce the loss and crosstalk in RF application; the insulation side wall covering the side wall of the groove can effectively isolate the GaN layer grown in an epitaxial mode, so that an isolation layer of a GaN device can be formed without an additional ion implantation or etching method in the subsequent preparation process of related devices and circuits, and the process difficulty is reduced; the GaN layer is epitaxially grown in the groove of the Si substrate in a region selective manner, so that the process difficulty can be reduced compared with the heteroepitaxy of the whole wafer; thus, the present invention can heteroepitaxially form a uniform high-quality GaN layer on a large-sized Si substrate.
Drawings
FIG. 1 shows a process flow diagram for fabricating a GaN-Si hetero-epitaxial structure in an example.
Fig. 2 is a schematic structural view of an SOI substrate in the embodiment.
Fig. 3 is a schematic structural diagram of the SOI substrate after a groove is formed therein in the embodiment.
Figure 4 shows a schematic structural diagram of a local SOI substrate formed by oxygen ion implantation in an embodiment,
FIG. 5 is a schematic structural diagram illustrating the formation of an insulating dielectric layer in an embodiment.
FIG. 6 is a schematic structural diagram illustrating the formation of an insulating sidewall in an embodiment.
FIG. 7 shows an example in which an AlN layer and Al layer are formed in a stacked manner in the recess in this orderxGa1-xThe structure of the N transition layer and the GaN layer is shown schematically.
Description of the element reference numerals
A 100-SOI substrate; 101-backing base silicon; 102-buried oxide layer; 103-top silicon; 110-a groove; 200-local SOI substrate; 201-local SOI backed base silicon; 202-local SOI buried oxide layer; 203-local SOI top silicon; 300-an insulating dielectric layer; 310-insulating side walls; 400-epitaxial stack; 401-AlN layer; 402-AlxGa1-xAn N transition layer; 403-GaN layer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and therefore, only the components related to the present invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed according to specific situations, and the layout of the components may be more complicated.
Referring to fig. 1, the present embodiment provides a method for fabricating a GaN-Si hetero-epitaxial structure, in which a recess is formed in a Si substrate, and a partial SOI substrate is formed at the bottom of the recess by oxygen ion implantation, so that stress generated during GaN layer epitaxy can be absorbed by the partial SOI substrate, and the partial SOI substrate on which a GaN layer is epitaxially grown can be fabricatedThe GaN layer grows in the groove on the bottom, so that the required Al can be reducedxGa1-xThe thickness of the N transition layer can reduce the growth process time and the process cost, and the thinner AlxGa1-xThe N transition layer can also improve the heat conduction performance, and meanwhile, the local SOI oxygen buried layer formed in the local SOI substrate can improve the breakdown voltage of a GaN device and can reduce the loss and crosstalk in RF application; the insulation side wall covering the side wall of the groove can effectively isolate the GaN layer grown in an epitaxial mode, so that an isolation layer of a GaN device can be formed without an additional ion implantation or etching method in the subsequent preparation process of related devices and circuits, and the process difficulty is reduced; the GaN layer is epitaxially grown in the groove of the Si substrate in a region selective manner, so that the process difficulty can be reduced compared with the heteroepitaxy of the whole wafer; so that a uniform, high-quality GaN layer can be heteroepitaxially grown on a large-sized Si substrate.
Specifically, referring to fig. 2 to 7, there are shown schematic structural views presented in the steps of fabricating the GaN-Si hetero-epitaxial structure.
First, a Si substrate is provided.
Specifically, referring to fig. 2, in the present embodiment, the Si substrate is an SOI substrate 100, that is, the SOI substrate 100 includes a back substrate silicon 101, a buried oxide layer 102 and a top layer silicon 103, but the material of the Si substrate is not limited thereto, for example, the Si substrate may also be an Si (111) substrate to meet the requirement of the subsequent high temperature epitaxy process, wherein the size of the Si substrate may be a wafer with a size of 8 inches, 12 inches, and the like, which is not limited herein.
Next, a recess 100 is formed in the Si substrate.
Specifically, referring to fig. 3, the recess 110 is formed in the SOI substrate 100, wherein a forming method for forming the recess 110 may adopt a photolithography method, that is, the forming method may include steps of coating, exposing, and developing, so as to form a patterned mask on the surface of the top silicon 103 to expose a region to be etched, and other regions are protected by the mask, and then the SOI substrate 100 may be etched by a dry reactive ion etching RIE using an F-based atmosphere to form the recess 110 for forming a region required for forming the subsequent epitaxial growth epitaxial stack 400. Wherein the depth of the recess 110 may be determined according to the required thickness of the epitaxial stack 400. In this embodiment, the recess 110 penetrates through the buried oxide layer 102 in the SOI substrate 100, and the depth of the recess 110 is preferably 1 μm to 5 μm, such as a value within a limit range of 2 μm, 2.5 μm, and the like. Through the grooves 110, the epitaxial stack 400 may be epitaxially grown with regioselectivity, thereby reducing process difficulty and forming a uniform, high-quality GaN layer 403, relative to heteroepitaxy of the entire wafer.
Next, a local SOI substrate 200 is formed at the bottom of the recess 110 by oxygen ion implantation.
Specifically, a new SOI substrate, that is, the local SOI substrate 200, may be formed at the bottom of the groove 110 by the oxygen ion implantation, so that the local SOI substrate 200 may be formed only in a region where the epitaxial stacked layer 400 needs to be epitaxially grown, so as to reduce the region where the epitaxial stacked layer 400 is epitaxially grown, and thus, the GaN layer 403 may be epitaxially grown with a regioselectivity, which may reduce the process difficulty compared to the hetero-epitaxy of the entire wafer; and the stress generated in the process of forming the GaN layer 403 can be absorbed by the local SOI substrate 200, so that the required Al can be reduced when the GaN layer 403 is grown in the groove 110xGa1-xThe thickness of the N transition layer 402 can reduce the growth process time and the process cost, and the Al is thinnerxGa1-x N transition layer 402, and Al may also be reducedxGa1-xThe poor thermal conductivity caused by the N transition layer 402 to improve the thermal conductivity; meanwhile, the local SOI buried oxide layer 202 in the local SOI substrate 200 can also improve the breakdown voltage of the GaN device and reduce the loss and crosstalk in RF application.
As an example, the step of forming the local SOI substrate 200 at the bottom of the recess 110 by oxygen ion implantation includes:
forming SiO covering the bottom of the groove 1102Layer (not shown), and the SiO2The thickness range of the layer comprises 200nm to 500 nm;
oxygen ion implantation is carried out, wherein the oxygen ion implantation conditions comprise implantation energy of 50 keV-100 keV and implantation dosage of 10 keV17～1018ions/cm2；
And annealing, wherein the annealing conditions comprise that the annealing temperature is 1300-1400 ℃, and the annealing time is 1-2 h.
Specifically, referring to fig. 4, a dashed box illustrates a region of the local SOI substrate 200. A layer of SiO may be formed in the recess 110 prior to oxygen ion implantation2A layer with a thickness of 200nm, 300nm, 400nm, 500nm, etc., and then implanted at an implantation energy of 50keV to 100keV and an implantation dose of 1017～1018ions/cm2Under the conditions of (1), performing oxygen ion implantation, and then performing annealing at an annealing temperature of 1300-1400 ℃ for 1-2 h to form the local SOI buried oxide layer 202 at a predetermined depth in the back substrate silicon 101, wherein the depth of the local SOI buried oxide layer 202 can be adjusted by controlling the implantation process conditions, and is not limited herein, for example, the implantation energy can be 80keV, and the dosage can be 5 × 1017ions/cm2The annealing temperature can be 1350 ℃, the annealing time can be 1.5h and the like.
Next, an insulating dielectric layer 300 is formed in the recess 110 to cover the bottom and sidewalls of the recess 110.
Specifically, referring to fig. 5, the insulating dielectric layer 300 may be formed by CVD, but is not limited thereto. Wherein, the insulating medium layer 300 can adopt SiO2The choice of the layer or SiN layer, its specific thickness and material, is not overly limited herein.
As an example, before forming the insulating dielectric layer 300, a step of performing a surface oxidation treatment and a cleaning treatment is further included; wherein the surface oxidation treatment method comprises H2O2One or a combination of surface oxidation, ozone surface oxidation and oxygen plasma oxidation, and the cleaning solution of the cleaning treatment comprises BOE cleaning solution.
Specifically, the surface of the groove 110 may be cleaned by performing the surface oxidation treatment and the cleaning treatment, so as to achieve a smooth surface effect, improve the surface roughness, and ensure good interface quality. Wherein, preferably, after the pretreatment operation, the surface roughness of the groove 110 is less than 0.5nm, such as 0.2nm, 0.1nm, etc.
Then, the insulating medium layer 300 at the bottom of the groove 110 is removed, and an insulating sidewall 310 covering the sidewall of the groove 110 is formed.
Specifically, referring to fig. 6, the insulating dielectric layer 300 at the bottom of the groove 110 may be etched by using a dry reactive ion etching RIE method, and because the etching is anisotropic etching, only the insulating dielectric layer 300 at the bottom of the groove 110 is etched in the vertical direction, and the insulating dielectric layer 300 at the side wall of the groove 110 is left, so as to form the insulating sidewall 310. The GaN layer 403 can be effectively isolated by the insulating side walls 310 covering the side walls of the groove 110, so that an isolation layer of a GaN device circuit is formed without an additional ion implantation or etching method in the subsequent device and circuit preparation process, thereby further reducing the cost and the process difficulty.
As an example, the step of forming the local SOI substrate 200 by oxygen ion implantation further includes after forming the insulating dielectric layer 300 and before forming the insulating sidewall spacers 310, so as to expand the application range.
Then, an AlN layer 401 and Al stacked in the recess 110 are sequentially formedxGa1-xAn N transition layer 402 and a GaN layer 403, wherein Al is in the layerxGa1-xIn the N transition layer 402, the value range of x includes 0 < x < 1.
As an example, the AlxGa1-xThe N transition layer 402 may comprise a single layer or multiple layers, when the Al isxGa1-xWhen the N transition layer 402 is a multilayer, the values of x decrease in the extending direction from the AlN layer 401 to the GaN layer 403.
As an example, the AlN layer 401 and Al are formed in the recess 110 in a stacked mannerxGa1-xThe steps of the N transition layer 402 and the GaN layer 403 include:
forming the AlN nucleation layer (not shown) in the groove 110 at 900-980 ℃, and then raising the temperature to 1000-1085 ℃ to convert the AlN nucleation layer into the AlN layer 401;
forming the Al under the condition of 1000-1060 DEG CxGa1-xAn N transition layer 402;
under the condition of 1000-1040 deg.C in the described AlxGa1-xThe GaN layer 403 is formed on the N transition layer.
Specifically, in the process of forming the AlN layer 401, the low temperature is first used to facilitate the nucleation of AlN material to form the AlN nucleation layer, and the high temperature is then used to improve the quality of the AlN nucleation layer and to provide the subsequent Al layerxGa1-xThe growth of the N-transition layer 402 reduces the temperature difference. Then growing said Al with different Al components preferably at 1000-1060 deg.CxGa1-x N transition layer 402 to further relieve stress due to lattice mismatch of materials, but not limited thereto, the AlxGa1-xThe N transition layer 402 may also be a single layer. Wherein said Al isxGa1-xThe N transition layer 402 may include a first Al sequentially stacked on the AlN layer 401xGa1-xX is more than 0.5 and less than or equal to 0.8 in the N transition layer, and second AlxGa1-xX is more than 0.3 and less than or equal to 0.5 in the N transition layer, and third AlxGa1-xX is more than 0 and less than or equal to 0.3 of the N transition layer, and the first Al is formedxGa1-xThe thickness of the N transition layer comprises 200 nm-300 nm, such as 270nm Al0.8Ga0.2N transition layer, the second Al formedxGa1-xThe thickness of the N transition layer comprises 200nm to 300nm, such as 290nm Al0.5Ga0.5N transition layer, the third Al formedxGa1-xThe thickness of the N transition layer comprises 400nm to 500nm, such as 470nm of Al0.2Ga0.8Transition layer of N, however, said AlxGa1-xThe structure of the N transition layer 402 is not limited to this, and may be selected as needed. Finally, the GaN layer 403 is formed under the condition of 1000-1040 ℃, wherein the thickness of the GaN layer 403 can be in the rangeIncluding, but not limited to, 800nm to 1000nm, such as 900 nm.
Further, the GaN layer 403 may include a bottom GaN layer and a top GaN layer.
Specifically, the AlN layer 401 and Al are stacked in this orderxGa1-xThe pressure in the chamber may be 100mbar for the N transition layer 402 and the bottom GaN layer, and preferably 400mbar for the top GaN layer with a final thickness of 150 nm-250 nm, so that the AlN layer 401, Al, are grownxGa1-xWhen the N transition layer 402 and the bottom GaN layer are grown under a relatively low pressure, more carbon C may be introduced during the growth process to form a semi-insulating material, and when the top GaN layer having a final thickness of 150nm to 250nm is grown, the pressure is increased to improve the quality of the grown GaN crystal, thereby forming the high-quality GaN layer 403.
The embodiment also provides a GaN-Si hetero-epitaxial structure, which comprises a Si substrate, a groove, a local SOI substrate, an insulating side wall, an AlN layer and Al layer, wherein the AlN layer and the Al layer are sequentially stackedxGa1-xN transition layer and GaN layer. Wherein the groove is located in the Si substrate; the local SOI substrate is positioned at the bottom of the groove; the insulating side wall is positioned in the groove and covers the side wall of the groove; the AlN layer and the Al layer are sequentially stackedxGa1-xThe N transition layer and the GaN layer are arranged in the groove and the Al layerxGa1-xIn the N transition layer, the value range of x is more than 0 and less than 1. Specifically, the GaN-Si hetero-epitaxial structure may be formed using the above-described fabrication method, but is not limited thereto. Referring to fig. 7, the GaN-Si hetero-epitaxial structure in the present embodiment includes an SOI substrate 100, a recess 110, a local SOI substrate 200, an insulating sidewall 310, and an AlN layer 401 and Al stacked in sequencexGa1-xThe N transition layer 402 and the GaN layer 403, and the GaN-Si hetero-epitaxial structure is obtained by the above preparation method, so that details about the preparation process of the GaN-Si hetero-epitaxial structure are omitted here.
As an example, the AlxGa1-xThe N transition layer 402 may comprise a single layer or multiple layers, when the Al isxGa1-xWhen the N transition layer 402 is a multilayer, the values of x decrease sequentially from the AlN layer to the GaN layer in the extending direction.
As an example, the AlxGa1-xThe N transition layer 402 comprises first Al which is positioned on the AlN layer 401 and is stacked in sequencexGa1-xX is more than 0.5 and less than or equal to 0.8 in the N transition layer, and second AlxGa1-xX is more than 0.3 and less than or equal to 0.5 in the N transition layer and third AlxGa1-xX is more than 0 and less than or equal to 0.3 in the N transition layer; and the first Al is formedxGa1-xThe thickness of the N transition layer is 200 nm-300 nm, and the second Al is formedxGa1-xThe thickness of the N transition layer comprises 200 nm-300 nm, and the third Al is formedxGa1-xThe thickness of the N transition layer is 400 nm-500 nm, such as the first AlxGa1-xThe N transition layer comprises Al with the thickness of 270nm0.8Ga0.2N transition layer, the second AlxGa1-xThe N transition layer comprises Al with the thickness of 290nm0.5Ga0.5N transition layer, the third AlxGa1-xThe N transition layer comprises Al with the thickness of 470nm0.2Ga0.8Transition layer of N, however, said AlxGa1-xThe structure of the N transition layer 402 is not limited to this, and may be selected as needed.
As an example, the GaN layer includes a bottom GaN layer having a thickness of 650nm to 750nm and a top GaN layer having a thickness of 150nm to 250 nm.
As an example, the Si base further includes a Si (111) substrate, in this embodiment, the SOI substrate 100 is adopted, and the groove 110 penetrates through the buried oxide layer 102 in the SOI substrate 100.
As an example, the depth of the groove 110 ranges from 1 μm to 5 μm; the insulating sidewall spacers 310 in the grooves 110 comprise SiO2A layer or a SiN layer.
In the present embodiment, the local SOI substrate 200 is formed at the bottom of the groove 110, so that the stress generated during the epitaxy of the GaN layer 403 can be absorbed by the local SOI substrate 200, and the GaN layer 403 grown in the groove 110 on the local SOI substrate 200 can reduce the requirementThe Al isxGa1-xThe thickness of the N transition layer 402 can reduce the growth process time and the process cost, and the Al is thinnerxGa1-xThe N transition layer 402 can also improve the heat conduction performance, and the local SOI buried oxide layer 202 formed in the local SOI substrate 200 can improve the breakdown voltage of a GaN device and can reduce the loss and crosstalk in RF application; the epitaxially grown GaN layer 403 can be effectively isolated by the insulating side walls 310 covering the side walls of the groove 110, so that an isolation layer of a GaN device can be formed without an additional ion implantation or etching method in the subsequent preparation process of related devices and circuits, and the process difficulty is reduced; in the groove 110, the GaN layer 403 is epitaxially grown in a regioselective manner, so that the process difficulty can be reduced compared with the heteroepitaxy of the whole wafer; so that the GaN layer 403 of uniform, high quality can be heteroepitaxially grown on a large-sized Si substrate.
In summary, according to the GaN-Si hetero-epitaxial structure and the fabrication method of the present invention, the groove is formed in the Si substrate, and the local SOI substrate is formed at the bottom of the groove by oxygen ion implantation, so that the stress generated during the GaN layer epitaxy process can be absorbed by the local SOI substrate, and the GaN layer is grown in the groove on the local SOI substrate, thereby reducing the Al required for the GaN layer epitaxyxGa1-xThe thickness of the N transition layer can reduce the growth process time and the process cost, and the thinner AlxGa1-xThe N transition layer can also improve the heat conduction performance, and meanwhile, the local SOI oxygen buried layer formed in the local SOI substrate can improve the breakdown voltage of a GaN device and can reduce the loss and crosstalk in RF application; the insulation side wall covering the side wall of the groove can effectively isolate the GaN layer grown in an epitaxial mode, so that an isolation layer of a GaN device can be formed without an additional ion implantation or etching method in the subsequent preparation process of related devices and circuits, and the process difficulty is reduced; the GaN layer is epitaxially grown in the groove of the Si substrate in a region selective manner, so that the process difficulty can be reduced compared with the heteroepitaxy of the whole wafer; thus, the present invention can heteroepitaxially form a uniform high-quality GaN layer on a large-sized Si substrate.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (8)

1. A preparation method of a GaN-Si heteroepitaxial structure is characterized by comprising the following steps:
providing an SOI substrate;
forming a groove in the SOI substrate, wherein the groove penetrates through a buried oxide layer in the SOI substrate, and the depth range of the groove comprises 1-5 μm;
forming a local SOI substrate at the bottom of the groove by oxygen ion implantation;
carrying out surface oxidation treatment and cleaning treatment;
forming an insulating medium layer covering the bottom and the side wall of the groove in the groove;
removing the insulating medium layer at the bottom of the groove to form an insulating side wall covering the side wall of the groove, wherein the local SOI substrate is positioned below the insulating side wall;
forming an AlN layer and Al layer stacked in sequence on the local SOI substrate in the groove based on the local SOI substratexGa1-xAn N transition layer and a GaN layer, wherein Al is in the layerxGa1-xIn the N transition layer, the value range of x is more than 0 and less than 1, and the AlxGa1-xThe N transition layer comprises first Al which is positioned on the AlN layer and is stacked in sequencexGa1-xX is more than 0.5 and less than or equal to 0.8 in the N transition layer, and second AlxGa1-xX is more than 0.3 and less than or equal to 0.5 in the N transition layer, and third AlxGa1-xX is more than 0 and less than or equal to 0.3 of the N transition layer, and the first Al is formedxGa1-xThe thickness of the N transition layer is 200 nm-300 nm, and the second Al is formedxGa1-xThe thickness of the N transition layer comprises200nm to 300nm, the third Al is formedxGa1-xThe thickness of the N transition layer is 400 nm-500 nm.
2. The method of claim 1, wherein the step of forming a local SOI substrate at the bottom of the recess by oxygen ion implantation comprises:
forming SiO covering the bottom of the groove2A layer;
oxygen ion implantation is carried out, wherein the oxygen ion implantation conditions comprise implantation energy of 50 keV-100 keV and implantation dosage of 10 keV17～1018ions/cm2；
And annealing, wherein the annealing conditions comprise that the annealing temperature is 1300-1400 ℃, and the annealing time is 1-2 h.
3. The method of claim 1, wherein: and forming the local SOI substrate by oxygen ion implantation after the insulating dielectric layer is formed and before the insulating side wall is formed.
4. The production method according to claim 1, wherein an AlN layer and Al layer are formed in the recess so as to be stacked in this orderxGa1-xThe N transition layer and the GaN layer comprise the following steps:
forming an AlN nucleating layer in the groove at 900-980 ℃, and then raising the temperature to 1000-1085 ℃ to convert the AlN nucleating layer into the AlN layer;
forming the Al under the condition of 1000-1060 DEG CxGa1-xAn N transition layer;
under the condition of 1000-1040 deg.C in the described AlxGa1-xAnd forming the GaN layer on the N transition layer.
5. The method of claim 1, wherein: forming the AlN layer and the Al layer which are sequentially stacked under the condition that the pressure in the cavity is 100mbarxGa1-xN transition layer andand forming a top GaN layer under the pressure of 400mbar in the cavity.
6. The method of claim 1, wherein: the surface oxidation treatment method comprises H2O2One or a combination of surface oxidation, ozone surface oxidation and oxygen plasma oxidation, and the cleaning solution of the cleaning treatment comprises BOE cleaning solution.
7. A GaN-Si heteroepitaxial structure, characterized in that it comprises:
an SOI substrate;
the groove is positioned in the SOI substrate, penetrates through a buried oxide layer in the SOI substrate, has a depth range of 1-5 mu m and has a surface roughness of less than 0.5 nm;
a local SOI substrate located at the bottom of the groove;
the insulating side wall is positioned in the groove and covers the side wall of the groove, and the local SOI substrate is positioned below the insulating side wall;
an AlN layer and Al layer sequentially stacked in the groove and on the local SOI substratexGa1-xAn N transition layer and a GaN layer, wherein Al is in the layerxGa1-xIn the N transition layer, the value range of x is more than 0 and less than 1, and the AlxGa1-xThe N transition layer comprises first Al which is positioned on the AlN layer and is stacked in sequencexGa1-xX is more than 0.5 and less than or equal to 0.8 in the N transition layer, and second AlxGa1-xX is more than 0.3 and less than or equal to 0.5 in the N transition layer, and third AlxGa1-xX is more than 0 and less than or equal to 0.3 of the N transition layer, and the first Al is formedxGa1-xThe thickness of the N transition layer is 200 nm-300 nm, and the second Al is formedxGa1-xThe thickness of the N transition layer comprises 200 nm-300 nm, and the third Al is formedxGa1-xThe thickness of the N transition layer is 400 nm-500 nm.
8. The heteroepitaxial structure of claim 7, wherein: the GaN layer includes a bottom GaN layer and a top GaN layer.
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