CN115440573A - Single crystal SiC/Si wafer substrate, heterostructure and preparation method thereof - Google Patents

Single crystal SiC/Si wafer substrate, heterostructure and preparation method thereof Download PDF

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CN115440573A
CN115440573A CN202110619695.1A CN202110619695A CN115440573A CN 115440573 A CN115440573 A CN 115440573A CN 202110619695 A CN202110619695 A CN 202110619695A CN 115440573 A CN115440573 A CN 115440573A
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layer
gan
single crystal
wafer substrate
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黄早红
任新平
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Shanghai Chuanxin Semiconductor Co ltd
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Shanghai Chuanxin Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02373—Group 14 semiconducting materials
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/02447—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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Abstract

The invention provides a single crystal SiC/Si wafer substrate, a heterostructure and a preparation method thereof. The single crystal SiC/Si wafer substrate includes: a Si substrate having a plurality of patterned cell regions formed thereon, the plurality of cell regions being spaced apart from each other by spacers, and each cell region including a single crystal SiC layer formed on the corresponding cell region. The heterostructure includes the single crystal SiC/Si and GaN layers described previously. The preparation method includes reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer. Similarly, the nitrogen-containing gas and gallium-containing vapor phase material are reacted on the patterned single crystal SiC/Si wafer substrate by a MOCVD epitaxial growth process to form a single crystal GaN layer. The resulting single crystal SiC and GaN structures within the cell region have high quality and low defect density.

Description

Single crystal SiC/Si wafer substrate, heterostructure and preparation method thereof
Technical Field
The present invention relates to heterostructures and methods of making the same; in particular to a monocrystal SiC/Si wafer substrate, a monocrystal GaN/SiC heterostructure and a preparation method thereof.
Background
High power and high frequency circuits require devices based on semiconductor materials that have both large breakdown voltages and high electron speeds. Unlike conventional semiconductor materials, wide bandgap materials, such as GaN and SiC, are of particular interest because of their ability to be used at higher power densities. GaN and SiC based devices grown on silicon (Si) substrates are expected to be one of the best candidates for next generation systems seeking close proximity to each other, void-free integration of RF and digital circuitry.
SiC is also gaining wide attention in power application fields due to its high thermal conductivity compared to GaN, can theoretically withstand higher power density than existing polycrystalline SiC, and 3C — SiC can be directly grown on Si to be noticed, and also has extremely high electron mobility. Currently, a number of attempts have been made to directly grow and integrate high quality SiC and GaN devices on Si substrates for high quality power device applications.
The more common integration techniques are hybrid integration and heteroepitaxy, where hybrid integration approaches, such as wire bonding and flip chip approaches, provide short term solutions. However, this approach has limitations in terms of interconnect loss and chip positioning/alignment issues and integration density. In addition, the use of SiC and GaN materials for power devices exhibiting excellent performance is greatly limited in cost by the high defect density and small size of the substrate.
Heteroepitaxy, where different semiconductors are integrated onto Si substrates, is a more promising approach, while the biggest problems with growing Compound Semiconductors (CS) directly on Si are lattice mismatch and mismatch of Coefficient of Thermal Expansion (CTE). Current solutions to form GaN and SiC on larger size Si wafers appear to be less costly, while lattice mismatch and high defect density problems on larger size Si wafers become more severe. Alternatively, a complicated process of introducing a plurality of layers such as a buffer layer, a superlattice layer, and a barrier layer is required.
Accordingly, there is a need in the art for a simplified method of growing high quality single crystal SiC and GaN on large size silicon wafers and improved structures thereof.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for preparing a single crystal SiC-Si wafer base, which is used to solve the problems of lattice mismatch and thermal expansion coefficient mismatch between a SiC layer heteroepitaxially grown on a larger Si substrate and the substrate in the prior art.
To achieve the above objects and othersIn other related objects, the present invention provides a patterned single crystal SiC/Si wafer substrate, a patterned single crystal GaN/SiC/Si heterostructure wafer substrate, and a method of making the same, the method of making the single crystal SiC/Si wafer substrate comprising at least: providing a Si substrate; depositing SiO on the Si substrate 2 Layer of and on said SiO 2 Patterning a layer to form a pattern on the SiO 2 A plurality of grooves are formed in the layer, the grooves being formed of SiO surrounding the periphery thereof 2 The side wall is defined, and the Si substrate is exposed from the bottom of the groove; forming a layer of carbonaceous material in the recess; reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove; and removing the remaining carbon-containing material layer by a chemical mechanical polishing process to form a plurality of SiO-based layers 2 A sidewall separated SiC cell region.
Preferably, the annealing process comprises furnace annealing or rapid thermal annealing.
Preferably, the preparation method of the single crystal SiC/Si wafer substrate is characterized in that: the annealing process is a laser-based local annealing process.
Preferably, the SiC cell region has a size of less than or equal to 4 inches.
Preferably, the shape of the SiC unit cell region is a smooth rounded polygon, an ellipse, a circle, or a combination thereof.
Preferably, the thickness of the SiC cell region is from 0.1um to 10um.
Preferably, the layer of carbonaceous material comprises a layer of carbon formed by spin-on polymethylmethacrylate or chemical vapor deposition.
The invention also provides a wafer substrate of single crystal SiC/Si, the wafer substrate comprising at least: a Si substrate on which a plurality of patterned cell regions are formed, the plurality of cell regions being spaced apart from each other by spacers, and each cell region including a single crystal SiC layer formed on the corresponding cell region.
Preferably, the spacer comprises silicon dioxide or a void.
Preferably, the single crystal SiC is 3C-SiC or 4H-SiC.
The present invention provides a SiC-based metal oxide semiconductor field effect transistor formed based on the aforementioned patterned single crystal SiC/Si wafer substrate.
The invention provides a preparation method of a patterned single crystal GaN/SiC/Si heterostructure wafer substrate, which at least comprises the following steps: providing a Si substrate; depositing SiO on the Si substrate 2 Layer of and to the SiO 2 Patterning a layer to form a pattern on the SiO 2 A plurality of grooves are formed in the layer, the grooves being formed of SiO surrounding the periphery thereof 2 The side wall is limited, and the Si substrate is exposed at the bottom of the groove; forming a layer of carbonaceous material in the recess; reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove; removing the residual carbon-containing material layer by chemical mechanical polishing process to form the SiO 2 A sidewall-separated SiC cell region; continuing to deposit a GaN stack on the patterned SiC/Si wafer substrate, the GaN stack including a GaN layer and an AlGaN barrier layer; and removing the SiO by a chemical mechanical polishing process 2 A GaN stack on the surface.
Preferably, the GaN stack further includes a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.
Preferably, the GaN stack is deposited by performing a MOCVD epitaxial growth process comprising: forming a GaN nucleation layer at a temperature of 500-800 ℃; and forming a GaN epitaxial layer at a temperature of 900-1100 ℃. .
Preferably, the precursor for depositing the GaN stack includes NH as a nitrogen source 3 And organic vapor phase materials containing aluminum and gallium.
Preferably, the aluminum-containing organic vapor phase material is trimethylaluminum (TMAl) and the gallium-containing organic vapor phase material is trimethylgallium (TMGa).
The invention also provides a patterned single crystal GaN/SiC/Si heterostructure wafer substrate, the wafer substrate comprising at least: a Si substrate on which a plurality of patterned cell regions are formed, the plurality of cell regions being spaced apart from each other by spacers, and each cell region including: a single crystal SiC layer formed on the respective cell regions; and a GaN stack including a GaN layer and an AlGaN barrier layer.
Preferably, the GaN stack further includes a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.
The present invention also provides a GaN-based High Electron Mobility Transistor (HEMT) formed based on the aforementioned patterned single crystal GaN/SiC/Si heterostructure wafer substrate.
As described above, the method for producing a single crystal SiC/Si wafer substrate of the present invention has the following advantageous effects: the single crystal SiC layer is selectively grown on the Si substrate, the CMOS device based on the compound semiconductor can be purposefully positioned on the substrate, so that the performance of a circuit is optimized, meanwhile, the defect density at an interface can be reduced through selective area growth, and therefore the device based on the wafer substrate has small leakage current and optimized performance; the laser with high energy is adopted, a localized heating scheme can be provided, and the resolution of an irradiation area can be improved by controlling the spatial distribution of the laser; laser-based localized annealing enables Si materials to undergo melting and recrystallization in a very short period of time, rapidly bringing the material to homogeneity, which allows modification of surface properties without changing bulk region properties, reducing damage to the substrate and adjacent circuitry by confining energy absorbing regions to the irradiated surface regions. By the preparation method of the patterned single crystal SiC/Si wafer substrate, high-quality single crystal SiC and GaN can be grown on a large-size substrate, and the obtained wafer substrate structure has high quality and low defect density and is particularly suitable for manufacturing SiC and GaN power devices.
Drawings
FIG. 1 shows a flow chart of a method of preparing a single crystal SiC/Si wafer substrate of the present invention.
FIG. 2 shows a schematic of the structure of a patterned single crystal SiC/Si wafer substrate according to the present invention.
FIGS. 3 to 6 are schematic structural views showing stages of a method for manufacturing a single crystal SiC/Si wafer substrate according to the present invention.
FIG. 7 shows a flow chart of a method of manufacturing a wafer substrate that is a patterned single crystal GaN/SiC/Si heterostructure of the present invention.
FIG. 8 shows a schematic of the structure of a wafer substrate that is a patterned single crystal GaN/SiC/Si heterostructure of the present invention.
Fig. 9 shows a schematic plan view of a HEMT device fabricated as a wafer substrate of a patterned single crystal GaN/SiC/Si heterostructure according to the present invention.
Description of the element reference
110 Si substrate
120 SiO 2 Layer(s)
122 SiO 2 Side wall
124. Spacer region
130. Groove
140 SiC layer
142 SiC cell region
250 GaN layer
252 GaN/SiC cell region
350 GaN stack
352 GaN buffer layer
354 GaN hetero-layer
356 AlGaN barrier layer
360. Grid metal
370. Source metal
380. Metal of drain electrode
S1 to S8
Detailed Description
Hereinafter, embodiments of the present invention are described with reference to specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. For purposes of clarity, components and steps that are well known to those skilled in the art are omitted to avoid unnecessarily obscuring the elements of the invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In order to solve the problems of lattice mismatch and thermal expansion coefficient mismatch between a compound semiconductor grown on a larger Si substrate and the substrate, and device performance degradation caused by high defect density, the present invention provides a novel method to selectively or locally grow SiC on the Si substrate. Such an approach allows the performance of the circuit to be optimized via purposeful positioning of compound semiconductor-based CMOS devices on commonly used Si substrates. Selective area growth helps to reduce the density of misfit dislocations in lattice mismatched systems by reducing the interaction and propagation of dislocations. Since the area of the growth area is limited to several mm 2 The quality of the heterogrowth compound semiconductor can be better optimized.
Herein, the term "large-sized substrate" means a wafer having a size exceeding 4 inches in terms of a wafer diameter; thus, the method of preparing a single crystal SiC/Si wafer substrate according to the present invention can be applied to larger wafers having a size exceeding 4 inches, for example, wafers greater than or equal to 6 inches, for example, wafers of 8 inches.
Conventionally, the step of growing SiC on the Si substrate by carbonization is carried out using a carbon source previously deposited on the Si by an annealing process conventional in the art, which causes the diffusion of carbon into the Si. Examples of annealing processes that are conventional in the art include furnace annealing, rapid Thermal Annealing (RTA), in which growth of a SiC layer only needs to be performed at a relatively lower temperature, for example, at a temperature of 1000-1400 ℃, in an RTA process due to enhanced SiC crystallization at a high heating rate. Preferably, the carbon source previously deposited on Si can be locally annealed using a high power laser beam. Laser irradiation has very high energy and can decompose the carbon source while melting the silicon to initiate SiC growth. Laser-based processes can provide localized heating; specifically, the spatial distribution of the laser is controlled by the laser beam focused by the optical element, which achieves localization of the irradiation energy and increases the spatial resolution of the laser. Further, based on localized annealing by laser light, siC growth on a larger substrate can be achieved under ambient conditions (atmospheric pressure and room temperature conditions), enabling the irradiated region of the Si substrate to undergo melting and recrystallization in an extremely short period of time, as compared to conventional furnace annealing and RTA processes.
On the other hand, the invention also provides a method for growing the crack-free AlGaN/GaN heterostructure on the single crystal SiC/Si wafer substrate, the AlGaN/GaN heterostructure is epitaxially grown on the single crystal SiC layer by the Metal Organic Chemical Vapor Deposition (MOCVD) technology, the SiC layer is grown on the selective area of the Si substrate relative to the SiC growth on the whole substrate, and the performance of the device can be effectively improved by adjusting the accumulation of lattice mismatch and thermal expansion mismatch; accordingly, a high quality GaN/SiC heterostructure can be formed on the patterned single crystal SiC/Si wafer substrate. Such AlGaN/GaN heterostructures can be used to fabricate high performance power devices such as High Electron Mobility Transistors (HEMTs).
As shown in fig. 1 and fig. 3 to 6, the present invention provides a method of selectively forming single crystal SiC on a Si substrate, the method of selectively forming a single crystal SiC layer comprising the steps of:
s1: a Si substrate is provided.
S2: deposition of SiO on Si substrates 2 And (3) a layer.
S3: to SiO 2 The layer is patterned to form a layer on the SiO 2 The layer forms a plurality of grooves.
S4: a layer of carbonaceous material is formed in the recess.
S5: and forming a SiC layer in the groove through an annealing process.
S6: and flattening and cleaning.
The preparation method of the single crystal SiC/Si wafer substrate adopts photoetching to SiO 2 The layer is patterned to form a layer of SiO 2 The silicon single crystal SiC layer is selectively grown on the Si substrate, the density of misfit dislocation in a lattice mismatched system can be reduced, and the defect density of the single crystal SiC/Si heterostructure can be reduced. In addition, by adjusting the process parameters of the annealing operation, the geometry and thickness of the SiC cell region can be determined, thus enabling optimization of circuit performance according to the positioning of the device. In an embodiment, localized annealing, e.g., laser thermal annealing with very high energy to decompose a solid carbon source, may be employed, and the irradiated regions of the Si substrate will undergo melting and recrystallization in a very short period of time, faster material homogenization in selective regions may be achieved relative to conventional annealing processes, and localized annealing under ambient conditions may mitigate the accumulation of thermal mismatch at the junctions.
The method of making the patterned single crystal SiC/Si wafer substrate will be described in detail below with reference to the method flow diagram of fig. 1 and the schematic structural diagram of the various stages.
Specifically, at step S1, shown in fig. 3, a Si substrate 110 is provided, the Si substrate 110 having a (111) crystal plane orientation.
As shown in FIG. 4, siO is deposited on the surface of the Si substrate 110 at step S2 2 Layer 120, deposited SiO 2 Layer 120 may have a thickness greater than 0.1 μm, for example, a thickness from 0.1 μm to 5 μm. For preparing SiO 2 Examples of processes for layers may include chemical vapor deposition (LPCVD), ultra-high vacuum chemical vapor deposition (UHCVD), plasma enhanced chemical vapor deposition (pecvd)Deposition (PECVD) or High Density Plasma Chemical Vapor Deposition (HDPCVD).
Next, referring to fig. 5, a patterning step is performed at step S3, at SiO 2 A photomask is applied to layer 120 and etched to form a plurality of recesses 130, the bottoms of recesses 130 exposing Si substrate material, thereby resulting in a patterned Si substrate.
Subsequently, at step S4, a carbon source is introduced into the patterned Si substrate 110 to form a carbon-containing material layer in the groove 130. In an embodiment, examples of the carbon source according to the present embodiment may include polymethyl methacrylate (PMMA), C60, CVD carbon layer, or similar carbon-containing material, wherein PMMA may be applied onto the patterned Si substrate 110 using a spin coating method.
Next, referring to FIG. 5, an annealing process is performed that anneals the carbon-containing material layer such that the carbon-containing material layer contacts the Si substrate material at the bottom of the recess 130 and grows a SiC layer 140 without SiC growing on SiO 2 I.e., the upper surface of spacer 124. By the reaction of SiO 2 The side wall surrounds the groove to selectively grow the single crystal SiC layer at the bottom of the groove, so that defect expansion caused by lattice mismatch and thermal expansion coefficient mismatch can be reduced, mismatch dislocation can be reduced, and defects at the interface of the single crystal SiC and Si can be reduced. Examples of the annealing process employed according to the present embodiment may include furnace annealing, rapid thermal annealing. In an embodiment, the recess 130 may be locally annealed, for example, using a laser-based technique to apply a shaped high-energy laser beam to the recess 130 region of the Si substrate 110 to locally anneal a previously deposited carbon-containing material layer on the Si substrate 110. Because the semiconductor is locally annealed with high-energy laser light, the absorbed laser energy is directly converted into heat, and by this pyrolysis, high-energy laser light with a threshold above the melting of the material can cause a higher solubility in the solid phase, which can more quickly homogenize the material. The laser source may be a KrF excimer laser (λ =248 nm), and the localized irradiation of the layer of carbon-containing material with a shorter wavelength laser may achieve surface properties without altering the bulk region propertiesLocal modification of the texture. The laser light is scanned across the substrate at a rate to form a single crystal SiC layer 140 in the recess 130 of the Si substrate 110, and the SiC cell region 142 can have a thickness from 0.1 μm to 10 μm, depending on the application of the SiC/Si wafer base. In the present embodiment, the thickness on the SiC unit region can be determined by controlling the energy and the scanning rate of the laser light; that is, the annealing time is appropriately increased to obtain a thicker SiC layer.
Subsequently, the carbon-containing material layer remaining on the upper surface of the spacer 124 may be removed, and the annealed substrate surface may be treated, for example, using a Chemical Mechanical Polishing (CMP) method to remove the remaining carbon layer, and obtain a planarized SiC surface, as shown in fig. 6.
As a second embodiment, the present invention provides a method of fabricating a wafer substrate of a patterned GaN/SiC heterostructure, comprising the steps of:
s1: a Si substrate is provided.
S2: deposition of SiO on Si substrates 2 And (3) a layer.
S3: to SiO 2 The layer is patterned to form a layer on the SiO 2 The layer forms a plurality of grooves.
S4: a layer of carbonaceous material is formed in the recess.
S5: and forming a SiC layer in the groove through an annealing process.
S6: and flattening and cleaning.
S7: and depositing a GaN layer on the patterned SiC/Si wafer substrate.
S8: and flattening and cleaning.
Referring to steps S1 to S6 in the first embodiment, a patterned SiC/Si wafer substrate may be formed. At step S7 after step S6, a GaN layer may be formed on the entire patterned Si substrate 110 by Metal Organic Chemical Vapor Deposition (MOCVD). The patterned SiC/Si wafer substrate includes a plurality of SiC cell regions 142 and SiO separating the SiC cell regions 2 A side wall 122. In this embodiment, the MOCVD epitaxial growth process may be a two-step process including; firstly, a GaN nucleation layer is formed at a low temperature of 500-800 ℃ to effectively improve the subsequent processThe crystal quality of the high temperature grown GaN thin film is then raised to 900-1100 ℃ to form a high quality GaN layer on the GaN nucleation layer. The GaN layer 250 may include a GaN stack including a thick GaN layer and an AlGaN barrier layer. In one embodiment, the precursors used to deposit the GaN layer may include a nitrogen source and an organic vapor material including aluminum and gallium, for example, the nitrogen source is NH 3 The aluminum-containing organic vapor phase material is trimethylaluminum (TMAl), and the gallium-containing organic vapor phase material is trimethylgallium (TMGa). In an embodiment, the GaN layer may further include a GaN buffer layer disposed between the single crystal SiC layer 140 and the GaN layer 250 to adjust stress balance in the epitaxial film.
Referring to fig. 7, at step S8, selective removal of polycrystalline SiO is performed 2 A step of depositing a GaN layer on the surface, leaving a GaN layer 250 overlying the single crystal SiC layer 140, thereby forming a plurality of GaN/SiC unit regions 252 on the Si substrate. For example, a Chemical Mechanical Polishing (CMP) process may be used to remove the polycrystalline SiO 2 The deposited GaN layer 250.
The invention also provides a patterned single crystal SiC/Si wafer substrate. Referring to FIG. 2, which isbase:Sub>A schematic structural view ofbase:Sub>A patterned single crystal SiC/Si wafer substrate according to the present invention, FIG. 6 can bebase:Sub>A partial view of the patterned single crystal SiC/Si wafer substrate of FIG. 2 taken along section A-A'. The wafer base of single crystal SiC/Si has a Si substrate 110 with a crystal orientation (111), the Si substrate 110 has a plurality of patterned cell regions 142 formed thereon, the plurality of cell regions are spaced apart from each other by spacers 124, and each cell region 142 includes: a single crystal SiC layer formed on the respective cell regions. The SiC cell region may have a smooth rounded polygon, ellipse, circle, or the like for reducing defect growth at the edge of the region. Depending on the device application, the size of the cell region may be the same and not exceed the size of currently available SiC substrates, e.g., not exceeding 4 inches. The smaller the size of the SiC cell region, the less stress and fewer defects are present in the grown SiC layer. In some embodiments, the single crystal SiC can be any of 3C-SiC or 4H-SiC.
In another aspect, the present invention also provides a patterned GaN/SiC/Si heterostructure wafer substrate, which may include a patterned single crystal SiC/Si wafer substrate as previously described, and each unit region may include a GaN stack, which may include a GaN layer and an AlGaN barrier layer. In an embodiment, the GaN stack further includes a GaN buffer layer disposed between the SiC layer and the GaN layer.
In addition, the single crystal SiC/Si wafer substrate can be used for manufacturing improved SiC-based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, the preparation method of the patterned single crystal SiC/Si wafer substrate provides a plurality of SiC unit areas selectively grown on a large-size substrate, the SiC unit areas are heterogeneously grown on the large-size Si substrate, and SiC type power devices, such as MOSFET devices, prepared on the basis of the high-quality SiC/Si wafer substrate can realize the performance optimization and high yield of the devices.
The wafer substrate of the single crystal GaN/SiC/Si heterostructure can be used for manufacturing an improved GaN High Electron Mobility Transistor (HEMT) device, the preparation method of the wafer substrate of the patterned single crystal GaN/SiC/Si heterostructure provides a high-quality and crack-free AlGaN/GaN heterostructure, the AlGaN/GaN heterostructure is epitaxially grown on a SiC unit region 142, lattice mismatch and thermal expansion mismatch are reduced, and a GaN type power device, especially a HEMT device, prepared based on the high-quality AlGaN/GaN heterostructure can achieve performance optimization, high yield and cost benefit of the device. As shown in fig. 9, a side cross-sectional view of a HEMT structure based on the single crystal GaN/SiC heterostructure, the AlGaN/GaN heterostructure based HEMT device may include: the structure comprises a substrate, a SiC layer, a GaN stack 350, a gate metal 360, a source metal 370 and a drain metal 380, wherein the GaN stack 350 comprises a GaN buffer layer 352, a GaN hetero-layer 354 and an AlGaN barrier layer 356, the gate metal 360 is located between the source metal 370 and the drain metal 380, the source metal 370 and the drain metal 380 are in ohmic contact with the AlGaN barrier layer 356, the gate metal 360 is in Schottky contact with the AlGaN barrier layer 356, and the gate metal 360 is used for controlling the density of two-dimensional electron gas formed by the GaN hetero-layer 354 and the AlGaN barrier layer 356.
In summary, the method for preparing a single crystal SiC/Si wafer substrate of the present invention at least includes: providing a Si substrate; depositing SiO on the Si substrate 2 Layer of and on said SiO 2 Patterning a layer to form a pattern on the SiO 2 A plurality of grooves are formed in the layer, the grooves being formed of SiO surrounding the periphery thereof 2 The side wall is defined, and the Si substrate is exposed from the bottom of the groove; forming a layer of carbonaceous material in the recess; reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove; and removing the residual carbon-containing material layer by a chemical mechanical polishing process to form a plurality of SiO 2 A sidewall separated SiC cell region. The preparation method provided by the invention can grow high-quality single crystal SiC and GaN on the large-size substrate, and the obtained wafer substrate structure has high quality and low defect density, so that power devices with SiC or GaN as the substrate can be respectively manufactured by using the large-size Si wafer substrate, and the yield can be improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (19)

1. A method for producing a single crystal SiC/Si wafer substrate, characterized by comprising at least:
providing a Si substrate;
depositing SiO on the Si substrate 2 Layer of and on said SiO 2 Patterning a layer to form a patterned layer on the SiO 2 A plurality of grooves are formed in the layer, the grooves being formed of SiO surrounding the periphery thereof 2 A sidewall is defined, and the Si substrate is exposed from the bottom of the groove;
forming a layer of carbonaceous material in the recess;
reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove; and
removing the residual carbon-containing material layer by chemical mechanical polishing process to form a plurality of SiO-based layers 2 A sidewall separated SiC cell region.
2. The method of producing a single-crystal SiC/Si wafer substrate according to claim 1, characterized in that: the annealing process includes furnace annealing or rapid thermal annealing.
3. The method of producing a single-crystal SiC/Si wafer substrate according to claim 1, characterized in that: the annealing process is a laser-based local annealing process.
4. The method of producing a single-crystal SiC/Si wafer substrate according to claim 1, characterized in that: the SiC cell region has a size of less than or equal to 4 inches.
5. The method of producing a single-crystal SiC/Si wafer substrate according to claim 1, characterized in that: the SiC unit area is in a shape of a smooth rounded polygon, an ellipse, a circle or a combination of the above.
6. The method of producing a single-crystal SiC/Si wafer substrate according to claim 1, characterized in that: the thickness of the SiC unit area is from 0.1um to 10um.
7. The method of producing a single-crystal SiC/Si wafer substrate according to claim 1, characterized in that: the layer of carbonaceous material comprises a layer of carbon formed by spin-on polymethylmethacrylate or by chemical vapor deposition.
8. A patterned single crystal SiC/Si wafer substrate, characterized in that the wafer substrate comprises at least:
a Si substrate on which a plurality of patterned cell regions are formed, the plurality of cell regions being spaced apart from each other by spacers, and each cell region including a single crystal SiC layer formed on the corresponding cell region.
9. The patterned single crystal SiC/Si wafer substrate of claim 8, wherein: the spacer includes silicon dioxide or a void.
10. The patterned single crystal SiC/Si wafer substrate of claim 8, wherein: the single crystal SiC is 3C-SiC or 4H-SiC.
11. A SiC based metal oxide semiconductor field effect transistor formed on the basis of the patterned single crystal SiC/Si wafer substrate of any of claims 8-10.
12. A method for preparing a patterned single crystal GaN/SiC/Si heterostructure wafer substrate, characterized in that it comprises at least:
providing a Si substrate;
depositing SiO on the Si substrate 2 Layer of and to the SiO 2 Patterning a layer to form a patterned layer on the SiO 2 A plurality of grooves are formed in the layer, the grooves being formed of SiO surrounding the periphery thereof 2 The side wall is limited, and the Si substrate is exposed at the bottom of the groove;
forming a layer of carbonaceous material in the recess; reacting the carbon-containing material layer with the Si substrate exposed in the groove by an annealing process to selectively grow a single crystal SiC layer at the bottom of the groove;
by chemical meansRemoving the residual carbon-containing material layer by mechanical polishing process to form SiO 2 A sidewall-separated SiC cell region;
continuing to deposit a GaN stack on the patterned SiC/Si wafer substrate, the GaN stack including a GaN layer and an AlGaN barrier layer; and
removing the SiO by a chemical mechanical polishing process 2 A GaN stack on the surface.
13. The method of preparing a patterned single crystal GaN/SiC/Si heterostructure wafer substrate according to claim 12, wherein: the GaN stack further includes a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.
14. The method of preparing a patterned single crystal GaN/SiC/Si heterostructure wafer substrate according to claim 12, wherein: depositing the GaN stack by performing a MOCVD epitaxial growth process, the MOCVD epitaxial growth process comprising: forming a GaN nucleation layer at a temperature of 500-800 ℃; and forming a GaN epitaxial layer at a temperature of 900-1100 ℃.
15. The method of preparing a patterned single crystal GaN/SiC/Si heterostructure wafer substrate according to claim 12, wherein: precursors for depositing the GaN stack include NH as a nitrogen source 3 And organic vapor phase materials containing aluminum and gallium.
16. The method of preparing a patterned single crystal GaN/SiC/Si heterostructure wafer substrate of claim 15, wherein: the aluminum-containing organic vapor phase material is trimethylaluminum (TMAl) and the gallium-containing organic vapor phase material is trimethylgallium (TMGa).
17. A patterned single crystal GaN/SiC/Si heterostructure wafer substrate, comprising at least:
a Si substrate on which a plurality of patterned unit regions are formed, the plurality of unit regions being spaced apart from each other by spacers, and each unit region including:
a single crystal SiC layer formed on the respective cell regions; and
a GaN stack including a GaN layer and an AlGaN barrier layer.
18. The patterned single crystal GaN/SiC/Si heterostructure wafer substrate of claim 17, wherein: the GaN stack further includes a GaN buffer layer disposed between the single crystal SiC layer and the GaN layer.
19. A GaN-based high electron mobility transistor formed based on the patterned single crystal GaN/SiC/Si heterostructure wafer substrate of any of claims 17-18.
CN202110619695.1A 2021-06-03 2021-06-03 Single crystal SiC/Si wafer substrate, heterostructure and preparation method thereof Pending CN115440573A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117438391A (en) * 2023-12-18 2024-01-23 北京青禾晶元半导体科技有限责任公司 High-thermal-conductivity 3C-SiC polycrystalline substrate and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117438391A (en) * 2023-12-18 2024-01-23 北京青禾晶元半导体科技有限责任公司 High-thermal-conductivity 3C-SiC polycrystalline substrate and preparation method thereof
CN117438391B (en) * 2023-12-18 2024-03-15 北京青禾晶元半导体科技有限责任公司 High-thermal-conductivity 3C-SiC polycrystalline substrate and preparation method thereof

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