CN111583873B - Pixel circuit and driving method thereof - Google Patents
Pixel circuit and driving method thereof Download PDFInfo
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- CN111583873B CN111583873B CN202010531850.XA CN202010531850A CN111583873B CN 111583873 B CN111583873 B CN 111583873B CN 202010531850 A CN202010531850 A CN 202010531850A CN 111583873 B CN111583873 B CN 111583873B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
A pixel circuit and a driving method thereof, wherein the pixel circuit includes: arranged to drive a light emitting element, the pixel circuit includes: a light emission driving sub-circuit and a duration control sub-circuit; the light-emitting element is a micro organic light-emitting diode; a light-emitting driving sub-circuit which is respectively electrically connected with the first scanning signal terminal, the first data signal terminal, the first power terminal and the first node and is configured to provide a driving current to the first node under the control of the first scanning signal terminal and the first data signal terminal; the time length control sub-circuit is respectively connected with the second scanning signal end, the third scanning signal end, the first initial signal end, the second data signal end, the first node and the second node and is set to provide the driving current of the first node for the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end; and a light emitting element connected to the second node and the second power source terminal, respectively.
Description
Technical Field
The present disclosure relates to but not limited to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof.
Background
Micro Organic Light-Emitting diodes (Micro-OLEDs for short) are Micro displays developed in recent years, and are also called silicon-based OLEDs. The Micro-OLED can not only realize active addressing of pixels, but also can realize preparation of a plurality of functional circuits such as a time sequence control (TCON) circuit, an over-current protection (OCP) circuit and the like on a silicon substrate, thereby being beneficial to reducing the system volume and realizing light weight. The Micro-OLED is prepared by adopting a mature Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process, has the advantages of small volume, high resolution (Pixels Per Inc, PPI for short), high refresh rate and the like, and is widely applied to the field of near-eye display of Virtual Reality (VR) or Augmented Reality (AR).
Currently, the Micro-OLED drives pixels to emit light by using an AMOLED driving method. Compared with an Active Matrix Organic Light-Emitting Diode (AMOLED), the silicon-based OLED has the advantages that the size of a pixel is small, the required driving current of the pixel is small, particularly the driving current of a low gray scale and a medium gray scale is small, the display unevenness of the Micro-OLED can be caused by the existing driving method of the Micro-OLED, and the display effect of the Micro-OLED is further influenced.
Disclosure of Invention
The disclosure provides a pixel circuit and a driving method thereof, which can avoid the phenomenon of nonuniform display of a Micro-OLED and improve the display effect of the Micro-OLED.
In a first aspect, the present disclosure provides a pixel circuit arranged to drive a light emitting element, the pixel circuit comprising: a light emission driving sub-circuit and a duration control sub-circuit; the light-emitting element is a micro organic light-emitting diode;
the light-emitting driving sub-circuit is respectively electrically connected with the first scanning signal terminal, the first data signal terminal, the first power supply terminal and the first node, and is arranged to provide driving current for the first node under the control of the first scanning signal terminal and the first data signal terminal;
the time length control sub-circuit is respectively connected with the second scanning signal end, the third scanning signal end, the first initial signal end, the second data signal end, the first node and the second node, and is set to provide the driving current of the first node for the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end;
the light emitting elements are respectively connected with the second node and a second power supply end.
In one possible implementation, the pixel circuit further includes: a reset sub-circuit;
the reset sub-circuit is respectively connected with the reset signal end, the second initial signal end and the second node and is set to provide the signal of the second initial signal end for the second node under the control of the reset signal end.
In one possible implementation, the anode of the light emitting element is connected to the second node, and the cathode of the light emitting element is connected to the second power supply terminal.
In one possible implementation, the light emission driving sub-circuit includes: the circuit comprises a first transistor, a second transistor and a first capacitor, wherein the second transistor is a driving transistor;
a control electrode of the first transistor is connected with a first scanning signal end, a first electrode of the first transistor is connected with a first data signal end, and a second electrode of the first transistor is connected with a third node;
a control electrode of the second transistor is connected with a third node, a first electrode of the second transistor is connected with a first power supply end, and a second electrode of the second transistor is connected with a first node;
the first end of the first capacitor is connected with a third node, and the second end of the first capacitor is connected with a first power supply end.
In one possible implementation, the duration control sub-circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a second capacitor;
a control electrode of the third transistor is connected with a second scanning signal end, a first electrode of the third transistor is connected with a first initial signal end, and a second electrode of the third transistor is connected with a fourth node;
a control electrode of the fourth transistor is connected with a third scanning signal end, a first electrode of the fourth transistor is connected with a second data signal end, and a second electrode of the fourth transistor is connected with a fourth node;
a control electrode of the fifth transistor is connected with a fourth node, a first electrode of the fifth transistor is connected with a first node, and a second electrode of the fifth transistor is connected with a second node;
and the first end of the second capacitor is connected with a fourth node, and the second end of the second capacitor is connected with a second node.
In one possible implementation, the reset sub-circuit includes: a sixth transistor;
and the control electrode of the sixth transistor is connected with the reset signal end, the first electrode of the sixth transistor is connected with the second initial signal end, and the second electrode of the sixth transistor is connected with the second node.
In one possible implementation, the pixel circuit further includes: a reset sub-circuit; the light emission driving sub-circuit includes: the circuit comprises a first transistor, a second transistor and a first capacitor, wherein the second transistor is a driving transistor; the duration control sub-circuit comprises: a third transistor, a fourth transistor, a fifth transistor, and a second capacitor; the reset sub-circuit includes: a sixth transistor;
a control electrode of the first transistor is connected with a first scanning signal end, a first electrode of the first transistor is connected with a first data signal end, and a second electrode of the first transistor is connected with a third node;
a control electrode of the second transistor is connected with a third node, a first electrode of the second transistor is connected with a first power supply end, and a second electrode of the second transistor is connected with a first node;
the first end of the first capacitor is connected with a third node, and the second end of the first capacitor is connected with a first power supply end;
a control electrode of the third transistor is connected with a second scanning signal end, a first electrode of the third transistor is connected with a first initial signal end, and a second electrode of the third transistor is connected with a fourth node;
a control electrode of the fourth transistor is connected with a third scanning signal end, a first electrode of the fourth transistor is connected with a second data signal end, and a second electrode of the fourth transistor is connected with a fourth node;
a control electrode of the fifth transistor is connected with a fourth node, a first electrode of the fifth transistor is connected with a first node, and a second electrode of the fifth transistor is connected with a second node;
a first end of the second capacitor is connected with a fourth node, and a second end of the second capacitor is connected with a second node;
and the control electrode of the sixth transistor is connected with the reset signal end, the first electrode of the sixth transistor is connected with the second initial signal end, and the second electrode of the sixth transistor is connected with the second node.
In a possible implementation manner, when the signal of the first scanning signal terminal is an active level signal, the signal of the second scanning signal terminal and the signal of the third scanning signal terminal are inactive level signals, when the signal of the second scanning signal terminal is an active level signal, the signal of the first scanning signal terminal and the signal of the third scanning signal terminal are inactive level signals, and when the signal of the third scanning signal terminal is an active level signal, the signal of the first scanning signal terminal and the signal of the second scanning signal terminal are inactive level signals.
In a possible implementation manner, when the signal of the second scan signal terminal is an active level signal, the signal of the first initial signal terminal is a signal that makes the fifth transistor in a conducting state; when the signal of the third scan signal terminal is an active level signal, the signal of the second data signal terminal is a signal which turns off the fifth transistor.
In a possible implementation manner, when the signal of the reset signal terminal is an active level signal, a difference between a voltage value of the signal of the second initial signal terminal and a voltage value of the signal of the second power terminal is smaller than a turn-on voltage of the light emitting element.
In a second aspect, the present disclosure also provides a driving method of a pixel circuit, configured to drive the pixel circuit, the method including:
the light-emitting driving sub-circuit supplies a driving current to the first node under the control of the first scanning signal terminal and the first data signal terminal;
the time length control sub-circuit provides the driving current of the first node to the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end.
In one possible implementation, the method further includes:
the reset sub-circuit provides a signal of a second initial signal terminal to the second node under the control of the reset signal terminal.
The present disclosure provides a pixel circuit and a driving method thereof, the pixel circuit being configured to drive a light emitting element, the pixel circuit including: a light emission driving sub-circuit and a duration control sub-circuit; the light-emitting element is a micro organic light-emitting diode; a light-emitting driving sub-circuit which is respectively electrically connected with the first scanning signal terminal, the first data signal terminal, the first power terminal and the first node and is configured to provide a driving current to the first node under the control of the first scanning signal terminal and the first data signal terminal; the time length control sub-circuit is respectively connected with the second scanning signal end, the third scanning signal end, the first initial signal end, the second data signal end, the first node and the second node and is set to provide the driving current of the first node for the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end; and a light emitting element connected to the second node and the second power source terminal, respectively. According to the technical scheme, the time length control sub-circuit can avoid the phenomenon of uneven display of the Micro-OLED by controlling the light emitting time length of the light emitting element, and the display effect of the Micro-OLED is improved.
Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. Other advantages of the disclosure may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.
Drawings
The accompanying drawings are included to provide an understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.
Fig. 1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a pixel circuit provided in an exemplary embodiment;
fig. 3 is an equivalent circuit diagram of a light emission driving sub-circuit provided by an exemplary embodiment;
FIG. 4 is an equivalent circuit diagram of a duration control sub-circuit provided by an exemplary embodiment;
FIG. 5 is an equivalent circuit diagram of a reset sub-circuit provided in an exemplary embodiment;
fig. 6 is an equivalent circuit diagram of a pixel circuit provided by an exemplary embodiment;
FIG. 7 is a timing diagram illustrating operation of a pixel circuit according to an exemplary embodiment;
fig. 8 is a flowchart of a driving method of a pixel circuit according to an embodiment of the disclosure.
Detailed Description
The present disclosure describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of the embodiments described in this disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.
The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure that have been disclosed may also be combined with any conventional features or elements to form a technical solution as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other aspects to form yet another aspect defined by the claims. Thus, it should be understood that any features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
Unless otherwise defined, technical or scientific terms used in the disclosure of the present disclosure should have the ordinary meaning as understood by those of ordinary skill in the art to which the disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The source and drain of the switching transistor used in all embodiments of the present disclosure are symmetrical, so the source and drain can be interchanged. In the embodiments of the present disclosure, in order to separate two poles of the switching transistor except for the gate, the source thereof is referred to as a first pole, the drain thereof is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistor employed by the embodiments of the present disclosure includes: the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 1, a pixel circuit provided by an embodiment of the present disclosure is configured to drive a light emitting element, and includes: a light emission driving sub-circuit and a duration control sub-circuit. The light-emitting element is a Micro OLED (organic light-emitting diode).
And a light emission driving sub-circuit electrically connected to the first scan signal terminal G1, the first Data signal terminal Data1, the first power source terminal VDD, and the first node N1, respectively, and configured to supply a driving current to the first node N1 under the control of the first scan signal terminal G1 and the first Data signal terminal Data 1. And the time length control sub-circuit is respectively connected with the second scanning signal terminal G2, the third scanning signal terminal G3, the first Initial signal terminal Initial1, the second Data signal terminal Data2, the first node N1 and the second node N2, and is arranged to provide the driving current of the first node N1 to the second node N2 under the control of the second scanning signal terminal G2, the third scanning signal terminal G3, the first Initial signal terminal Initial1 and the second Data signal terminal Data 2.
And light emitting elements connected to the second node N2 and a second power source terminal VSS, respectively.
In one exemplary embodiment, the pixel circuit is disposed on a micro OLED display panel including a plurality of pixels each including one light emitting element.
In one exemplary embodiment, the first power source terminal VDD continuously supplies a high-level signal, and the second power source terminal VSS continuously supplies a low-level signal.
In an exemplary embodiment, the signals of the first scan signal terminal G1, the second scan signal terminal G2, and the third scan signal terminal G3 are all pulse signals.
In an exemplary embodiment, the signals of the first Data signal terminal Data1 and the second Data signal terminal Data2 are pulse signals.
In an exemplary embodiment, the signal of the first Initial signal terminal Initial1 may be a pulse signal, or may be a constant voltage signal.
The light-emitting duration of the light-emitting element can be controlled by controlling signals of the second scanning signal end, the first initial signal end, the third scanning signal end and the second data signal end, the light-emitting duration of the light-emitting element can be controlled to be shorter when the pixel displays a low gray scale, and the light-emitting duration of the light-emitting element can be controlled to be longer when the pixel displays a high gray scale.
The pixel circuit provided by the embodiment of the present disclosure is configured to drive a light emitting element, and includes: a light emission driving sub-circuit and a duration control sub-circuit; the light-emitting element is a micro organic light-emitting diode; a light-emitting driving sub-circuit which is respectively electrically connected with the first scanning signal terminal, the first data signal terminal, the first power terminal and the first node and is configured to provide a driving current to the first node under the control of the first scanning signal terminal and the first data signal terminal; the time length control sub-circuit is respectively connected with the second scanning signal end, the third scanning signal end, the first initial signal end, the second data signal end, the first node and the second node and is set to provide the driving current of the first node for the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end; and a light emitting element connected to the second node and the second power source terminal, respectively. According to the technical scheme, the time length control sub-circuit can avoid the phenomenon of uneven display of the Micro-OLED by controlling the light emitting time length of the light emitting element, and the display effect of the Micro-OLED is improved.
Fig. 2 is a schematic structural diagram of a pixel circuit according to an exemplary embodiment. As shown in fig. 2, an exemplary embodiment provides the pixel circuit further including: and a reset sub-circuit.
A Reset sub-circuit, connected to the Reset signal terminal Reset, the second Initial signal terminal Initial2 and the second node N2, respectively, is configured to provide the signal of the second Initial signal terminal Initial2 to the second node N2 under the control of the Reset signal terminal Reset.
The reset sub-circuit can initialize the anode of the light-emitting element to ensure the normal light emission of the light-emitting element.
In an exemplary embodiment, the signals of the Reset signal terminal Reset are all pulse signals.
In an exemplary embodiment, when the signal of the Reset signal terminal Reset is an active level signal, a voltage difference between the signal of the second Initial signal terminal Initial2 and the signal of the second power source terminal VSS is less than a turn-on voltage of the light emitting element. The voltage difference between the signal of the second initialization signal terminal initialization 2 and the signal of the second power source terminal VSS is smaller than the turn-on voltage of the light emitting element, so that the light emitting element is prevented from emitting light when the anode of the light emitting element is initialized.
In an exemplary embodiment, the signal of the second Initial signal terminal Initial2 may be a pulse signal, or may be a constant voltage signal.
In one exemplary embodiment, as shown in fig. 1 and 2, the anode of the light emitting element is connected to the second node N2, and the cathode of the light emitting element is connected to the second power source terminal VSS.
Fig. 3 is an equivalent circuit diagram of a light emission driving sub-circuit provided in an exemplary embodiment. As shown in fig. 3, in an exemplary embodiment, the light emission driving sub-circuit includes: a first transistor M1, a second transistor M2 and a first capacitor C1, the second transistor M2 is a driving transistor.
A control electrode of the first transistor M1 is connected to the first scan signal terminal G1, a first electrode of the first transistor M1 is connected to the first Data signal terminal Data1, and a second electrode of the first transistor M1 is connected to the third node N3; a control electrode of the second transistor M2 is connected to the third node N3, a first electrode of the second transistor M2 is connected to the first power terminal VDD, and a second electrode of the second transistor M2 is connected to the first node N1; a first terminal of the first capacitor C1 is connected to the third node N3, and a second terminal of the first capacitor C1 is connected to the first power source terminal VDD.
The first transistor M1 and the second transistor M2 are switching transistors.
Fig. 3 shows an exemplary structure of the light emission driving sub-circuit, and those skilled in the art will readily understand that the implementation of the light emission driving sub-circuit is not limited thereto as long as the function thereof can be achieved.
Fig. 4 is an equivalent circuit diagram of the duration control sub-circuit provided in an exemplary embodiment. As shown in fig. 4, in an exemplary embodiment, the duration control sub-circuit includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a second capacitor C2.
A control electrode of the third transistor M3 is connected to the second scan signal terminal G2, a first electrode of the third transistor M3 is connected to the first Initial signal terminal Initial1, and a second electrode of the third transistor M3 is connected to the fourth node N4;
a control electrode of the fourth transistor M4 is connected to the third scan signal terminal G3, a first electrode of the fourth transistor M4 is connected to the second Data signal terminal Data2, and a second electrode of the fourth transistor M4 is connected to the fourth node N4; a control electrode of the fifth transistor M5 is connected to the fourth node N4, a first electrode of the fifth transistor M5 is connected to the first node N1, and a second electrode of the fifth transistor M5 is connected to the second node N2; the first terminal of the second capacitor C2 is connected to the fourth node N4, and the second terminal of the second capacitor C2 is connected to the second node N2.
The third transistor M3, the fourth transistor M4, and the fifth transistor M5 are switching transistors.
In an exemplary embodiment, the second terminal of the second capacitor C2 may be further connected to the second power supply terminal VSS, or may be connected to the ground terminal, which is not limited in the embodiments of the present disclosure.
Fig. 4 shows an exemplary structure of the duration control sub-circuit, and those skilled in the art will readily understand that the implementation of the duration control sub-circuit is not limited thereto as long as the function thereof can be realized.
Fig. 5 is an equivalent circuit diagram of a reset sub-circuit provided in an exemplary embodiment. As shown in fig. 5, in one exemplary embodiment, the reset sub-circuit includes: and a sixth transistor M6.
A control electrode of the sixth transistor M6 is connected to the Reset signal terminal Reset, a first electrode of the sixth transistor M6 is connected to the second Initial signal terminal Initial2, and a second electrode of the sixth transistor M6 is connected to the second node N2.
Fig. 5 shows an exemplary structure of the reset sub-circuit, and those skilled in the art will readily understand that the implementation of the reset sub-circuit is not limited thereto as long as the function thereof can be realized.
Fig. 6 is an equivalent circuit diagram of a pixel circuit provided in an exemplary embodiment. As shown in fig. 6, in an exemplary embodiment, a pixel circuit includes: a light-emitting drive sub-circuit, a duration control sub-circuit and a reset sub-circuit. The light emission driving sub-circuit includes: a first transistor M1, a second transistor M2 and a first capacitor C1, the second transistor M2 being a driving transistor; the duration control sub-circuit comprises: a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a second capacitor C2; the reset sub-circuit includes: and a sixth transistor M6.
A control electrode of the first transistor M1 is connected to the first scan signal terminal G1, a first electrode of the first transistor M1 is connected to the first Data signal terminal Data1, and a second electrode of the first transistor M1 is connected to the third node N3; a control electrode of the second transistor M2 is connected to the third node N3, a first electrode of the second transistor M2 is connected to the first power terminal VDD, and a second electrode of the second transistor M2 is connected to the first node N1; a first terminal of the first capacitor C1 is connected to the third node N3, and a second terminal of the first capacitor C1 is connected to the first power source terminal VDD; a control electrode of the third transistor M3 is connected to the second scan signal terminal G2, a first electrode of the third transistor M3 is connected to the first Initial signal terminal Initial1, and a second electrode of the third transistor M3 is connected to the fourth node N4; a control electrode of the fourth transistor M4 is connected to the third scan signal terminal G3, a first electrode of the fourth transistor M4 is connected to the second Data signal terminal Data2, and a second electrode of the fourth transistor M4 is connected to the fourth node N4; a control electrode of the fifth transistor M5 is connected to the fourth node N4, a first electrode of the fifth transistor M5 is connected to the first node N1, and a second electrode of the fifth transistor M5 is connected to the second node N2; a first terminal of the second capacitor C2 is connected to the fourth node N4, and a second terminal of the second capacitor C2 is connected to the second node N2; a control electrode of the sixth transistor M6 is connected to the Reset signal terminal Reset, a first electrode of the sixth transistor M6 is connected to the second Initial signal terminal Initial2, and a second electrode of the sixth transistor M6 is connected to the second node N2; a control electrode of the seventh transistor M7 is connected to the light emission control terminal, a first electrode of the seventh transistor M7 is connected to the second node N2, and a second electrode of the seventh transistor M7 is connected to the anode of the light emitting element.
In one exemplary embodiment, the transistors T1 through T6 may be N-type thin film transistors, or may be P-type thin film transistors.
In an exemplary embodiment, all transistors are of the same type, so that the process flow can be unified, the process procedures can be reduced, and the yield of products can be improved. In addition, all transistors may be low temperature polysilicon thin film transistors in consideration of a small leakage current of the low temperature polysilicon thin film transistors.
In an exemplary embodiment, when the signal of the first scan signal terminal G1 is an active level signal, the signal of the second scan signal terminal G2 and the signal of the third scan signal terminal G3 are inactive level signals, when the signal of the second scan signal terminal G2 is an active level signal, the signal of the first scan signal terminal G1 and the signal of the third scan signal terminal G3 are inactive level signals, and when the signal of the third scan signal terminal G3 is an active level signal, the signal of the first scan signal terminal G1 and the signal of the second scan signal terminal G2 are inactive level signals. That is, the signal at the first scanning signal terminal G1, the signal at the second scanning signal terminal G2, and the signal at the third scanning signal terminal G3 are not active level signals at the same time. Here, the active level signal refers to a signal for turning on the transistor, and the inactive level signal refers to a signal for turning off the transistor.
In an exemplary embodiment, when the signal of the second scan signal terminal G2 is an active level signal, the signal of the first Initial signal terminal Initial1 is a signal that makes the fifth transistor M5 in a turn-on state; when the signal of the third scan signal terminal G3 is an active level signal, the signal of the second Data signal terminal Data2 is a signal that turns off the fifth transistor M5. The timing at which the fifth transistor M5 is in an on state and the timing at which the fifth transistor M5 is in an off state determine the light emission time of the light emitting element.
The pixel circuit provided by one exemplary embodiment is explained below by the operation process of the pixel circuit.
Taking the transistors T1 to T6 in the pixel circuit provided by an exemplary embodiment as P-type thin film transistors as an example, fig. 7 is an operation timing diagram of the pixel circuit provided by an exemplary embodiment. As shown in fig. 6 and 7, an exemplary embodiment provides a pixel circuit including: 6 transistors (T1 to T6), 2 capacitance units (C1 and C2), 8 input terminals (G1, G2, G3, Data1, Data2, Initial1, Initial2 and Reset) and 2 power supply terminals (VDD and VSS).
The first power terminal VDD continuously provides a high level signal; the second power source terminal VSS continuously supplies a low level signal. The second transistor T2 is a driving transistor, and the transistors other than the second transistor T2 are switching transistors.
An exemplary embodiment provides a pixel circuit operating process including:
in the first stage S1, i.e., the Reset stage, the Reset signal terminal Reset of the input terminals and the input signal of the second Initial signal terminal Initial2 are low level signals, and the input signals of the first scan signal terminal G1, the second scan signal terminal G2, the third scan signal terminal G3, the first Data signal terminal Data1, the second Data signal terminal Data2 and the first Initial signal terminal Initial1 are high level signals.
In S1, the input signal of the Reset signal terminal Reset is a low level signal, the sixth transistor T6 is turned on, and the input signal of the second Initial signal terminal Initial2 is written into the second node N2 to Reset the anode of the Micro OLED. At this time, the Micro OLED does not emit light.
In the second stage S2, the input signals of the second scan signal terminal G2 and the first Initial signal terminal Initial1 are low level signals, and the input signals of the first scan signal terminal G1, the third scan signal terminal G3, the first Data signal terminal Data1, the second Data signal terminal Data2, the Reset signal terminal Reset and the second Initial signal terminal Initial2 are high level signals.
In S2, the input signal of the second scan signal terminal G2 is a low level signal, the third transistor T3 is turned on, the input signal of the first Initial signal terminal Initial1 is written into the fourth node N4, and the second capacitor C2 starts to be charged. Since the input signal of the first Initial signal terminal Initial1 is a low level signal, the fifth transistor T5 is turned on, and the level of the signal of the first node N1 is the same as the level of the second node N2. At this time, the Micro OLED does not emit light.
In the third stage S3, i.e., the light emitting stage, the input signals of the first scan signal terminal G1 and the first Data signal terminal Data1 among the input terminals are low level signals, and the input signals of the second scan signal terminal G2, the third scan signal terminal G3, the second Data signal terminal Data2, the Reset signal terminal Reset, the first Initial signal terminal Initial1, and the second Initial signal terminal Initial2 are high level signals.
In S3, although the input signal at the second scan signal terminal G2 is a high level signal and the third transistor T3 is turned off, the fourth node N4 is still at a low level under the bootstrap action of the second capacitor C2 and the fifth transistor T5 is still turned on. The input signal of the first scan signal terminal G1 is a low level signal, the first transistor T1 is turned on, the input signal of the first Data signal terminal Data1 is written into the third node N3, and the first capacitor C1 starts to charge. Since the input signal of the first Data signal terminal Data1 is a low level signal, the third node N3 is a low level, and the second transistor T2 is turned on, at this time, the Micro OLED emits light.
In the fourth stage S4, the input signals of the first scan signal terminal G1, the second scan signal terminal G2, the third scan signal terminal G3, the first Data signal terminal Data1, the second Data signal terminal Data2, the Reset signal terminal Reset, the first Initial signal terminal Initial1, and the second Initial signal terminal Initial2 among the input terminals are high level signals.
In S4, although the input signal of the first scan signal terminal G1 is a high level signal and the first transistor T1 is turned off, the third node N3 is still at a low level under the bootstrap action of the first capacitor C1, the second transistor T2 is still turned on, and at this time, the Micro OLED still emits light.
In the fifth stage S5, the input signals of the third scan signal terminal G3 and the second Data signal terminal Data2 are low level signals, and the input signals of the first scan signal terminal G1, the second scan signal terminal G2, the first Data signal terminal Data1, the Reset signal terminal Reset, the first Initial signal terminal Initial1 and the second Initial signal terminal Initial2 are high level signals.
In S5, the input signal of the third scan signal terminal G3 is a low level signal, the fourth transistor T4 is turned on, the input signal of the second Data signal terminal Data2 is written into the fourth node N4, and the fifth transistor T5 is turned off because the input signal of the second Data signal terminal Data2 is a high level signal, at which time the Micro OLED stops emitting light.
As can be seen from the above analysis, the on time and the off time of the fifth transistor T5 determine the light emitting time of the Micro OLED.
The embodiment of the disclosure further provides a driving method of a pixel circuit, and fig. 8 is a flowchart of the driving method of the pixel circuit provided by the embodiment of the disclosure. As shown in fig. 8, a driving method of a pixel circuit provided by the embodiment of the present disclosure includes the following steps:
in step 100, the light-emitting driving sub-circuit provides a driving current to the first node under the control of the first scan signal terminal and the first data signal terminal.
The pixel circuit is the pixel circuit provided in any of the foregoing embodiments, and the implementation principle and the implementation effect are similar, and are not described herein again.
In one exemplary embodiment, the driving method of the pixel circuit further includes: the reset sub-circuit provides a signal of a second initial signal terminal to the second node under the control of the reset signal terminal.
The drawings in this disclosure relate only to the structures to which the embodiments of the disclosure relate, and other structures may refer to general designs.
Although the embodiments disclosed in the present disclosure are described above, the descriptions are only for the convenience of understanding the present disclosure, and are not intended to limit the present disclosure. It will be understood by those skilled in the art of the present disclosure that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure, and that the scope of the disclosure is to be limited only by the terms of the appended claims.
Claims (11)
1. A pixel circuit arranged to drive a light emitting element, the pixel circuit comprising: a light emission driving sub-circuit and a duration control sub-circuit; the light-emitting element is a micro organic light-emitting diode;
the light-emitting driving sub-circuit is respectively electrically connected with the first scanning signal terminal, the first data signal terminal, the first power supply terminal and the first node, and is arranged to provide driving current for the first node under the control of the first scanning signal terminal and the first data signal terminal;
the time length control sub-circuit is respectively connected with the second scanning signal end, the third scanning signal end, the first initial signal end, the second data signal end, the first node and the second node, and is set to provide the driving current of the first node for the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end;
the duration control sub-circuit comprises: a third transistor, a fourth transistor, a fifth transistor, and a second capacitor;
a control electrode of the third transistor is connected with a second scanning signal end, a first electrode of the third transistor is connected with a first initial signal end, and a second electrode of the third transistor is connected with a fourth node;
a control electrode of the fourth transistor is connected with a third scanning signal end, a first electrode of the fourth transistor is connected with a second data signal end, and a second electrode of the fourth transistor is connected with a fourth node;
a control electrode of the fifth transistor is connected with a fourth node, a first electrode of the fifth transistor is connected with a first node, and a second electrode of the fifth transistor is connected with a second node;
a first end of the second capacitor is connected with a fourth node, and a second end of the second capacitor is connected with a second node;
the light emitting elements are respectively connected with the second node and a second power supply end.
2. The pixel circuit according to claim 1, further comprising: a reset sub-circuit;
the reset sub-circuit is respectively connected with the reset signal end, the second initial signal end and the second node and is set to provide the signal of the second initial signal end for the second node under the control of the reset signal end.
3. The pixel circuit according to claim 1 or 2, wherein an anode of the light emitting element is connected to the second node, and a cathode of the light emitting element is connected to a second power supply terminal.
4. The pixel circuit according to claim 1, wherein the light emission driving sub-circuit comprises: the circuit comprises a first transistor, a second transistor and a first capacitor, wherein the second transistor is a driving transistor;
a control electrode of the first transistor is connected with a first scanning signal end, a first electrode of the first transistor is connected with a first data signal end, and a second electrode of the first transistor is connected with a third node;
a control electrode of the second transistor is connected with a third node, a first electrode of the second transistor is connected with a first power supply end, and a second electrode of the second transistor is connected with a first node;
the first end of the first capacitor is connected with a third node, and the second end of the first capacitor is connected with a first power supply end.
5. The pixel circuit of claim 2, wherein the reset sub-circuit comprises: a sixth transistor;
and the control electrode of the sixth transistor is connected with the reset signal end, the first electrode of the sixth transistor is connected with the second initial signal end, and the second electrode of the sixth transistor is connected with the second node.
6. The pixel circuit according to claim 1, further comprising: a reset sub-circuit; the light emission driving sub-circuit includes: the circuit comprises a first transistor, a second transistor and a first capacitor, wherein the second transistor is a driving transistor; the duration control sub-circuit comprises: a third transistor, a fourth transistor, a fifth transistor, and a second capacitor; the reset sub-circuit includes: a sixth transistor;
a control electrode of the first transistor is connected with a first scanning signal end, a first electrode of the first transistor is connected with a first data signal end, and a second electrode of the first transistor is connected with a third node;
a control electrode of the second transistor is connected with a third node, a first electrode of the second transistor is connected with a first power supply end, and a second electrode of the second transistor is connected with a first node;
the first end of the first capacitor is connected with a third node, and the second end of the first capacitor is connected with a first power supply end;
a control electrode of the third transistor is connected with a second scanning signal end, a first electrode of the third transistor is connected with a first initial signal end, and a second electrode of the third transistor is connected with a fourth node;
a control electrode of the fourth transistor is connected with a third scanning signal end, a first electrode of the fourth transistor is connected with a second data signal end, and a second electrode of the fourth transistor is connected with a fourth node;
a control electrode of the fifth transistor is connected with a fourth node, a first electrode of the fifth transistor is connected with a first node, and a second electrode of the fifth transistor is connected with a second node;
a first end of the second capacitor is connected with a fourth node, and a second end of the second capacitor is connected with a second node;
and the control electrode of the sixth transistor is connected with the reset signal end, the first electrode of the sixth transistor is connected with the second initial signal end, and the second electrode of the sixth transistor is connected with the second node.
7. The pixel circuit according to claim 6, wherein the signal of the second scan signal terminal and the signal of the third scan signal terminal are inactive level signals when the signal of the first scan signal terminal is an active level signal, the signal of the first scan signal terminal and the signal of the third scan signal terminal are inactive level signals when the signal of the second scan signal terminal is an active level signal, and the signal of the first scan signal terminal and the signal of the second scan signal terminal are inactive level signals when the signal of the third scan signal terminal is an active level signal.
8. The pixel circuit according to claim 7, wherein when the signal of the second scan signal terminal is an active level signal, the signal of the first initial signal terminal is a signal for turning on the fifth transistor; when the signal of the third scan signal terminal is an active level signal, the signal of the second data signal terminal is a signal which turns off the fifth transistor.
9. The pixel circuit according to claim 2, wherein when the signal of the reset signal terminal is an active level signal, a difference between a voltage value of the signal of the second initialization signal terminal and a voltage value of the signal of the second power source terminal is smaller than a turn-on voltage of the light emitting element.
10. A method of driving a pixel circuit, arranged to drive a pixel circuit as claimed in any one of claims 1 to 9, the method comprising:
the light-emitting driving sub-circuit supplies a driving current to the first node under the control of the first scanning signal terminal and the first data signal terminal;
the time length control sub-circuit provides the driving current of the first node to the second node under the control of the second scanning signal end, the third scanning signal end, the first initial signal end and the second data signal end.
11. The method of claim 10, further comprising:
the reset sub-circuit provides a signal of a second initial signal terminal to the second node under the control of the reset signal terminal.
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| CN114360435A (en) * | 2020-09-28 | 2022-04-15 | 京东方科技集团股份有限公司 | Pixel circuit, pixel driving method and display device |
| CN117859167A (en) * | 2022-06-21 | 2024-04-09 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof, display substrate and display device |
| CN117897759A (en) * | 2022-07-21 | 2024-04-16 | 京东方科技集团股份有限公司 | Pixel driving circuit and driving method, display panel and display device |
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