CN111580428A - Instruction sending circuit - Google Patents
Instruction sending circuit Download PDFInfo
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- CN111580428A CN111580428A CN202010357248.9A CN202010357248A CN111580428A CN 111580428 A CN111580428 A CN 111580428A CN 202010357248 A CN202010357248 A CN 202010357248A CN 111580428 A CN111580428 A CN 111580428A
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- Prior art keywords
- module
- instruction
- signal
- power supply
- latch
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The application discloses instruction transmitting circuit, this circuit includes: the device comprises a secondary power supply module, an instruction generation module and a latch module; the input end of the secondary power supply module is connected with a bus power supply, and the output end of the secondary power supply module is connected with the instruction generation module and the latch module, and is used for converting an electric signal output by the bus power supply and supplying power to the instruction generation module and the latch module; the instruction generating module is arranged between the secondary power supply module and the latch module and used for generating an instruction signal and a chip selection signal and sending the instruction signal and the chip selection signal to the latch module; and the latch module is used for judging whether the instruction signal is a wrong instruction signal or not under the control of the chip selection signal and filtering the wrong instruction signal. The technical problems of poor stability and reliability of the instruction sending circuit in the prior art are solved.
Description
Technical Field
The application relates to the technical field of instruction sending control of electronic equipment, in particular to an instruction sending circuit.
Background
The reliability design of instruction transmission is an important component in the technical field of reliability, and how to ensure the stability, reliability, credibility, anti-interference performance and anti-mistransmission of instruction signals in the design process of an instruction transmission circuit is a key point of attention in various fields in recent years. The instruction sending circuit is widely applied to electronic equipment design, has a simple structure and can better realize instruction sending.
Fig. 1 is a schematic diagram of a conventional command transmitting circuit. As shown in fig. 1, the bus power supply supplies power to the single chip microcomputer after passing through the secondary power supply module, the instruction output IO port of the single chip microcomputer is directly connected to the instruction execution module, and the instruction outputs a level signal through the IO port of the single chip microcomputer to directly control the instruction execution module to work, although the instruction transmission circuit has a simple structure and is easy to implement; on one hand, however, because the load carrying capacity of the IO port of the single chip microcomputer is limited, when the instruction execution module is at different temperatures, the load carrying capacity required for execution changes, so that the load carrying capacity of the IO port of the single chip microcomputer cannot meet the load carrying requirement under severe conditions, and the instruction cannot be executed, thereby causing the instruction execution capacity of the instruction transmission circuit in the prior art to be poor; on the other hand, when the IO port of the single chip microcomputer is interfered, the instruction output IO port is easily interfered and presents an unstable state, and the instruction output is not judged to be directly connected with the instruction execution module, so that the instruction is mistakenly sent and executed under the condition of interference; on the other hand, when the bus power supply fluctuates and the single chip microcomputer is restarted due to instant power failure, the single chip microcomputer has an instable state at the instant of power-on, and the state of the instruction sending IO port is unstable, so that the instruction is sent out by mistake and executed by mistake. Therefore, in the prior art, the stability and reliability of the instruction sending circuit are poor due to the limited loading capacity of the single-chip microcomputer IO port or the easy unstable state of the single-chip microcomputer IO port.
Disclosure of Invention
The technical problem that this application was solved is: aiming at the problems of poor stability and poor reliability of the instruction sending circuit in the prior art, the instruction sending circuit is provided, the latch module is arranged behind the instruction generating module in the instruction sending circuit, and the latch module is used for judging and filtering the error instruction signal of the instruction signal generated by the instruction generating module, so that the instruction sending circuit is prevented from sending the generated error instruction signal to the instruction executing module, and the reliability of the instruction sending circuit is improved.
In a first aspect, an embodiment of the present application provides an instruction sending circuit, including: the device comprises a secondary power supply module, an instruction generation module and a latch module; wherein the content of the first and second substances,
the input end of the secondary power supply module is connected with the bus power supply, and the output end of the secondary power supply module is connected with the instruction generation module and the latch module, and is used for converting the electric signal output by the bus power supply and supplying power to the instruction generation module and the latch module;
the instruction generating module is arranged between the secondary power supply module and the latch module and used for generating an instruction signal and a chip selection signal and sending the instruction signal and the chip selection signal to the latch module;
and the latch module is used for judging whether the instruction signal is a wrong instruction signal or not under the control of the chip selection signal and filtering the wrong instruction signal.
According to the scheme provided by the embodiment of the application, the latch module is arranged behind the instruction generating module in the instruction sending circuit, and the latch module is used for judging and filtering the error instruction signal of the instruction signal generated by the instruction generating module, so that the instruction sending circuit is prevented from sending the generated error instruction signal to the instruction executing module, and the reliability of the instruction sending circuit is further improved.
Optionally, the instruction sending circuit further includes: a buffer module; wherein the content of the first and second substances,
the buffer module is connected with the secondary power supply module, the instruction generating module and the latch module, arranged between the instruction generating module and the latch module, and used for enhancing the instruction signal output by the instruction generating module and sending the enhanced instruction signal to the latch module.
In the scheme provided by the embodiment of the application, the buffer module is arranged between the instruction generating module and the latch module in the instruction sending circuit, and the instruction signal generated by the instruction generating module is enhanced through the buffer module, so that the loading capacity of the instruction signal is improved, and the stability and the reliability of the instruction sending circuit are further improved.
Optionally, the buffer module is a bidirectional buffer.
Optionally, the instruction sending circuit further includes: an anti-false-sending module; wherein the content of the first and second substances,
the false-sending prevention module is arranged between the secondary power supply module and the latch module and used for enabling the latch module after the output voltage of the secondary power supply module is stable.
According to the scheme provided by the embodiment of the application, the anti-false-sending module is arranged between the secondary power supply module and the latch module in the instruction sending circuit, and the latch module is enabled after the output voltage of the secondary power supply module is stable through the anti-false-sending module, so that the false instruction sending during power-on or after power-off restarting is avoided, and the reliability of the instruction sending circuit is improved.
Optionally, the mis-sending prevention module comprises: the circuit comprises a capacitor, a diode, a first resistor and a second resistor; wherein the content of the first and second substances,
the anode of the capacitor is connected with the output end of the secondary module, the cathode of the capacitor is connected with the cathode of the diode and one end of the second resistor; the anode of the diode is connected with one end of the first resistor; the other ends of the first resistor and the second resistor are grounded.
Optionally, the parameters of the capacitor, the first resistor and the second resistor satisfy the following relationship:
5*R1*C1≤t1
R2*C1≥t2
wherein R is1Represents a resistance value of the first resistor; r2Represents the resistance value of the second resistor; c1A capacitance value representing the capacitance; t is t1Representing a power-on time of the instruction generation module; t is t2Indicating the time at which the instruction generation module is initialized.
Optionally, the chip selection signal includes a first pulse signal and a second pulse signal, where the first pulse signal and the second pulse signal are both high-level pulse signals, and a time interval between the first pulse signal and the second pulse signal is equal to a duration of the instruction signal.
Optionally, the instruction generating module is a single chip microcomputer, an ARM chip or a digital signal processor DSP.
Optionally, the latch module is a tri-state output latch.
Optionally, the output voltage range of the secondary power supply module is 5V ± 1V.
Drawings
FIG. 1 is a circuit diagram of a conventional instruction issue circuit according to an embodiment of the present disclosure;
FIG. 2 is a circuit diagram of an instruction issue circuit according to an embodiment of the present disclosure;
Detailed Description
In order to better understand the technical solutions, the technical solutions of the present application are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present application are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application, and the technical features in the embodiments and examples of the present application may be combined with each other without conflict.
Referring to fig. 2, an embodiment of the present application provides an instruction transmitting circuit, including: the device comprises a secondary power supply module 1, an instruction generation module 2 and a latch module 3; wherein the content of the first and second substances,
the input end of the secondary power supply module 1 is connected with a bus power supply, and the output end of the secondary power supply module is connected with the instruction generation module 2 and the latch module 3, and is used for converting an electric signal output by the bus power supply and supplying power to the instruction generation module 2 and the latch module 3;
the instruction generating module 2 is arranged between the secondary power supply module 1 and the latch module 3, and is configured to generate an instruction signal and a chip selection signal, and send the instruction signal and the chip selection signal to the latch module 3;
and the latch module 3 is used for judging whether the instruction signal is a wrong instruction signal or not under the control of the chip selection signal and filtering the wrong instruction signal.
Specifically, the secondary power module 1 is a module for converting the bus power supply electric energy into electric energy of another form or specification, for example, converting a direct current voltage into an alternating current voltage to obtain a high voltage direct current voltage; the secondary power supply module is an important component of the emergency power supply and is also an important component of the aircraft power supply system. In the scheme provided by the embodiment of the application, after the secondary power supply module 1 converts the bus power supply electric energy into electric energy of another form or specification, the electric energy is uniformly supplied to the instruction generation module 2 and the latch module 3 through the output end.
In one possible implementation, the output voltage of the secondary power supply module 1 is in a range of 5V ± 1V.
Further, the instruction generating module 2 is disposed between the secondary power supply module 1 and the latch module 3, and an output end of the instruction generating module is connected to an input end of the latch module 3. When the secondary power supply module 1 powers up the instruction generating module 2, the instruction generating module 2 starts to work, generates an instruction signal and a chip selection signal, and sends the instruction signal and the chip selection signal to the latch module 3. Specifically, in the solution provided in the embodiment of the present application, the instruction generating module 2 has multiple types, and the following description takes several preferred types as examples.
In a possible implementation manner, the instruction generation module is a single chip, an ARM chip or a digital signal processor DSP.
In one possible implementation manner, the chip selection signal includes a first pulse signal and a second pulse signal, where the first pulse signal and the second pulse signal are both high-level pulse signals, and a time interval between the first pulse signal and the second pulse signal is equal to a duration of the instruction signal.
Further, in the solution provided in the embodiment of the present application, an input end of the latch module 3 is connected to an output end of the instruction generating module 2, and an output end of the latch module 3 is connected to an external instruction executing module. The latch module 3 is preset with a judgment program for instruction sending, when the secondary power module 1 powers up the latch module 3 and the latch module 3 receives the instruction signal and the chip selection signal sent by the instruction generating module 2, the latch module 3 calls and executes the preset judgment program under the control of the chip selection signal to judge whether the current instruction signal is a wrong instruction signal, if so, the instruction signal is filtered, otherwise, the instruction signal is sent to an external instruction execution module, so that the instruction execution module executes corresponding operation according to the instruction signal. Specifically, in the solution provided in the embodiment of the present application, there are various kinds of latch modules 3, and a preferred example is described below.
In one possible implementation, the latch module 3 is a tri-state output latch.
Specifically, in the solution provided in the embodiment of the present application, the tri-state output latch may be an eight-bit tri-state output latch, and may also be a tri-state output latch with other bits, which is not limited herein.
Further, the loading capacity of the command signal output by the command generating module 2 is enhanced. The instruction transmission circuit further includes: a buffer module 4; wherein the content of the first and second substances,
the buffer module 4 is connected to the secondary power supply module 1, the instruction generation module 2, and the latch module 3, and is disposed between the instruction generation module 2 and the latch module 3, and configured to perform enhancement processing on the instruction signal output by the instruction generation module 2, and send the enhanced instruction signal to the latch module 3.
In one possible implementation, the buffer module 4 is a bidirectional buffer.
In the scheme provided by the embodiment of the application, the buffer module 4 is arranged between the instruction generating module 2 and the latch module 3 in the instruction sending circuit, and the instruction signal generated by the instruction generating module is enhanced through the buffer module 4, so that the loading capacity of the instruction signal is improved, and the stability and the reliability of the instruction sending circuit are further improved.
Further, in order to prevent the wrong instruction transmission at the moment of power-on or after the restart of power failure, and improve the reliability of the output of the instruction transmission circuit, the instruction transmission circuit further comprises: an anti-false-sending module 5; wherein the content of the first and second substances,
the false triggering prevention module 5 is arranged between the secondary power supply module 1 and the latch module 3, and is used for enabling the latch module 3 after the output voltage of the secondary power supply module 1 is stable.
In a possible manner, the anti-missending module 5 comprises: a capacitor 51, a diode 52, a first resistor 53, and a second resistor 54; wherein the content of the first and second substances,
the anode of the capacitor 51 is connected to the output end of the secondary module 1, and the cathode of the capacitor 51 is connected to the cathode of the diode 52 and one end of the second resistor 54; an anode of the diode 52 is connected to one end of the first resistor 53; the other ends of the first resistor 53 and the second resistor 54 are both grounded.
In a possible implementation manner, the parameters of the capacitor 51, the first resistor 53 and the second resistor 54 satisfy the following relationship:
5*R1*C1≤t1
R2*C1≥t2
wherein R is1Represents the resistance value of the first resistor 53; r2Represents the resistance value of the second resistor 54; c1Represents the capacitance value of the capacitor 51; t is t1Represents the power-on time of the instruction generation module 2; t is t2Indicating the time at which the instruction generation module 2 is initialized.
Specifically, in the solution provided in the embodiment of the present application, an output end of the secondary power supply module 1 is connected to a positive end of a capacitor 51, a negative end of the capacitor 51 is connected to a cathode of a diode 52, an anode of the diode 52 is connected to one end of a first resistor 53, the other end of the first resistor 53 is connected to ground, a negative end of the capacitor 51 is connected to one end of a second resistor 54, the false triggering prevention module 5 is connected to an enable port of the latch module 3, and the other end of the second resistor 54 is connected to ground; the voltage of the enabling port of the latch module 3 is slowly reduced from high level to low level and the low level is kept stable after the bus power supply is powered on, the high level of the enabling port can keep the high resistance state of the latch module 3 in the process that the high level is slowly reduced to the low level, an instruction sending access is blocked in the power-on process, instruction missending and messy sending caused by the instable state of the instruction sending port of the single chip microcomputer at the moment of power-on are avoided, and the power supply interference resistance of the instruction sending is realized. The anode of the diode 52 and the first resistor 53 are grounded in series, the cathode of the diode 52 is connected with the negative end of the capacitor 51 to form a power-down capacitor 51 voltage recovery circuit, voltage recovery balance between the two polar plates of the capacitor 51 at the moment of power down is connected with the ground, the capacitor 51 can be started up slowly when power is supplied again, instruction missending in the process of power-down, power-up and restarting at the moment of power down is avoided, and reliability and anti-power interference capability of the instruction sending circuit are further enhanced.
In the scheme provided by the embodiment of the application, the latch module 3 is arranged behind the instruction generating module 2 in the instruction sending circuit, and the latch module 3 is used for distinguishing and filtering the instruction signal generated by the instruction generating module 2, so that the instruction sending circuit is prevented from sending the generated error instruction signal to the instruction executing module, and the reliability of the instruction sending circuit is further improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. An instruction issue circuit, comprising: the device comprises a secondary power supply module, an instruction generation module and a latch module; wherein the content of the first and second substances,
the input end of the secondary power supply module is connected with the bus power supply, and the output end of the secondary power supply module is connected with the instruction generation module and the latch module, and is used for converting the electric signal output by the bus power supply and supplying power to the instruction generation module and the latch module;
the instruction generating module is arranged between the secondary power supply module and the latch module and used for generating an instruction signal and a chip selection signal and sending the instruction signal and the chip selection signal to the latch module;
and the latch module is used for judging whether the instruction signal is a wrong instruction signal or not under the control of the chip selection signal and filtering the wrong instruction signal.
2. The circuit of claim 1, wherein the instruction issue circuit further comprises: a buffer module; wherein the content of the first and second substances,
the buffer module is connected with the secondary power supply module, the instruction generating module and the latch module, arranged between the instruction generating module and the latch module, and used for enhancing the instruction signal output by the instruction generating module and sending the enhanced instruction signal to the latch module.
3. The circuit of claim 2, wherein the buffer module is a bi-directional buffer.
4. The circuit of claim 1, wherein the instruction issue circuit further comprises: an anti-false-sending module; wherein the content of the first and second substances,
the false-sending prevention module is arranged between the secondary power supply module and the latch module and used for enabling the latch module after the output voltage of the secondary power supply module is stable.
5. The circuit of claim 4, wherein the anti-misinterpretation module comprises: the circuit comprises a capacitor, a diode, a first resistor and a second resistor; wherein the content of the first and second substances,
the anode of the capacitor is connected with the output end of the secondary module, the cathode of the capacitor is connected with the cathode of the diode and one end of the second resistor; the anode of the diode is connected with one end of the first resistor; the other ends of the first resistor and the second resistor are grounded.
6. The circuit of claim 5, wherein parameters of the capacitance, the first resistance, and the second resistance satisfy the following relationship:
5*R1*C1≤t1
R2*C1≥t2
wherein R is1Represents a resistance value of the first resistor; r2Represents the resistance value of the second resistor; c1A capacitance value representing the capacitance; t is t1Representing a power-on time of the instruction generation module; t is t2Indicating the time at which the instruction generation module is initialized.
7. The circuit of any one of claims 1 to 6, wherein the chip select signal comprises a first pulse signal and a second pulse signal, wherein the first pulse signal and the second pulse signal are both high-level pulse signals, and a time interval between the first pulse signal and the second pulse signal is equal to a duration of the command signal.
8. The circuit of any one of claims 1-6, wherein the instruction generation module is a single chip, an ARM chip, or a Digital Signal Processor (DSP).
9. A circuit as claimed in any one of claims 1 to 6, wherein said latch module is a tristate output latch.
10. The circuit according to any one of claims 1 to 6, wherein the output voltage range of the secondary power supply module is 5V ± 1V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010357248.9A CN111580428B (en) | 2020-04-29 | 2020-04-29 | Instruction sending circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010357248.9A CN111580428B (en) | 2020-04-29 | 2020-04-29 | Instruction sending circuit |
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| CN111580428A true CN111580428A (en) | 2020-08-25 |
| CN111580428B CN111580428B (en) | 2022-07-29 |
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