Specific embodiment
Below in conjunction with attached drawing, the invention will be further described.
Fig. 1 is the system composition block diagram of auto compensating type AC voltage regulator, and analog-to-digital conversion coding unit is to AC power source electricity
Pressure carries out voltage sample, the output voltage grade encoded radio P2 after analog-to-digital conversion;Delay protection unit input voltage grade coding
Value P2, exports the voltage class encoded radio P3 after postponing and trigger region does not control signal P4;After interlocking control unit input delay
Voltage class encoded radio P3 and not trigger region control signal P4, export Trig control signal P5;Trigger unit is according to input
Trig control signal P5 issues trigger signal P6 to auto compensating type main circuit, controls the logical of thyristor in thyristor switch group
It is disconnected;Error detection control unit judges whether the Trig control signal P5 of input is effective Trig control signal, and according to judging result
Protection control signal is issued to auto compensating type main circuit, thyristor switch group is protected.
Fig. 2 is auto compensating type main circuit embodiment 1, including compensator transformer TB1 and auto-transformer TB2, and 6 two-way
Thyristor SR1-SR6 collectively constitutes thyristor switch group, and fuse FU1 and relay normally open switch KA-1, relay is normally closed opens
It closes KA-2 and forms relay protection circuit.
In Fig. 2, the bucking coil of compensator transformer TB1 is connected in phase line, and phase line input terminal is L1, output end L2.
Voltage on TB1 magnet exciting coil is controlled by thyristor switch group.Auto-transformer TB2 has 3 output tap C1, C2, C3, two-way
One end of TB1 magnet exciting coil, the other end point of SR1, SR3, SR5 are connected to after one end of thyristor SR1, SR3, SR5 are in parallel
It is not connected to tap C1, C2, C3;TB1 magnet exciting coil is connected in addition after one end of bidirectional thyristor SR2, SR4, SR6 are in parallel
One end, the other end of SR2, SR4, SR6 are then respectively connected to tap C1, C2, C3.If auto-transformer TB2 tap C1, C2
Between output voltage U12 it is different from the output voltage U23 between C2, C3, then thyristor switch group be up to forward direction U12, forward direction
U23, forward direction U12+U23, reversed U12, reversed U23, reversed U12+U23 totally 6 kinds of magnet exciting coil voltage compensation working conditions, it is additional
0 voltage compensation working condition when a kind of input voltage is within normal range (NR), the AC power source electricity of phase line input terminal L1 input
Enough be at most divided into 7 voltage ranges compensates control to pressure energy.In Fig. 2, N is zero curve, and G11, G12 to G61, G62 are respectively
The trigger signal input terminal of bidirectional thyristor SR1 to SR6.In Fig. 2, the ipsilateral brilliant lock of bidirectional thyristor SR1, SR3, SR5 composition
Pipe, bidirectional thyristor SR2, SR4, SR6 form another ipsilateral thyristor;To avoid short circuit, cannot have 2 simultaneously in ipsilateral thyristor
A and 2 or more thyristors simultaneously turn on;For example, SR1, SR3 cannot be simultaneously turned on, SR4, SR6 cannot be simultaneously turned on, etc.
Deng.
Fig. 3 is auto compensating type main circuit embodiment 2, including compensator transformer TB1 and auto-transformer TB2, and 8 two-way
Thyristor SR1-SR8 collectively constitutes thyristor switch group, and fuse FU1 and relay normally open switch KA-1, relay is normally closed opens
It closes KA-2 and forms relay protection circuit.
In Fig. 3, the bucking coil of compensator transformer TB1 is connected in phase line, and phase line input terminal is L1, output end L2.
Voltage on TB1 magnet exciting coil is controlled by thyristor switch group.Auto-transformer TB2 has 4 outputs tap C1, C2, C3, C4,
One end of TB1 magnet exciting coil, SR1, SR3, SR5, SR7 are connected to after one end of bidirectional thyristor SR1, SR3, SR5, SR7 are in parallel
Other end be respectively connected to tap C1, C2, C3, C4;It is connected after one end of bidirectional thyristor SR2, SR4, SR6, SR8 are in parallel
To the other end of TB1 magnet exciting coil, the other end of SR2, SR4, SR6, SR8 be then respectively connected to tap C1, C2, C3,
C4.If the output voltage U12 between auto-transformer TB2 tap C1, C2, the output voltage U23 between C2, C3, the output between C3, C4
Voltage U34 is respectively different, then thyristor switch group includes forward direction U12, forward direction U23, forward direction U34, forward direction U12+U23, forward direction U23
+ U34, forward direction U12+U23+U34, reversed U12, reversed U23, reversed U34, reversed U12+U23, reversed U23+U34, reversed U12
+ U23+U34 totally 12 kinds of magnet exciting coil voltage compensation working conditions, 0 electricity when a kind of additional input voltage is within normal range (NR)
Compensation work state is pressed, the AC supply voltage of phase line input terminal L1 input can be divided into most 13 voltage ranges and be mended
Repay control.In Fig. 3, N is zero curve, and G11, G12 to G81, G82 are respectively the trigger signal input of bidirectional thyristor SR1 to SR8
End.In Fig. 3, bidirectional thyristor SR1, SR3, SR5, SR7 form ipsilateral thyristor, bidirectional thyristor SR2, SR4, SR6, SR8 group
At another ipsilateral thyristor;To avoid short circuit, cannot there is 2 and 2 or more thyristors in ipsilateral thyristor simultaneously while leading
It is logical;For example, SR1, SR7 cannot be simultaneously turned on, and SR4, SR8 cannot be simultaneously turned on, etc..
Each bidirectional thyristor in Fig. 2, Fig. 3 can be substituted with the unidirectional thyristor of 2 reverse parallel connections.Fig. 2, Fig. 3
In, relay normally open switch and relay normally closed switch composition relay protection switch.
Fig. 4 is analog-to-digital conversion coding unit embodiment 1.In Fig. 4, FD1 is that real available value detects device LTC1966,
LTC1966 and transformer TV1, capacitor CV1, capacitor CV2, resistance RV1, resistance RV2 constitute RMS to DC circuit, to from phase line
The AC supply voltage virtual value of L1 and zero curve N input measures, and obtains AC supply voltage sampled value U1.LTC1966's
UIN1, UIN2 are alternating voltage difference input terminal, and USS is the negative supply input terminal that can be grounded, and UDD is positive power input,
GND is ground terminal, and EN is that low level effectively enables control signal, and UOUT is voltage output end, and COM is output voltage return
End.
In Fig. 4, FD2 is biproduct parting A/D converter ICL7109, for by AC supply voltage waving interval range
Voltage divides into voltage class section and is converted to the voltage class encoded radio output of binary system composition.In Fig. 4, ICL7109's
Operation/holding end RUN, low byte enable end LBEN, test lead TEST connect high level, chip select terminal CE/LOAD, mode end MODE,
High byte enable end HBEN, oscillator selection end OSC SEL connect low level, and work is continuing (i.e. automatic to repeat) conversion regime
And the direct output mode of high byte;Crystal oscillator XT1 is connected to the oscillator input OSC IN and oscillator output end of ICL7109
OSC OUT;One end connection composition integrating circuit of integrating capacitor C11, integrating resistor R11, automatic zero set capacitor C12, in addition one
End is respectively connected to the integrating capacitor end INT, buffer output end BUF, automatic zero set capacitance terminal AZ of ICL7109;ICL7109
Differential Input high-end IN HOL input ac power voltage sample value U1, Differential Input low side IN LO be connected to reference voltage
Output end REF OUT;Resistance RF1, resistance RF2 divide reference voltage, and la tension de reference Uref est, Uref are obtained on resistance RF2
It is input to reference voltage positive input terminal REF IN+ and reference voltage negative input end REF IN-;Reference capacitance C13 is connected to reference
Capacitor positive input terminal REF CAP+ and reference capacitance negative input end REF CAP-;The V+ of ICL7109 is positive power source terminal, is connected to electricity
Source+VCC;The V- of ICL7109 is negative power end, is connected to power supply-VCC;The GND of ICL7109 is digital ground terminal, and COMMON is mould
Quasi- ground terminal, is connected to publicly GND.
If the AC supply voltage fluctuation range of input is 220V ± 10%, it is desirable that implemented using auto compensating type main circuit
Example 1 is stablized to be exported in the range of 220V ± 2%, and AC supply voltage waving interval range is 242V to 198V, at this time
Using the analog-to-digital conversion coding unit embodiment 1 of Fig. 4, input can be divided into section voltage in 242V to the voltage between 198V
Size is 7 voltage class sections of 6.4V, and the voltage in 3 voltage class sections therein is higher than desired output voltage model
It encloses, needs to carry out drop compensation;The voltage in 3 voltage class sections boosts lower than desired output voltage range
Compensation;1 voltage class section carries out 0 voltage compensation, i.e. uncompensation within desired output voltage range.The electricity of 6.4V
It is not more than 220V ± 1.5% between pressure area, meets requirement of the output control within 220V ± 2%;7 voltage class of 6.4V
The corresponding AC supply voltage waving interval in section is 242.4V to 197.6V, covers the range actually fluctuated.Using Fig. 2
Auto compensating type main circuit embodiment 1 compensates, and the output voltage U12 of auto-transformer TB2 is low, U23 high;Voltage U23
It is 2 times of voltage U12;Then the input voltage of auto-transformer TB2 is alternating current 220V, and the excitation of TB1 is only made of output voltage U12
When coil voltage, TB1 offset voltage is 6.4V;The input voltage of auto-transformer TB2 is alternating current 220V, only uses output voltage
When U23 does the magnet exciting coil voltage of TB1, TB1 offset voltage is 12.8V;The input voltage of auto-transformer TB2 is exchange
220V, while when doing using output voltage U12, U23 the magnet exciting coil voltage of TB1, TB1 offset voltage is 19.2V.In Fig. 4,
ICL7109 carries out A/D conversion to from the differential voltage between Differential Input high-end IN HOL and Differential Input low side IN LO;
The corresponding practical AC supply voltage waving interval in 7 voltage class sections of 6.4V is 242.4V to 197.6V, covers reality
The range of border fluctuation;Reference voltage Ucp that Differential Input low side IN LO is inputted, being exported from reference voltage output end REF OUT
It should be corresponding with the lower bound theoretical value 197.6V of AC supply voltage waving interval range;Accordingly, it is determined that the change of transformer TV1
Than the intrinsic standoff ratio with resistance RV1, resistance RV2, it should when AC supply voltage is lower bound theoretical value 197.6V, make AC power source
Voltage sample value U1 is equal to the reference voltage Ucp of reference voltage output end REF OUT output.In Fig. 4, analog-to-digital conversion coding unit
The voltage class encoded radio P2 of output by exported from ICL7109 highest 4 B12, B11, B10, B9 data Y14, Y13, Y12,
Y11 composition;One-to-one 7 voltage class in 7 voltage class sections encode from low to high for Y14, Y13, Y12, Y11 and voltage
Value is 0000,0001,0010,0011,0100,0101,0110 respectively, is realized by adjusting the size of la tension de reference Uref est.
Adjust la tension de reference Uref est size method first is that: demarcation voltage of the AC supply voltage in 2 voltage class sections of highest
When fluctuating up and down at 236V, adjusting (adjusts) intrinsic standoff ratio of resistance RF1, resistance RF2, makes the numerical value of Y14, Y13, Y12, Y11
It is fluctuated between 0110 and 0101;Adjust la tension de reference Uref est size method second is that: set Ux and exist as AC supply voltage
When the teachings fluctuation of 197.6V to 242.4V, inputted from Differential Input high-end IN HOL and Differential Input low side IN LO
Voltage change range has
The variation range of Ux corresponds to 7 minimum code values of B12, B11, B10, B9;If corresponding B12, B11, B10, B9's
The input variation full scale input voltage range of 10 BCD encoded radios is Um, is had
The reference voltage of ICL7109 is the 1/2 of full scale input voltage, is had
Therefore, the intrinsic standoff ratio for only needing to adjust resistance RF1, resistance RF2 at this time makes Uref be equal to the calculated value of formula (1) i.e.
It can.
If the AC supply voltage fluctuation range of input is 220V+10% to 220V-20%, it is desirable that use auto compensating type
Main circuit embodiment 2 is stablized to be exported in the range of 220V ± 2%, AC supply voltage waving interval range be 242V extremely
176V uses the analog-to-digital conversion coding unit embodiment 1 of Fig. 4 at this time, can be by input at 242V to the voltage between 176V points
Voltage for 10 voltage class sections that section voltage swing is 7V, 3 voltage class sections therein is higher than the defeated of requirement
Voltage range out needs to carry out drop compensation;The voltage in 6 voltage class sections is needed lower than desired output voltage range
Carry out boosting compensation;1 voltage class section carries out 0 voltage compensation, i.e. uncompensation within desired output voltage range.
The voltage range of 7V is 220V ± 1.6%, meets requirement of the output control within 220V ± 2%;10 voltage class of 7V
The corresponding AC supply voltage waving interval in section is 244.5V to 174.5V, covers the range actually fluctuated.Using Fig. 3
Auto compensating type main circuit embodiment 2 compensates, and the output voltage U12 of auto-transformer TB2 is minimum, U23 highest;Electricity
Pressure U23 is 3 times of voltage U12, and voltage U34 is 2 times of voltage U12;Then the input voltage of auto-transformer TB2 is exchange
220V, when only making the magnet exciting coil voltage of TB1 of output voltage U12, TB1 offset voltage is 7V;Auto-transformer TB2's is defeated
Entering voltage is alternating current 220V, and when only making the magnet exciting coil voltage of TB1 of output voltage U23, TB1 offset voltage is 21V;Self coupling becomes
The input voltage of depressor TB2 is alternating current 220V, when only making the magnet exciting coil voltage of TB1 of output voltage U34, TB1 offset voltage
For 14V;The input voltage of auto-transformer TB2 is alternating current 220V, while the excitation wire of TB1 is done using output voltage U12, U23
When enclosing voltage, TB1 offset voltage is 28V;Etc..At this point, the corresponding practical AC power source electricity in 10 voltage class sections of 7V
Pressure waving interval is 244.5V to 174.5V, covers the range actually fluctuated;Differential Input low side IN LO input, from base
The reference voltage Ucp of quasi- voltage output end REF OUT output should be theoretical with the lower bound of AC supply voltage waving interval range
Value 174.5V is corresponding;Accordingly, it is determined that the no-load voltage ratio of transformer TV1 and the intrinsic standoff ratio of resistance RV1, resistance RV2, it should in AC power source
When voltage is lower bound theoretical value 174.5V, export AC supply voltage sampled value U1 equal to reference voltage output end REF OUT
Reference voltage Ucp.In Fig. 4, the voltage class encoded radio P2 of analog-to-digital conversion coding unit output is by from ICL7109 highest 4
Data Y14, Y13, Y12, Y11 composition of B12, B11, B10, B9 output, Y14, Y13, Y12, Y11 and voltage 10 from low to high
The one-to-one 10 voltage class encoded radios in voltage class section are 0000 respectively, 0001,0010,0011,0100,0101,
0110,0111,1000,1001, it is realized by adjusting the size of la tension de reference Uref est.Adjust the side of la tension de reference Uref est size
Method first is that: AC supply voltage is on highest two voltage class sections boundary (i.e. the 235.4V of AC supply voltage)
When lower fluctuation, adjusting (adjusts) intrinsic standoff ratio of resistance RF1, resistance RF2, makes the numerical value of Y14, Y13, Y12, Y11 in 1000 and
It is fluctuated between 1001;Adjust la tension de reference Uref est size method second is that: set Uy as AC supply voltage 174.5V to
When the teachings fluctuation of 244.5V, from the voltage change of Differential Input high-end IN HOL and Differential Input low side IN LO input
Range has at this time
The variation range of Uy corresponds to 10 encoded radios of B12, B11, B10, B9 output binary-coded decimal, inputs, has for full scale
Therefore, the intrinsic standoff ratio for only needing to adjust resistance RF1, resistance RF2 at this time makes Uref be equal to the calculated value of formula (2) i.e.
It can.
In Fig. 4, other peripheral cell parameters of LTC1966, ICL7109 can be by reading corresponding device data handbook
It is determined.AC supply voltage sampled value U1 can also realize that ICL7109 can also use it using other detection circuits
His device, for example, ICL7109 is replaced using double integration A/D converter MAX139, MAX140, ICL7107 etc., MAX139,
The binary coding of the outputs such as MAX140, ICL7107 is 7 sections of codes, is acted on identical as the binary-coded decimal that ICL7109 is exported.
Fig. 5 is analog-to-digital conversion coding unit embodiment 2, and the AC supply voltage inputted from phase line L1 and zero curve N is through transformation
It after device TV2 decompression, is rectified by the rectifier bridge that diode DV1-DV4 is formed, then through capacitor CV3 filtering and resistance RV3, resistance RV4
Partial pressure obtains the AC supply voltage sampled value U2 with the AC supply voltage virtual value direct proportionality of input;Resistance RV5
Lower threshold potential circuit is formed with voltage-stabiliser tube WV1, voltage is and AC supply voltage waving interval range on voltage-stabiliser tube WV1
The corresponding lower threshold voltage U2cp of lower limit value.AC supply voltage sampled value U2 can also send the difference of the ICL7109 into Fig. 4
Divide input high-end IN HOL, the voltage class encoded radio that binary system is constituted is converted to by ICL7109 and is exported.
In Fig. 5, FD3 is biproduct parting A/D converter MC14433, for by AC supply voltage waving interval range
Voltage divides into voltage class section and is converted to the voltage class encoded radio output of binary system composition.In Fig. 5, MC14433's
Conversion end output end EOC is connected to transformation result output control terminal DU, its work is made to repeat transition status automatically;Integral
Resistance R14 and integrating capacitor C14 is connected to external integral element end R1, R1/C1, C1 of MC14433;Oscillation resistance R15 connection
To clock outward element end CP0, CP1 of MC14433;Compensating electric capacity C15 be connected to MC14433 external compensating electric capacity end C01,
C02;Resistance RF3, resistance RF4 divide power supply+VCC, and la tension de reference Uref est 1, Uref1 input are obtained on resistance RF4
To reference voltage input terminal VREF;VDD is the positive power source terminal of MC14433, is connected to power supply+VCC;VSS is digital ground terminal, VAG
To simulate ground terminal, it is connected to publicly.
In Fig. 5, FD4 is 4 road D-latch CD4042, and 4 data input pin D0-D3 of CD4042 are connected to MC14433's
4 data output end Q0-Q3;The triggering input end of clock CP of CD4042 is connected to hundred gating signal output ends of MC14433
DS2;The clock polarity control terminal POL of CD4042 connects high level, and positive power source terminal VDD is connected to power supply+VCC, digital ground terminal VSS
It is connected to publicly.CD4042 latches hundred BCD data that timesharing after each conversion end of MC14433 exports, modulus
Transform coding unit output voltage class encoded radio P2 by exported from CD4042 output end Q3, Q2, Q1, Q0 data Y14,
Y13, Y12, Y11 composition.CD4042 can be replaced with other latch.
If the AC supply voltage fluctuation range of input is 220V ± 10%, it is desirable that implemented using auto compensating type main circuit
Example 1 is stablized to be exported in the range of 220V ± 2%, and AC supply voltage waving interval range is 242V to 198V, at this time
Using the analog-to-digital conversion coding unit embodiment 2 of Fig. 5, input can be divided into section voltage in 242V to the voltage between 198V
Size is 7 voltage class sections of 6.4V, and the voltage in 3 voltage class sections therein is higher than desired output voltage model
It encloses, needs to carry out drop compensation;The voltage in 3 voltage class sections boosts lower than desired output voltage range
Compensation;1 voltage class section carries out 0 voltage compensation, i.e. uncompensation within desired output voltage range.
In Fig. 5, the measured voltage input terminal VX of MC14433 is connected to the output end of AC supply voltage sampled value U2, and
Lower threshold voltage U2cp is connected to publicly GND, and therefore, MC14433 is to AC supply voltage sampled value U2 and lower bound
Voltage difference between threshold voltage U2cp is converted;The corresponding practical AC power source electricity in 7 voltage class sections of 6.4V
Pressure waving interval is 242.4V to 197.6V, the lower bound of lower threshold voltage U2cp and AC supply voltage waving interval range
Theoretical value 197.6V is corresponding;Therefore, the intrinsic standoff ratio of the no-load voltage ratio of transformer TV2 and resistance RV3, resistance RV4, it should in AC power source
When voltage is lower bound theoretical value 197.6V, AC supply voltage sampled value U2 is made to be equal to lower threshold voltage U2cp.In Fig. 5, mould
The voltage class encoded radio P2 of number transform coding unit output is by data Y14, Y13, Y12, Y11 from MC14433 hundred output
Composition;Due to requiring input being divided into 7 voltages that section voltage swing is 6.4V in 242.4V to the voltage between 197.6V
One-to-one 7 voltage class in 7 voltage class sections are compiled from low to high for grade interval, Y14, Y13, Y12, Y11 and voltage
Code value is 0000,0001,0010,0011,0100,0101,0110 respectively, and the reference voltage of MC14433 is input to by adjusting
U2ref size is realized.Adjust reference voltage U2ref size method first is that: AC supply voltage is in 2 voltage of highest etc.
When fluctuating up and down at the demarcation voltage 236V in grade section, reference voltage is enabled to reduce since maximum value, adjusts resistance RF3, resistance
The intrinsic standoff ratio of RF4 fluctuates the numerical value of Y14, Y13, Y12, Y11 between 0110 and 0101;Adjust reference voltage U2ref size
Method second is that: set the voltage change of Ux at this time as AC supply voltage in the teachings fluctuation of 197.6V to 242.4V
Range has
Since the measurement output of MC14433 is 3 half BCD data, corresponding full scale input, kilobit shares 20 plus hundred
A BCD encoded radio, the variation range of Ux correspond to 7 minimum code values therein;If the input of corresponding 20 BCD encoded radios becomes
Changing full scale input voltage range is Uz, is had
The reference voltage of MC14433 is equal to full scale input voltage, has
Therefore, the intrinsic standoff ratio for only needing to adjust resistance RF3, resistance RF4 at this time makes U2ref be equal to the calculated value of formula (3) i.e.
It can.
If the AC supply voltage fluctuation range of input is 220V+10% to 220V-20%, it is desirable that use auto compensating type
Main circuit embodiment 2 is stablized to be exported in the range of 220V ± 2%, AC supply voltage waving interval range be 242V extremely
176V uses the analog-to-digital conversion coding unit embodiment 2 of Fig. 5 at this time, can be by input at 242V to the voltage between 176V points
Voltage for 10 voltage class sections that section voltage swing is 7V, 3 voltage class sections therein is higher than the defeated of requirement
Voltage range out needs to carry out drop compensation;The voltage in 6 voltage class sections is needed lower than desired output voltage range
Carry out boosting compensation;1 voltage class section carries out 0 voltage compensation, i.e. uncompensation within desired output voltage range.
The corresponding practical AC supply voltage waving interval in 10 voltage class sections of 7V is 244.5V to 174.5V, lower threshold electricity
Press U2cp corresponding with the lower limit value theoretical value 174.5V of AC supply voltage waving interval range;Therefore, the no-load voltage ratio of transformer TV2
With the intrinsic standoff ratio of resistance RV3, resistance RV4, it should when AC supply voltage is lower bound theoretical value 174.5V, keep AC power source electric
Sampled value U2 is pressed to be equal to lower threshold voltage U2cp.In Fig. 5, analog-to-digital conversion coding unit output voltage class encoded radio P2 by
From MC14433 hundred data Y14, Y13, Y12, the Y11 exported compositions, Y14, Y13, Y12, Y11 and supply voltage are from low to high
The one-to-one 10 voltage class encoded radios in 10 voltage class sections are 0000 respectively, 0001,0010,0011,0100,
0101,0110,0111,1000,1001, it is realized by adjusting the size of reference voltage U2ref.Adjust reference voltage U2ref
The method of size first is that: AC supply voltage is in highest two voltage class sections boundary (i.e. AC supply voltage
When 235.4V) fluctuating up and down, reference voltage is enabled to reduce since maximum value, adjusts the intrinsic standoff ratio of resistance RF3, resistance RF4, make
The numerical value of Y14, Y13, Y12, Y11 fluctuate between 1000 and 1001;Adjust reference voltage U2ref size method second is that: set
Uy is voltage change range of the AC supply voltage in the teachings fluctuation of 174.5V to 244.5V at this time, is had
The variation range of Uy corresponds to MC14433 kilobit plus hundred 10 minimum codes shared in 20 BCD encoded radios
Value;If the input variation full scale input voltage range for corresponding to 20 BCD encoded radios at this time is Uz, have
The reference voltage of MC14433 is equal to full scale input voltage, has
Therefore, the intrinsic standoff ratio for only needing to adjust resistance RF3, resistance RF4 at this time makes U2ref be equal to the calculated value of formula (4) i.e.
It can.
In Fig. 5, other peripheral cell parameters of MC14433 can be carried out really by reading corresponding device data handbook
It is fixed.AC supply voltage sampled value U2 can also be realized using other detection circuits, for example, being detected using various real available values
Chip is realized.Difference between AC supply voltage sampled value U2 and corresponding lower threshold voltage can also use its other party
Method obtains, for example, AC supply voltage sampled value U2 is subtracted corresponding lower threshold voltage with analog voltage subtraction circuit
Value.
In the various embodiments described above, when carrying out voltage compensation using auto compensating type main circuit embodiment 1, the mould of Fig. 4 is utilized
The number transform coding unit embodiments 1 either analog-to-digital conversion coding unit embodiment 2 of Fig. 5, will input 242V to 198V it
Between voltage when being divided into 7 voltage class sections that section voltage swing is 6.4V, the voltage that is made of Y14, Y13, Y12, Y11
In grade encoded radio, Y14 is constantly equal to 0, and therefore, at this time by 3, i.e., actual voltage class encoded radio is it is also assumed that be
Y13, Y12, Y11 composition, Y13, Y12, Y11 and voltage one-to-one 7 voltage in 7 voltage class sections etc. from low to high
Grade encoded radio is 000,001,010,011,100,101,110 respectively.
Fig. 6 is delay protection unit embodiment block diagram, wherein delay detection module YC1 is respectively to the voltage class of input
Encoded radio Y14, Y13, Y12, Y11 carry out voltage class encoded radio Y24, Y23, Y22, Y21 after signal delay is postponed,
Y23, Y24, Y22, Y21 form P3;YC1 module carries out Edge check to Y14, Y13, Y12, Y11 respectively simultaneously and obtains edge inspection
Survey signal Y34, Y33, Y32, Y31;Not trigger region control signal generator module YC2 by Edge check signal Y34, Y33 of input,
Y32, Y31 are converted to not trigger region control signal P4 output.In the embodiment block diagram of Fig. 6, the electricity of delay detection module YC1 input
Pressure grade encoded radio has Y14, Y13, Y12, Y11 etc. 4, and K is equal to 4;If K is equal to 3, the electricity of delay detection module YC1 input
Pressure grade encoded radio is made of 3 binary values, for example, when by Y13, Y12, Y11, after progress signal delay is postponed
Voltage class encoded radio accordingly also only has Y23, Y22, Y21 etc. 3, carries out Edge check to Y13, Y12, Y11 and obtains edge
Signal also Y33, Y32, Y31 etc. 3 are detected, not the Edge check signal of trigger region control signal generator module YC2 input
Only Y33, Y32, Y31 etc. 3.
Fig. 7 is the delay detection circuit embodiment 1 that delay detection module encodes value signal Y11 for voltage class.Resistance
RY0, capacitor CY0, driving gate FY0 realize the signal delay of Y11 is obtained Y11 it is delayed after signal Y21.Resistance RY1, electricity
Hold the rising edge detection circuit that CY1, diode DY1, phase inverter FY1 composition are directed to input signal Y 11, the output of phase inverter FY1
In signal YP1, the pulse of corresponding negative pulse form is exported after Y11 rising edge.Resistance RY2, capacitor CY2, two
Pole pipe DY2, phase inverter FY2, FY3 composition are directed to the failing edge detection circuit of input signal Y 11, the output signal of phase inverter FY3
In YP2, the pulse of corresponding negative pulse form is exported after Y11 failing edge.NAND gate FY4 is accomplished that negative patrol
Collect or logic function, when there is negative pulse generation in input signal Y P1, YP2, the Edge check signal of NAND gate FY4 output
Positive pulse is generated in Y31, i.e., when input signal Y 11 changes, NAND gate FY4 exports the pulse of a positive pulse form.
In Fig. 7, the device of driving gate FY0, phase inverter FY1, phase inverter FY3 preferably with Schmidt's input, for example, phase inverter selects
74HC14, CD40106 etc.;Driving gate FY0 can be made of 2 phase inverters with Schmidt's input.
Fig. 8 is the delay detection circuit embodiment 2 that delay detection module encodes value signal Y11 for voltage class.Reverse phase
Device FY5, resistance RY3, capacitor CY3 carry out reverse phase and delay to input signal Y 11, obtain the delayed inversion signal YP0 of Y11;
Phase inverter FY6 again by YP0 reverse phase, obtain Y11 it is delayed after signal Y21.The signal of NAND gate FY7 input is Y11 and Y11
The pulse of negative pulse form corresponding with Y11 rising edge is generated in delayed inversion signal YP0, output signal YP1;Or door
The signal of FY8 input is the delayed inversion signal YP0 of Y11 and Y11, is generated in output signal YP2 corresponding with Y11 failing edge
The pulse of negative pulse form.NAND gate FY9 is accomplished that negative logic or logic function, when having in input signal Y P1, YP2
When negative pulse generates, positive pulse is generated in the Edge check signal Y31 of NAND gate FY9 output, i.e., when input signal Y 11 changes
When, NAND gate FY9 exports the pulse of a positive pulse form.In Fig. 8, phase inverter FY6, NAND gate FY7 or door FY8 are preferred
Device with Schmidt's input, for example, phase inverter selects 74HC14, CD40106 etc.;NAND gate selects 74HC132, CD4093
Etc.;Or door selects 74HC7032, or the phase inverters that input of 2 band Schmidts of selection and 1 NAND gate are realized or door
Function.
Fig. 9 is the delay detection circuit embodiment 3 that delay detection module encodes value signal Y11 for voltage class, wherein
Rising edge detection circuit for input signal Y 11 is formed by resistance RY1, capacitor CY1, diode DY1, phase inverter FY1, and
Failing edge detection electricity for input signal Y 11 is formed by resistance RY2, capacitor CY2, diode DY2, phase inverter FY2, FY3
Road, and it is identical as the embodiment 1 of Fig. 7 using the circuit of NAND gate FY4 output Edge check signal Y31.In Fig. 9, by reverse phase
Device FY11, FY12, FY13, FY14 realize the signal delay of Y11 is obtained Y11 it is delayed after signal Y21.
The embodiment 1-3 of Fig. 7, Fig. 8, Fig. 9 are the delay detection electricity for the signal Y11 in voltage class encoded radio
Road, for other signals in voltage class encoded radio, for example, it is directed to input signal Y 13, the delay detection circuit of Y12, and
The delay detection circuit of Y14 in 4 voltage class encoded radios is delayed with input signal Y 11 is directed in corresponding embodiment
The circuit structure of detection is as function.Delay detection circuit can also realize its function using other circuits met the requirements
Energy.
The function of trigger region control signal generator module is, when any one of Edge check signal of input or
It is multiple when having pulse relevant to edge, a pulse is not exported in trigger region control signal.Figure 10 is not trigger
Area controls signal generator module embodiment, by or door FY10 realize that the input signal of corresponding function or door FY10 are that edge is examined
Signal Y34, Y33, Y32, Y31 are surveyed, exports and controls signal P4 for not trigger region.In Figure 10 embodiment, trigger region does not control signal
The pulse of output is positive pulse, i.e., trigger region control signal high level is not effective;When or door FY10 change nor gate into when, do not touch
The pulse for sending out area's control signal output is negative pulse, and trigger region control signal low level is not effective.If the edge inspection of input
Survey signal Y34, Y33, Y32, Y31 in generate have pulse relevant to edge be negative pulse, then in Figure 10 or door should
Be changed to NAND gate either with door, realize negative logic or logic function.If the Edge check signal of input only has 3
When, for example, when only Edge check signal Y33, Y32, Y31, in Figure 10 or door, or for realizing not trigger region control
Other doors of signal generator module function processed, for example, nor gate, NAND gate is also 3 in-gate circuits with door etc. accordingly.
Figure 11 is that split-phase closes waveform diagram in the middle part of delay protection unit.In Figure 11, the Y11 in voltage class encoded radio divides
Not Fa Sheng rising edge change and failing edge changes, Y21 is the voltage class encoded radio after the Y11 delay T1 time;Fig. 7's
In the detection circuit embodiment 1 that is delayed, T1 is determined by the product size (i.e. time constant size) of resistance RY0 and capacitor CY0;Scheming
In 8 delay detection circuit embodiment 2, T1 is determined by the product size of resistance RY3 and capacitor CY3;Electricity is detected in the delay of Fig. 9
In road embodiment 3, T1 is determined by the gate delay time size of phase inverter FY11, FY12, FY13, FY14 itself.In Figure 11, letter
Because the negative pulse width that Y11 rising edge generates is T2 in number YP1;In the delay detection circuit embodiment 1 of Fig. 7 and the delay of Fig. 9
In detection circuit embodiment 3, T2 is determined by the product size of resistance RY1 and capacitor CY1;Implement in the delay detection circuit of Fig. 8
In example 2, T2 is determined by the product size of resistance RY3 and capacitor CY3.In Figure 11, because what Y11 failing edge generated bears in signal YP2
Pulse width is T3;In the delay detection circuit embodiment 1 of Fig. 7 and the delay detection circuit embodiment 3 of Fig. 9, T3 is by resistance
The product size of RY2 and capacitor CY2 determines;In the delay detection circuit embodiment 2 of Fig. 8, T3 is by resistance RY3 and capacitor CY3
Product size determine.In Figure 11,2 positive pulses in Edge check signal Y31 respectively in signal YP1 because of Y11 rising edge
Because the negative pulse that Y11 failing edge generates corresponds in the negative pulse and signal YP2 of generation.It is located in Figure 11 voltage class encoded radio
Y11 when rising edge occurs changing, no change has taken place by Y12, Y13, Y14 in voltage class encoded radio, its is corresponding at this time
Edge check signal Y32, Y33, Y34 do not generate positive pulse;If when failing edge, which occurs, for Y11 changes, voltage class encoded radio
In Y12 change simultaneously, no change has taken place by Y13, Y14, at this time in its corresponding Edge check signal Y32 generate with
Y12 changes relevant positive pulse;Because Y33, Y34 maintain low level not change, it is not drawn into Figure 11.It is not touched according to above-mentioned
The logic function of area's control signal generator module is sent out, not the single pulse width and input of trigger region control signal generator module output
Edge check signal in generate widest pulse width in the input pulse of the pulse jointly identical.In Figure 11, do not trigger
Area controls the 1st positive pulse in signal P4 and is generated by the 1st negative pulse in Edge check signal Y31, then the two width one
It causes;The 2nd positive pulse in trigger region control signal P4 be not by the 2nd negative pulse and edge inspection in Edge check signal Y31
The negative pulse joint effect surveyed in signal Y32 generates, and width and width in 2 negative pulses for generating the positive pulse are widest
Negative pulse width is identical;As can be seen from Figure 11, the negative pulse width in Y32 is wider, in the 2nd in P4 positive pulse width and Y23
Negative pulse width it is identical.This width difference is the difference because of the resistance, capacitance that determine T2, T3 in different delayed time detection circuit
Caused by different.
In the delay detection circuit embodiment 1 in Fig. 7 delay protection unit, voltage class encoded radio changes to right
When the delay time in the not trigger region control signal pulse forward position answered is the delay of FY10 in gate circuit FY1, FY4 and Figure 10
Between the sum of or gate circuit FY3, FY4 and Figure 10 in FY10 the sum of delay time;By multiplying for resistance RY0 and capacitor CY0
The range of choice of the signal delay time T1 for the voltage class encoded radio that product size determines is the ms order of magnitude, it is clear that is greater than voltage
Grade encoded radio changed to the delay time in corresponding not trigger region control signal pulse forward position, i.e. grade encoded radio is believed
Number delay is later than forward position moment of the pulse exported after voltage class encoded radio changes at the time of change.Strictly speaking,
T1 actually includes the sum of lag time and the delay time of gate circuit FY0 caused by resistance RY0 and capacitor CY0.Fig. 7
In embodiment 1, in selection parameter, the value of the value and T3 that make T2 is all larger than the value of T1, changes grade encoded radio signal delay
Meet the rear requirement along the moment of the pulse exported after need to changing earlier than voltage class encoded radio at the time of change.
It is delayed in detection circuit embodiment 2 in the delay protection unit of Fig. 8, voltage class encoded radio changes to right
When the delay time in the not trigger region control signal pulse forward position answered is the delay of FY10 in gate circuit FY7, FY9 and Figure 10
Between the sum of or gate circuit FY8, FY9 and Figure 10 in FY10 the sum of delay time;T1 is the numerical value of the ms order of magnitude, is shown
So, the signal delay time T1 of the voltage class encoded radio determined at this time by the product size of resistance RY3 and capacitor CY3 is greater than
Voltage class encoded radio changed to the delay time in corresponding not trigger region control signal pulse forward position, i.e. voltage class
Encoded radio signal delay is later than the forward position moment of the pulse exported after voltage class encoded radio changes at the time of change.Figure
In 8 delay detection circuit embodiment 2, occur at the time of voltage class encoded radio signal delay changes with voltage class encoded radio
The rear of the pulse exported after change is influenced by signal YP0 change along the moment;Voltage class encoded radio signal delay changes
At the time of change for signal YP0 after delay again through gate circuit FY6;The pulse that voltage class encoded radio exports after changing
It is rear along the moment be the sum of delay time again through FY10 in gate circuit FY7, FY9 and Figure 10, or letter after signal YP0 changes
The sum of delay time again through FY10 in gate circuit FY8, FY9 and Figure 10 after number YP0 changes;Obviously, voltage class encodes at this time
The rear of the pulse that value signal delay exports after changing at the time of change than voltage class encoded radio few passes through 2 along the moment
The delay time of gate circuit, meeting at the time of voltage class encoded radio signal delay changes need to occur earlier than voltage class encoded radio
The rear requirement along the moment of the pulse exported after change.
Figure 12 is the embodiment for interlocking control unit, and Figure 12 (a) is interlocking control unit embodiment 1, and YR1 therein is
ROM memory.If the output voltage U12 of auto-transformer TB2 is low, U23 high in Fig. 2 auto compensating type main circuit embodiment 1;
Voltage U23 is 2 times of voltage U12.Table 1 is to compensate control using Fig. 2 auto compensating type main circuit embodiment 1, utilizes figure
The 4 analog-to-digital conversion coding unit embodiment 1 either analog-to-digital conversion coding unit embodiment 2 of Fig. 5, is divided into 7 for supply voltage
A voltage class section, when forming 7 voltage class encoded radios by Y23, Y22, Y21 after Y13, Y12, Y11, or delay
Carry out the logic true value table of logic control;AC supply voltage fluctuation range is 220V ± 10%, it is desirable that is stablized in 220V
It is exported in the range of ± 2%.Using ROM memory realize interlocking control unit logic function when, P4, Y23-Y21 respectively according to
The data output D0-D5 of the secondary address input end A3-A0 for being connected to ROM memory, ROM memory are to interlock patrolling for control unit
Output is collected, 6 output signal P51-P56 form Trig control signal P5.
Table 1
In table 1, trigger region does not control invalidating signal, and P4 is equal to 0, and voltage class encoded radio is corresponding with voltage class 1-7
Value when, interlocking control unit control auto compensating type main circuit embodiment 1 carry out corresponding voltage compensation;For example, input electricity
When pressure is minimum voltage class 1, control P51, P56 output remove to open bidirectional thyristor SR1, SR6 for 0, control P52 etc. other
Output goes to turn off other bidirectional thyristors for 1, carries out positive benefit using the magnet exciting coil voltage that output voltage U12+U23 is TB1
It repays;When input voltage is voltage class 2, control P53, P56 output go to open bidirectional thyristor SR3, SR6, control P51 etc. for 0
Other outputs go to turn off other bidirectional thyristors for 1, carry out only with the magnet exciting coil voltage that output voltage U23 is TB1 positive
Compensation;When input voltage is voltage class 4, control P55, P56 output goes to open bidirectional thyristor SR5, SR6 for 0, controls P51
It goes to turn off other bidirectional thyristors for 1 Deng other outputs, realizes 0 voltage compensation;When input voltage is voltage class 5, control
P52, P53 output go to open bidirectional thyristor SR2, SR3 for 0, other outputs such as control P51 go to turn off other two-way brilliant locks for 1
Pipe carries out Contrary compensation only with the magnet exciting coil voltage that reversed output voltage U12 is TB1;Etc..When P4 is equal to 1, show
There is fluctuation in AC supply voltage, voltage class encoded radio is made to produce variation, need to carry out the combination of thyristor switch group on-off
The switching of state changes compensation way.In the handoff procedure of electronic switch, to avoid thyristor in thyristor switch group from switching
When, because the factor that electronic switch is delayed to turn off causes power supply short circuit, for example, thyristor SR1, SR3 are simultaneously turned on and are caused short circuit
Situations such as, when not trigger region controls the signal valid period, i.e. the P4 of embodiment is equal to 1, own in cutoff thyristor switching group
Bidirectional thyristor, interlocking control unit control P51-P56 all output 1.
In table 1, M is equal to 7.Not when trigger region control invalidating signal (P4 be equal to 0), 7 voltage class encoded radio P3's has
Effect encoded radio is corresponding with 7 groups of effective Trig control signals, accordingly realizes the control of 7 kinds of voltage compensation states;When P2 change makes P4
Effectively (P4 be equal to 1) when be corresponding with 1 group of effective Trig control signal, interlocking control unit exports altogether has 8 groups effectively to trigger control
Signal.When P4 invalid (P4 is equal to 0), and when the voltage class encoded radio P3 for interlocking control unit input is invalid code value, mutually
Lock control unit is corresponding with 1 group of specifically invalid Trig control signal.Using Fig. 4 analog-to-digital conversion coding unit embodiment 1 or
Person is the analog-to-digital conversion coding unit embodiment 2 of Fig. 5, supply voltage is divided into 7 voltage class sections, by Y13, Y12, Y11
Export the efficient coding value of 7 voltage class encoded radios, Y13, Y12, Y11 either Y23, Y22, Y21 are only possible to that there are 1 nothings
The output of encoded radio is imitated, is 111.In table 1, it is 1 which, which makes P56 output be 0, P51-P55 output,;
The specific invalid practical control of the Trig control signal without thyristor, even if the triggering control for playing thyristor is made
With also only making TB1 magnet exciting coil be connected to a tap and excitation voltage 0 of auto-transformer TB2, without voltage compensation;
This 1 group specifically invalid Trig control signal be also an option that other not and can be carried out the triggering combination of voltage compensation, for example, making
P55 output is 0, and others output is 1.
In table 1, low level is effective when the Trig control signal triggering bidirectional thyristor of interlocking control unit output is connected.Such as
The Trig control signal that fruit interlocks control unit output requires to be that high level is effective when triggering bidirectional thyristor conducting, then table 1 is patrolled
1 in the output signal of volume truth table, which needs to change into 0,0, needs to change into 1;When realizing its function with ROM memory, storage
The content of unit is according to 1 reverse phase of table.
Figure 12 (b) is interlocking control unit embodiment 2, and YR2 therein is ROM memory.If the main electricity of Fig. 3 auto compensating type
In road embodiment 2, the output voltage U12 of auto-transformer TB2 is minimum, U23 highest;Voltage U23 is 3 times of voltage U12, voltage
U34 is 2 times of voltage U12.Table 2 is to compensate control using Fig. 3 auto compensating type main circuit embodiment 2, utilizes the mould of Fig. 4
The either analog-to-digital conversion coding unit embodiment 2 of Fig. 5 of number transform coding unit embodiment 1, is divided into 10 electricity for supply voltage
Grade interval is pressed, 10 voltage class are formed by Y24, Y23, Y22, Y21 after Y14, Y13, Y12, Y11, or delay and are compiled
The logic true value table of logic control is carried out when code value;AC supply voltage fluctuation range is 220V+10% to 220V-20%,
It asks to be stablized and be exported in the range of 220V ± 2%.When realizing its logic function using ROM memory YR2, input P4,
Y24-Y21 is sequentially connected to the address end A4-A0 of ROM memory respectively, and the data output D0-D7 of ROM memory is mutual lock control
The logic of unit processed exports, and 8 output signal P51-P58 form Trig control signal P5.
In table 2, trigger region does not control invalidating signal, and P4 is equal to 0, and voltage class encoded radio is corresponding with voltage class 1-10
Value when, interlocking control unit control auto compensating type main circuit embodiment 2 carry out corresponding voltage compensation;For example, input electricity
When pressure is voltage class 7, control P57, P58 output go to open bidirectional thyristor SR7, SR8, other outputs such as control P51 for 0
It goes to turn off other bidirectional thyristors for 1, realizes 0 voltage compensation;When input voltage is voltage class 8, control P52, P53 output is
0 goes to open bidirectional thyristor SR2, SR3, other outputs such as control P51 go to turn off other bidirectional thyristors for 1, only with reversed
The magnet exciting coil voltage that output voltage U12 is TB1 carries out Contrary compensation;When input voltage is voltage class 9, P56, P57 are controlled
Output goes to open bidirectional thyristor SR6, SR7 for 0, other outputs such as control P51 are gone to turn off other bidirectional thyristors, only be adopted for 1
Contrary compensation is carried out with the magnet exciting coil voltage that reversed output voltage U34 is TB1;When input voltage is voltage class 10, control
P54, P55 output go to open bidirectional thyristor SR4, SR5 for 0, other outputs such as control P51 go to turn off other two-way brilliant locks for 1
Pipe carries out Contrary compensation only with the magnet exciting coil voltage that reversed output voltage U23 is TB1;Input voltage is voltage class 6
When, control P51, P54, which export, to be gone to open bidirectional thyristor SR1, SR4 for 0, other outputs such as control P52 go to turn off other pairs for 1
To thyristor, positive compensation is carried out only with the magnet exciting coil voltage that output voltage U12 is TB1;Input voltage is voltage class 4
When, control P53, P56 output go to open bidirectional thyristor SR3, SR6 for 0, other outputs such as control P51 go to turn off other for 1
Bidirectional thyristor carries out positive compensation only with the magnet exciting coil voltage that output voltage U23 is TB1;Input voltage is voltage etc.
When grade 3, control P51, P56 output go to open bidirectional thyristor SR1, SR6 for 0, other outputs such as control P52 go to turn off it for 1
His bidirectional thyristor carries out positive compensation using the magnet exciting coil voltage that output voltage U12+U23 is TB1;Input voltage is electricity
When pressing grade 1, control P51, P58 output go to open bidirectional thyristor SR1, SR8 for 0, other outputs such as control P52 go to close for 1
Break other bidirectional thyristors, carries out positive compensation using the magnet exciting coil voltage that output voltage U12+U23+U34 is TB1;Deng
Deng.Trigger region control signal is not effective, when P4 is equal to 1, shows that AC supply voltage has fluctuation, produces voltage class encoded radio
Variation has been given birth to, has needed to carry out the switching of thyristor switch group on-off assembled state, has changed compensation way, cutoff thyristor is opened at this time
All bidirectional thyristors of Guan Zuzhong, interlocking control unit control P51-P58 all output 1.
In table 2, M is equal to 10.Not when trigger region control invalidating signal (P4 be equal to 0), 10 voltage class encoded radio P3's
Efficient coding value is corresponding with 10 groups of effective Trig control signals, accordingly realizes the control of 10 kinds of voltage compensation states;When P2 changes
When making P4 effective (P4 is equal to 1), it is corresponding with 1 group of effective Trig control signal, interlocking control unit shares 11 groups and effectively triggers control
Signal processed.When P4 invalid (P4 is equal to 0), and when the voltage class encoded radio P3 for interlocking control unit input is invalid code value,
Interlocking control unit is corresponding with 1 group of specifically invalid Trig control signal;Utilize the analog-to-digital conversion coding unit embodiment 1 of Fig. 4
Either Fig. 5 analog-to-digital conversion coding unit embodiment 2, supply voltage is divided into 10 voltage class sections, by Y14, Y13,
The voltage class encoded radio of Y12, Y11 composition exports the efficient coding value of 10 voltage class encoded radios altogether, and 4 voltage class are compiled
There is likely to be the outputs of 6 invalid code values by code value Y14, Y13, Y12, Y11 or Y24, Y23, Y22, Y21, make mutually
Lock control unit exports same 1 group of invalid Trig control signal;In table 2, which export P58
It is 1 for 0, P51-P57 output;The specific invalid practical control of the Trig control signal without thyristor, even if playing
The triggering control action of thyristor also only makes TB1 magnet exciting coil be connected to a tap and excitation voltage of auto-transformer TB2
It is 0, without voltage compensation;This 1 group specifically invalid Trig control signal be also an option that other not can be carried out voltage compensation
Triggering combination, for example, making P57 output for 0, others output is 1.
In table 2, low level is effective when the Trig control signal triggering bidirectional thyristor of interlocking control unit output is connected.Such as
High level is effective when the Trig control signal that fruit interlocks control unit output requires triggering bidirectional thyristor to be connected, then 2 logic of table
1 in the output signal of truth table, which needs to change into 0,0, needs to change into 1;When realizing its function with ROM memory, storage is single
The content of member is according to 2 reverse phase of table.
Table 2
Combination logic function in either 2 truth table of table of table 1, can also be using the other modes except ROM memory
It goes to realize.
Figure 13 be trigger unit in trigger bidirectional thyristor SR1 trigger circuit embodiment, by altemating trigger optocoupler UG1,
Resistance RG1, resistance RG2 composition, Trig control signal P51 low level are effective.Altemating trigger optocoupler UG1 can choose
The phase shifts type bidirectional thyristor output light thermocouple such as MOC3021, MOC3022, MOC3023, MOC3051, MOC3052, MOC3053
Clutch.Power supply+VCCK is the controlled source controlled by error detection control unit.It triggers in Fig. 2 auto compensating type main circuit embodiment 1
Bidirectional thyristor SR2-SR8 in bidirectional thyristor SR2-SR6, or triggering Fig. 3 auto compensating type main circuit embodiment 2
Trigger circuit is as the circuit structure of triggering bidirectional thyristor SR1.The altemating trigger optocoupler UG1 of Figure 13 is exported from G11, G12
Trigger pulse and trigger unit in other altemating trigger optocouplers output trigger pulse collectively constitute trigger signal P6.
Figure 14 is error detection control unit embodiment, wherein YR3 is ROM memory, and ROM memory forms discrimination module, is used
In judge input Trig control signal P5 whether be effective Trig control signal;Triode VT, triode VK1, triode
VK2, relay coil KA, freewheeling diode VD, resistance RK1, resistance RK2, resistance RK3 composition protection control circuit.+ VCC2 is
The power supply of relay coil and the source current of trigger unit controlled source.
The error detection control unit embodiment of Figure 14 is used for the triggering issued for Figure 12 (a) interlocking control unit embodiment 1
Control signal is judged that table 3 is to judge to interlock whether the Trig control signal that control unit embodiment 1 issues is effectively to trigger
The logic true value table of signal is controlled, auto-transformer forms thyristor switch group by 3 taps, by 6 bidirectional thyristors at this time.
Table 3
When the Trig control signal that interlocking control unit embodiment 1 issues effectively touches for 8 groups listed by 8 rows of front in table 3
When hair controls 1 group in signal, the triggering control of discrimination module output differentiates that signal is effective, i.e. P7 is 1, expression triggering control letter
Number be effective Trig control signal, triode VK1, VK2 conducting, controlled source+VCCK obtain it is electric, trigger unit work normally, according to
Corresponding trigger pulse is issued according to Trig control signal.P7 be 1 simultaneously control triode VT conducting, relay coil KA obtain it is electric,
It is closed the relay normally open switch KA-1 in Fig. 2 auto compensating type main circuit embodiment 1, relay normally closed switch KA-2 is disconnected
It opens, thyristor switch group is in compensation work state.When the Trig control signal that interlocking control unit embodiment 1 issues is other
Signal, when not being any 1 group in 8 groups of effective Trig control signals listed by 8 rows of front in table 3, the touching of discrimination module output
Hair control differentiates that invalidating signal, i.e. P7 are 0, triode VK1, VK2 cut-off, controlled source+VCCK power loss, trigger unit not work
Make, i.e., does not issue the trigger pulse of triggering thyristor.P7 is 0 while controlling triode VT cut-off, and relay coil KA power loss makes
Relay normally open switch KA-1 in Fig. 2 auto compensating type main circuit embodiment 1 is disconnected, i.e. control disconnects the defeated of auto-transformer
Enter side supply voltage, make the voltage 0 between all taps of auto-transformer, realizes the protection to thyristor switch group;Control
Relay normally closed switch KA-2 closure, makes the voltage 0 being applied on TB1 magnet exciting coil.When interlocking control unit embodiment 1
Input is invalid code value, and when exporting invalid Trig control signal, from table 3 it can be seen that it is 0 that discrimination module, which equally export,
Realize the protection to thyristor switch group;Therefore, either because the failure of code error occurs in analog-to-digital conversion coding unit
Cause to output invalid code value, or interlocking control unit control mistake occurs and causes to output invalid triggering control letter
Number, error detection control unit, which starts, protects thyristor switch group.When the logic true value table of table 3 is real using ROM memory
Now, the address input of ROM memory needs 6, i.e. a0-a5 in table 3 is correspondingly connected with input signal P51-P56;ROM is deposited
The data output of reservoir needs 1, i.e. d0 in table 3 is correspondingly connected with the control signal P7 of output.
When error detection control unit need for Figure 12 (b) interlocking control unit embodiment 2 issue Trig control signal into
When row judges, table 4 is to judge to interlock whether the Trig control signal that control unit embodiment 2 issues is effective triggering control letter
Number logic true value table, auto-transformer forms thyristor switch group by 4 taps, by 8 bidirectional thyristors at this time.
Table 4
When the Trig control signal that interlocking control unit embodiment 2 issues is effective for 11 groups listed by 11 rows of front in table 4
When 1 group in Trig control signal, the triggering control of discrimination module output differentiates that signal is effective, i.e. P7 is 1, indicates triggering control
Signal is effective Trig control signal, and triode VK1, VK2 are connected, and controlled source+VCCK obtains electric, trigger unit normal work,
Corresponding trigger pulse is issued according to Trig control signal.P7 is in 1 while 3 auto compensating type main circuit embodiment 2 of control figure
Relay normally open switch KA- 1 be closed, relay normally closed switch KA-2 is disconnected, and circuit is in compensation work state.Work as interlocking
Control unit embodiment 2 issue Trig control signal be other signals, be not in table 4 front 11 rows listed by 11 groups effectively touch
When hair controls any 1 group in signal, the triggering control of discrimination module output differentiates that invalidating signal, i.e. P7 are 0, triode VK1,
VK2 cut-off, controlled source+VCCK power loss, trigger unit do not work, i.e., do not issue the trigger pulse of triggering thyristor.P7 is 0 same
When 3 auto compensating type main circuit embodiment 2 of control figure in relay normally open switch KA-1 disconnect, i.e., control disconnect self coupling become
The input side supply voltage of depressor makes the voltage 0 between all taps of auto-transformer, realizes the guarantor to thyristor switch group
Shield;Relay normally closed switch KA-2 closure is controlled, the voltage 0 being applied on TB1 magnet exciting coil is made.When interlocking control unit
The input of embodiment 2 is invalid code value, and when exporting invalid Trig control signal, from table 4, it can be seen that discrimination module exports
It is 0, realizes the protection to thyristor switch group;Similarly, either because code error occurs in analog-to-digital conversion coding unit
Failure lead to output invalid code value, or there is control mistake and causes to output invalid triggering control in interlocking control unit
Signal processed, error detection control unit, which starts, protects thyristor switch group.
When the logic true value table of table 4 is realized using ROM memory, for example, realizing error detection control using the embodiment of Figure 14
When the function of unit processed, the address input of the ROM memory YR3 in Figure 14 needs to be expanded to 8, i.e. address input needs a0-
A7 is correspondingly connected with input signal P51-P58;The data output of ROM memory needs 1, i.e. d0 in table 4 is correspondingly connected with defeated
Control signal P7 out.When error detection control unit judgement input Trig control signal be not effective Trig control signal, issue
Protection control signal is to auto compensating type main circuit, and when thyristor switch group being made to be in guard mode, auto compensating type exchange is steady
Depressor does not compensate input voltage, and the voltage of voltage-stablizer output is the AC supply voltage inputted.In thyristor switch
When group is in guard mode, if the Trig control signal of error detection control unit judgement input reverts to effectively triggering control letter
Number, then error detection control unit is automatically stopped the guard mode of thyristor switch group, and thyristor switch group is in compensation work again
State.
Combination logic function in either 4 truth table of table of table 3, can also be using the other modes except ROM memory
It goes to realize.
From above embodiment and its course of work it is found that as long as error detection control unit judges the triggering control letter of input
Number it is not effective Trig control signal, i.e., when Trig control signal is invalid, is not then issuing the trigger pulse of triggering thyristor
Meanwhile starting and thyristor switch group is made to be in guard mode;It is protected exporting effective Trig control signal by interlocking control unit
Ipsilateral thyristor does not simultaneously turn in card auto compensating type main circuit thyristor switch group, realizes the same of the mutual lock control of thyristor
When, also there is analog-to-digital conversion event to other improper control logic mistakes of appearance, including analog-to-digital conversion coding unit in system
Barrier either logic error outputs invalid code value, and logic error occurs in interlocking control unit, outputs invalid triggering
When controlling signal, is started by error detection control unit and thyristor switch group is made to be in guard mode;It is in thyristor switch group
When guard mode, if error detection control unit judges that auto compensating type AC voltage regulator reenters normal logic control shape
When the Trig control signal of state, i.e. error detection control unit judgement input reverts to effective Trig control signal, then it can stop automatically
Only the guard mode of thyristor switch group and it is made to be in compensation work state again.Above-mentioned function is effectively strengthened for steady
The protection for pressing through journey operation irregularity makes the more stable, reliable of single phase ac pressure stabilizing process.
In above each embodiment attached drawing, all ROM memories, logic gates and logic function integrated circuit are adopted
It is powered with positive single supply+VCC.Except for the technical features described in the specification, auto compensating type AC voltage regulator control of the present invention is realized
The other technologies of method processed are the routine techniques that those skilled in the art are grasped.