CN111580349A - Wafer stacking anomaly compensation method and wafer stacking anomaly information measurement method - Google Patents

Wafer stacking anomaly compensation method and wafer stacking anomaly information measurement method Download PDF

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CN111580349A
CN111580349A CN202010466230.2A CN202010466230A CN111580349A CN 111580349 A CN111580349 A CN 111580349A CN 202010466230 A CN202010466230 A CN 202010466230A CN 111580349 A CN111580349 A CN 111580349A
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wafer
stacking
measurement
exposure
edge
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刘隽瀚
周文湛
胡展源
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/7065—Defects, e.g. optical inspection of patterned layer for defects
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

The invention relates to a wafer stacking abnormality compensation method, which relates to the semiconductor integrated circuit manufacturing technology, and is characterized in that exposure units for stacking abnormality measurement are arranged, wherein the number of the exposure units for stacking abnormality measurement is any value between 25 and 35, the ratio of the number of the exposure units in the range of the edge of a wafer in the exposure units for stacking abnormality measurement to the number of the exposure units in the range of the edge of the wafer in the wafer surface is any value between 4:1 and 6:1, measurement points in each exposure unit for stacking abnormality measurement are arranged, the number of the measurement points in each exposure unit for stacking abnormality measurement is ensured to be equal, the information quantity proportion of stacking abnormality in the range of the edge of the wafer is increased, the obtained wafer stacking abnormality information can reflect the stacking abnormality information of the edge of the wafer better, and the wafer edge stacking compensation effect is better, thereby improving the yield of the product.

Description

Wafer stacking anomaly compensation method and wafer stacking anomaly information measurement method
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing technology, and more particularly, to a wafer overlay anomaly compensation method.
Background
In the manufacturing process of semiconductor integrated circuits, the lithographic area is often detected as an overlay anomaly, which may result in a reduction in product yield. In addition, the stacking fault mostly occurs around the wafer, i.e. the edge, and many stacking faults occur around the edge regardless of the process or the exposure tool. Specifically, referring to fig. 1, fig. 1 is a schematic diagram of a stacking anomaly of a PDF wafer, as shown in fig. 1, the stacking anomaly mostly occurs around a circle of the wafer. Referring to fig. 2 again, fig. 2 is a schematic diagram of a wafer stacking abnormal vector, as shown in fig. 2, the stacking abnormal vector in the exposure unit 103 near the center of the wafer is smaller, and the stacking abnormal vector in a circle around the wafer is larger, specifically, the stacking abnormal vector in the exposure unit (shot)101 and the exposure unit 102 at the edge of the wafer is larger, which easily exceeds the stacking abnormal threshold, and thus the yield of the product is reduced. And the die edge stacking capability is very difficult to compensate, so that it seriously affects the product yield.
Disclosure of Invention
The invention provides a wafer stacking abnormity compensation method, which comprises the following steps: s1: setting exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, and the ratio of the number of the exposure units in the range of the edge of the wafer in the exposure units for stacking anomaly measurement to the number of the exposure units in the range of the edge of the wafer in the wafer plane is any value between 4:1 and 6: 1; s2: designing a measuring point photomask layout, arranging measuring points positioned outside the wafer surface in the range of the exposure unit in the wafer surface, and ensuring that the number of the measuring points in each exposure unit for stacking abnormity measurement is equal; s3: acquiring stacking abnormal information of a measuring point in each exposure unit in the exposure units for stacking abnormal measurement, and further acquiring wafer stacking abnormal information; s4: obtaining a superposition anomaly compensation value according to the wafer superposition anomaly information obtained in the step S3; and S5: and performing superposition compensation on the wafer according to the superposition abnormal compensation value obtained in the step S4.
Further, the number of exposure units for overlay anomaly measurement set in step S1 is 30.
Further, in step S1, the number of exposure units located in the wafer edge range among the exposure units used for the overlay anomaly measurement and the number of exposure units in the wafer plane except the wafer edge range are set to be 5: 1.
Furthermore, the exposure unit located in the edge range of the wafer is moved to the edge side of the wafer by another exposure unit, so that the exposure unit is at least partially located outside the wafer surface.
Further, the number of measurement points in each exposure unit for the overlay anomaly measurement is 9.
Further, in step S2, the measurement point located outside the wafer surface within the exposure unit range is moved to a position within the wafer surface close to the wafer edge line, so as to locate the measurement point located outside the wafer surface within the exposure unit range within the wafer surface.
The invention also provides a method for measuring wafer stacking abnormal information, which comprises the following steps: s1: setting exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, and the ratio of the number of the exposure units in the range of the edge of the wafer in the exposure units for stacking anomaly measurement to the number of the exposure units in the range of the edge of the wafer in the wafer plane is any value between 4:1 and 6: 1; s2: designing a measuring point photomask layout, arranging measuring points positioned outside the wafer surface in the range of the exposure unit in the wafer surface, and ensuring that the number of the measuring points in each exposure unit for stacking abnormity measurement is equal; s3: and acquiring superposition abnormal information of a measuring point in each exposure unit in the exposure units for measuring the superposition abnormality, and further acquiring wafer superposition abnormal information.
Further, the number of exposure units for overlay anomaly measurement set in step S1 is 30.
Further, in step S1, the number of exposure units located in the wafer edge range among the exposure units used for the overlay anomaly measurement and the number of exposure units in the wafer plane except the wafer edge range are set to be 5: 1.
Further, in step S2, the measuring point located outside the wafer surface within the range of the exposure unit is moved to a position within the wafer surface close to the edge line of the wafer, so as to set the measuring point located outside the wafer surface within the range of the exposure unit within the wafer surface
The wafer stacking abnormity compensation method provided by the invention has the advantages that by arranging the exposure unit for stacking abnormity measurement, wherein the number of exposure units for the overlay anomaly measurement is any value between 25 and 35, and the ratio of the number of exposure units within the wafer edge range among the exposure units used for the overlay anomaly measurement to the number of exposure units within the wafer plane other than the wafer edge range is any value between 4:1 and 6:1, and setting measuring points in each exposure unit for stacking anomaly measurement to ensure the equal number of the measuring points in each exposure unit for stacking anomaly measurement, increasing the information quantity proportion of stacking anomaly in the wafer edge range, the obtained wafer stacking abnormal information can reflect the stacking abnormal information of the wafer edge, so that the wafer edge stacking compensation effect is better, and the product yield is improved.
Drawings
FIG. 1 is a diagram illustrating a PDF wafer stacking exception.
FIG. 2 is a diagram illustrating a wafer stacking exception vector.
FIG. 3 is a diagram illustrating a wafer overlay anomaly measurement according to the prior art.
Fig. 4 is a schematic view illustrating wafer overlay anomaly information measurement according to an embodiment of the present invention.
FIG. 5a is a schematic view of a layout of measurement points of an exposure unit located in a wafer plane.
FIG. 5b is a diagram illustrating the layout of the measurement points of the exposure unit located at the edge of the wafer.
Fig. 6a is a schematic view of compensation effect in the wafer plane for performing overlay compensation on the wafer by using the wafer overlay abnormal information obtained from the wafer overlay abnormal information measurement schematic view shown in fig. 4.
Fig. 6b is a schematic view of the compensation effect of the wafer edge for performing overlay compensation on the wafer by using the wafer overlay abnormal information obtained from the wafer overlay abnormal information measurement schematic view shown in fig. 4.
Fig. 7a is a schematic diagram of compensation effect in the wafer plane for performing overlay compensation on the wafer by using the wafer overlay abnormal information obtained by all the exposure units, 30 exposure units and 13 exposure units in the wafer plane, respectively.
Fig. 7b is a schematic diagram of the compensation effect of the wafer edge for performing overlay compensation on the wafer by using the wafer overlay abnormal information obtained by all the exposure units, 30 exposure units and 13 exposure units in the wafer surface.
The reference numerals of the main elements in the figures are explained as follows:
401. 402, 403, an exposure unit; 110. wafer edge line.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Currently, all the overlay abnormal value-supplementing methods measure overlay information in 13 exposure units (shots) in a wafer surface, measure 9 points in each exposure unit, and then perform value-supplementing according to the measured overlay abnormal information in the 13 exposure units. Specifically, referring to fig. 3, fig. 3 is a schematic view illustrating measurement of wafer overlay anomaly information in the prior art, for example, in fig. 3, the exposure unit D and the exposure unit U are 13 selected exposure units, fig. 3 also shows the distribution of the 13 exposure units, and the 13 exposure units are uniformly distributed in the wafer plane. However, if the entire wafer is measured after the overlay anomaly compensation is performed according to the overlay anomaly information obtained in fig. 3, it is obvious that the anomaly vector around the wafer is still large, and the anomalies are mainly concentrated around the wafer, so the existing method for compensating the overlay anomaly information in 13 exposure units in the measured wafer plane cannot effectively compensate the overlay anomaly around the wafer.
In an embodiment of the present invention, a method for compensating for a wafer stacking fault is provided, which includes: s1: setting exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, and the ratio of the number of the exposure units in the range of the edge of the wafer in the exposure units for stacking anomaly measurement to the number of the exposure units in the range of the edge of the wafer in the wafer plane is any value between 4:1 and 6: 1; s2: designing a measuring point photomask layout, arranging measuring points positioned outside the wafer surface in the range of the exposure unit in the wafer surface, and ensuring that the number of the measuring points in each exposure unit for stacking abnormity measurement is equal; s3: acquiring stacking abnormal information of a measuring point in each exposure unit in the exposure units for stacking abnormal measurement, and further acquiring wafer stacking abnormal information; s4: obtaining a superposition anomaly compensation value according to the wafer superposition anomaly information obtained in the step S3; and S5: and performing superposition compensation on the wafer according to the superposition abnormal compensation value obtained in the step S4.
Specifically, referring to fig. 4, fig. 4 is a schematic view illustrating measurement of wafer stacking anomaly information according to an embodiment of the present invention, as shown in fig. 4, the exposure unit D, the exposure unit U, and the exposure unit E are configured as exposure units for stacking anomaly measurement, and all the exposure units E and some of the exposure units D and U are exposure units located in the edge range of the wafer, and only a small number of the exposure units D and U are located in the portion of the wafer near the center of the circle, so that the proportion of stacking anomaly information in the edge range of the wafer is increased, and the obtained wafer stacking anomaly information can reflect stacking anomaly information of the edge of the wafer more.
Specifically, in one embodiment, the number of exposure units for overlay anomaly measurement set in step S1 is 30. More specifically, in one embodiment, in step S1, the number of exposure units located within the wafer edge range among the exposure units used for overlay anomaly measurement and the number of exposure units within the wafer plane except for the wafer edge range are set to be 5: 1. Thus, the number of exposure units in the wafer edge area is 25, and the number of exposure units in the wafer surface other than the wafer edge area (i.e., the exposure units in the portion of the wafer near the center of the circle) is 5. For example, for a 147nm radius wafer, the ratio of the number of exposure units located within the edge of the wafer in the range of 135nm to 147nm to the number of exposure units located in the range of 0nm to 135nm is 5: 1.
Specifically, in one embodiment, the exposure unit located within the edge of the wafer is moved to the edge of the wafer by another exposure unit, so that the exposure unit is at least partially located outside the wafer surface. If the exposure unit 401 is moved one more unit to the left edge of the wafer, a portion of the unit will be outside the wafer edge line 110.
Specifically, in one embodiment, the number of measurement points in each exposure unit for overlay anomaly measurement is 9.
Specifically, in one embodiment, in step S2, in order to ensure that the number of measurement points in each exposure unit for overlay anomaly measurement is equal, when designing the metrology point mask layout, the measurement points outside the wafer within the exposure unit are set within the wafer plane. Specifically, referring to fig. 4, fig. 5a and fig. 5b, fig. 5a is a schematic diagram of a layout of measurement points of exposure units located in a wafer plane, and fig. 5b is a schematic diagram of a layout of measurement points of exposure units located at a wafer edge. The metrology points in the exposure unit 403 in the wafer plane in FIG. 4 are laid out as shown in FIG. 5a, with all of the metrology points in the wafer plane; the layout of the measuring points in the exposure unit 402 on the edge of the wafer in fig. 4 is as shown in fig. 5b, and the same layout as that shown in fig. 5a is adopted, so that the measuring points 501 are located outside the edge line 110 of the wafer, that is, the newly added exposure unit has an incomplete exposure unit, and the measuring point position in the incomplete exposure unit exceeds the measuring range, in order to ensure that the overlay abnormal information of the exposure unit on the edge of the wafer is accurately measured, it is required to ensure that the number of the measuring points in the exposure unit on the edge is equal to the number of the measuring points of the exposure unit on the center portion of the wafer, that is, to ensure that the exposure unit on the edge does not lose the measuring points, the measuring points 501 located outside the edge line 110 of the wafer need to be moved into the measurable range, for example, the moved measuring points are 502, so that the overlay information of the edge of the. In one embodiment, the measurement point 501 outside the wafer edge line 110 is moved within the measurable range and the moved measurement point approaches the wafer edge line 110, i.e., the wafer edge measurement point is pushed as close as possible to the nominal measurement point. Therefore, the superposition abnormal information of the wafer edge can be obtained more optimally. In one embodiment, the layout of the measurement points outside the wafer edge line 110 is located closer to the wafer edge line 110 when the measurement point reticle layout is designed.
In an embodiment, in step S4, the wafer stacking anomaly information is obtained through an average calculation, so as to obtain a stacking anomaly compensation value. In step S5, any overlay compensation method may be used to perform overlay compensation on the wafer according to the obtained overlay abnormal compensation value.
Specifically, please refer to fig. 6a and 6b, in which fig. 6a is a schematic diagram of a compensation effect in a wafer plane for performing stacking compensation on a wafer by using the wafer stacking abnormality information obtained from the schematic diagram of measuring the wafer stacking abnormality information shown in fig. 4, fig. 6b is a schematic diagram of a compensation effect in a wafer edge for performing stacking compensation on a wafer by using the wafer stacking abnormality information obtained from the schematic diagram of measuring the wafer stacking abnormality information shown in fig. 4, as shown in fig. 6a, a maximum improvement amount of the wafer center stacking abnormality is 1.19nm, and a maximum improvement amount of the wafer edge stacking abnormality is 3.75 nm. Although the stacking compensation capability of the central portion of the wafer is inferior to that of the edge portion of the wafer, the stacking compensation of the central portion of the wafer is within the range of the stacking abnormality threshold value, and simultaneously the stacking abnormality compensation capability of the edge of the wafer is greatly improved, thereby improving the overall stacking abnormality compensation capability in the plane of the wafer.
In the present invention, 30 exposure units are selected for overlay anomaly measurement, and certainly, more exposure units can be selected for measurement, but at the same time, the workload is increased, as shown in fig. 7a and 7b, fig. 7a is a schematic diagram of compensation effect in a wafer plane for performing overlay compensation on a wafer by using wafer overlay anomaly information obtained by all exposure units, 30 exposure units and 13 exposure units in the wafer plane, and fig. 7b is a schematic diagram of compensation effect on a wafer edge for performing overlay compensation on a wafer by using wafer overlay anomaly information obtained by all exposure units, 30 exposure units and 13 exposure units in the wafer plane. As shown in fig. 7a and 7b, the compensation effect of the stacking compensation of the wafer by using the wafer stacking abnormality information obtained by 13 exposure units in the prior art is the worst, the product yield is low, the effect of the stacking compensation of the wafer by using the wafer stacking abnormality information obtained by 100 exposure units is substantially the same as the effect of the stacking compensation of the wafer by using the wafer stacking abnormality information obtained by 30 exposure units in the present invention, but the workload for obtaining the stacking abnormality information of 30 exposure units is much smaller than that for obtaining the stacking abnormality information of 100 exposure units, and therefore, the wafer stacking abnormality information obtained by selecting 30 exposure units is selected.
In an embodiment of the present invention, a method for measuring wafer overlay anomaly information is further provided, where the method includes: s1: setting exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, and the ratio of the number of the exposure units in the range of the edge of the wafer in the exposure units for stacking anomaly measurement to the number of the exposure units in the range of the edge of the wafer in the wafer plane is any value between 4:1 and 6: 1; s2: designing a measuring point photomask layout, arranging measuring points positioned outside the wafer surface in the range of the exposure unit in the wafer surface, and ensuring that the number of the measuring points in each exposure unit for stacking abnormity measurement is equal; s3: and acquiring superposition abnormal information of a measuring point in each exposure unit in the exposure units for measuring the superposition abnormality, and further acquiring wafer superposition abnormal information.
Specifically, referring to fig. 4, fig. 4 is a schematic view illustrating measurement of wafer stacking anomaly information according to an embodiment of the present invention, as shown in fig. 4, the exposure unit D, the exposure unit U, and the exposure unit E are configured as exposure units for stacking anomaly measurement, and all the exposure units E and some of the exposure units D and U are exposure units located in the edge range of the wafer, and only a small number of the exposure units D and U are located in the portion of the wafer near the center of the circle, so that the proportion of stacking anomaly information in the edge range of the wafer is increased, and the obtained wafer stacking anomaly information can reflect stacking anomaly information of the edge of the wafer more.
Specifically, in one embodiment, the number of exposure units for overlay anomaly measurement set in step S1 is 30. More specifically, in one embodiment, in step S1, the number of exposure units located within the wafer edge range among the exposure units used for overlay anomaly measurement and the number of exposure units within the wafer plane except for the wafer edge range are set to be 5: 1. Thus, the number of exposure units in the wafer edge area is 25, and the number of exposure units in the wafer surface other than the wafer edge area (i.e., the exposure units in the portion of the wafer near the center of the circle) is 5. For example, for a 147nm radius wafer, the ratio of the number of exposure units located within the edge of the wafer in the range of 135nm to 147nm to the number of exposure units located in the range of 0nm to 135nm is 5: 1.
Specifically, in one embodiment, the exposure unit located within the edge of the wafer is moved to the edge of the wafer by another exposure unit, so that the exposure unit is at least partially located outside the wafer surface. For example, if the exposure unit 401 is moved one more unit to the left, a portion of it will be outside the wafer edge line 110.
Specifically, in one embodiment, the number of measurement points in each exposure unit for overlay anomaly measurement is 9.
Specifically, in one embodiment, in step S2, in order to ensure that the number of measurement points in each exposure unit for overlay anomaly measurement is equal, when designing the metrology point mask layout, the measurement points outside the wafer within the exposure unit are set within the wafer plane. Specifically, referring to fig. 4, fig. 5a and fig. 5b, fig. 5a is a schematic diagram of a layout of measurement points of exposure units located in a wafer plane, and fig. 5b is a schematic diagram of a layout of measurement points of exposure units located at a wafer edge. The metrology points in the exposure unit 403 in the wafer plane in FIG. 4 are laid out as shown in FIG. 5a, with all of the metrology points in the wafer plane; the layout of the measuring points in the exposure unit 402 on the edge of the wafer in fig. 4 is as shown in fig. 5b, and the same layout as that shown in fig. 5a is adopted, so that the measuring points 501 are located outside the edge line 110 of the wafer, that is, the newly added exposure unit has an incomplete exposure unit, and the measuring point position in the incomplete exposure unit exceeds the measuring range, in order to ensure that the overlay abnormal information of the exposure unit on the edge of the wafer is accurately measured, it is required to ensure that the number of the measuring points in the exposure unit on the edge is equal to the number of the measuring points of the exposure unit on the center portion of the wafer, that is, to ensure that the exposure unit on the edge does not lose the measuring points, the measuring points 501 located outside the edge line 110 of the wafer need to be moved into the measurable range, for example, the moved measuring points are 502, so that the overlay information of the edge of the. In one embodiment, the measurement point 501 outside the wafer edge line 110 is moved within the measurable range and the moved measurement point approaches the wafer edge line 110, i.e., the wafer edge measurement point is pushed as close as possible to the nominal measurement point. Therefore, the superposition abnormal information of the wafer edge can be obtained more optimally. In one embodiment, the layout of the measurement points outside the wafer edge line 110 is located closer to the wafer edge line 110 when the measurement point reticle layout is designed.
In summary, by setting the exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, the ratio of the number of the exposure units in the exposure units for stacking anomaly measurement within the wafer edge range to the number of the exposure units in the wafer surface except the wafer edge range is any value between 4:1 and 6:1, and setting the measurement points in each exposure unit for stacking anomaly measurement, the number of the measurement points in each exposure unit for stacking anomaly measurement is ensured to be equal, the information quantity ratio of the stacking anomaly within the wafer edge range is increased, so that the obtained wafer stacking anomaly information can reflect the stacking anomaly information of the wafer edge more, the wafer edge stacking compensation effect is better, and the product yield is improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for compensating for a stacking fault of a wafer, comprising:
s1: setting exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, and the ratio of the number of the exposure units in the range of the edge of the wafer in the exposure units for stacking anomaly measurement to the number of the exposure units in the range of the edge of the wafer in the wafer plane is any value between 4:1 and 6: 1;
s2: designing a measuring point photomask layout, arranging measuring points positioned outside the wafer surface in the range of the exposure unit in the wafer surface, and ensuring that the number of the measuring points in each exposure unit for stacking abnormity measurement is equal;
s3: acquiring stacking abnormal information of a measuring point in each exposure unit in the exposure units for stacking abnormal measurement, and further acquiring wafer stacking abnormal information;
s4: obtaining a superposition anomaly compensation value according to the wafer superposition anomaly information obtained in the step S3; and
s5: and performing superposition compensation on the wafer according to the superposition abnormal compensation value obtained in the step S4.
2. The method as claimed in claim 1, wherein the number of the exposure units for stacking fault measurement set in step S1 is 30.
3. The wafer stacking fault compensation method according to any one of claims 1 or 2, wherein the step S1 is performed such that the ratio of the number of exposure units located within the wafer edge range among the exposure units used for the stacking fault measurement to the number of exposure units within the wafer plane except for the wafer edge range is 5: 1.
4. The method as claimed in claim 1, wherein the exposure unit located within the edge of the wafer is moved to the edge side of the wafer by one more exposure unit so that the exposure unit is located at least partially out of the wafer plane.
5. The method as claimed in claim 1, wherein the number of measurement points in each exposure unit for stacking fault measurement is 9.
6. The method as claimed in claim 1, wherein the measuring point located outside the wafer surface within the exposure unit range is moved to a position within the wafer surface close to the edge line of the wafer in step S2, so as to locate the measuring point located outside the wafer surface within the exposure unit range within the wafer surface.
7. A method for measuring wafer overlay anomaly information comprises:
s1: setting exposure units for stacking anomaly measurement, wherein the number of the exposure units for stacking anomaly measurement is any value between 25 and 35, and the ratio of the number of the exposure units in the range of the edge of the wafer in the exposure units for stacking anomaly measurement to the number of the exposure units in the range of the edge of the wafer in the wafer plane is any value between 4:1 and 6: 1;
s2: designing a measuring point photomask layout, arranging measuring points positioned outside the wafer surface in the range of the exposure unit in the wafer surface, and ensuring that the number of the measuring points in each exposure unit for stacking abnormity measurement is equal;
s3: and acquiring superposition abnormal information of a measuring point in each exposure unit in the exposure units for measuring the superposition abnormality, and further acquiring wafer superposition abnormal information.
8. The method as claimed in claim 7, wherein the number of the exposure units for overlay anomaly measurement set in step S1 is 30.
9. The wafer stacking fault information measurement method as claimed in any one of claims 7 or 8, wherein the step S1 is performed such that the ratio of the number of exposure units located within the wafer edge range among the exposure units used for stacking fault measurement to the number of exposure units within the wafer plane except the wafer edge range is 5: 1.
10. The method as claimed in claim 7, wherein in step S2, the measuring point located outside the wafer surface within the exposure unit range is moved to a position within the wafer surface close to the wafer edge line, so as to locate the measuring point located outside the wafer surface within the exposure unit range within the wafer surface.
CN202010466230.2A 2020-05-28 2020-05-28 Wafer stacking anomaly compensation method and wafer stacking anomaly information measurement method Pending CN111580349A (en)

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Application publication date: 20200825