CN111565500A - LED drive circuit with high power factor and low harmonic and LED device - Google Patents
LED drive circuit with high power factor and low harmonic and LED device Download PDFInfo
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Abstract
Description
技术领域technical field
本发明属于LED驱动的技术领域,尤其涉及一种高功率因数低谐波的LED驱动电路及LED装置。The invention belongs to the technical field of LED driving, and in particular relates to an LED driving circuit and an LED device with high power factor and low harmonics.
背景技术Background technique
传统的LED驱动电路一般采用恒流驱动,而对于利用运算放大器和开关元件实现的恒流驱动一般存在着功率因数低和谐波失真过大的问题,尤其对于大功率的LED驱动电路,其功率因数低和谐波失真的问题就更明显。故传统的LED驱动电路将其改进为通过利用分段式驱动电路对LED进行驱动,从而提高其功率因数,但是该种驱动方式下仍然没有解决其谐波失真过大的问题。因此,需要一种高功率因数低谐波的LED驱动电路,用以解决LED驱动中存在的谐波失真过大的问题。The traditional LED drive circuit generally adopts constant current drive, and the constant current drive realized by operational amplifiers and switching elements generally has the problems of low power factor and excessive harmonic distortion, especially for high-power LED drive circuits, its power The problems of low factor and harmonic distortion are even more pronounced. Therefore, the traditional LED driving circuit is improved to drive the LED by using a segmented driving circuit, thereby improving its power factor, but this driving mode still does not solve the problem of excessive harmonic distortion. Therefore, an LED driving circuit with high power factor and low harmonics is required to solve the problem of excessive harmonic distortion in LED driving.
发明内容SUMMARY OF THE INVENTION
有鉴于此,本发明实施例提供了一种高功率因数低谐波的LED驱动电路及LED装置,旨在解决传统的技术方案中存在的谐波失真过大的问题。In view of this, the embodiments of the present invention provide an LED driving circuit and an LED device with high power factor and low harmonics, aiming to solve the problem of excessive harmonic distortion in the traditional technical solution.
本发明实施例的第一方面提供了一种高功率因数低谐波的LED驱动电路,所述高功率因数低谐波的LED驱动电路包括分压电路、LED组件、N个钳位电路、N+1个恒流电路以及限流组件;A first aspect of the embodiments of the present invention provides an LED driving circuit with high power factor and low harmonics. The LED driving circuit with high power factor and low harmonics includes a voltage divider circuit, an LED component, N clamping circuits, N +1 constant current circuit and current limiting components;
所述分压电路配置为当接入直流电压时,对所述直流电压进行分压以生成参考电压;The voltage dividing circuit is configured to divide the DC voltage to generate a reference voltage when the DC voltage is connected;
所述LED组件包括依次串联的N+1个负载,所述N+1个负载包括第一负载至第N+1个负载,所述第一负载的正极接入直流电压,第k个负载的负极与第k+1个负载的正极连接;其中,N为大于等于1的整数,k为小于等于于N的正整数;The LED assembly includes N+1 loads connected in series in sequence, the N+1 loads include the first load to the N+1th load, the positive pole of the first load is connected to the DC voltage, and the kth load is connected to the DC voltage. The negative pole is connected to the positive pole of the k+1th load; wherein, N is an integer greater than or equal to 1, and k is a positive integer less than or equal to N;
第i个钳位电路,与所述分压电路连接,配置为当所述参考电压小于所述第i个钳位电路的钳位电压且当所述参考电压大于等于所述第i-1个钳位电路的钳位电压时,输出与所述参考电压相等的模拟量信号;其中,i为小于等于N的正整数;The i-th clamping circuit is connected to the voltage divider circuit, and is configured to be configured when the reference voltage is less than the clamping voltage of the i-th clamping circuit and when the reference voltage is greater than or equal to the i-1-th clamping circuit When the clamping voltage of the clamping circuit is used, an analog signal equal to the reference voltage is output; wherein, i is a positive integer less than or equal to N;
第j个恒流电路,与所述第j个钳位电路、第j个负载、第j+1个负载以及所述限流组件连接,配置为根据所述模拟量信号对输出电流进行控制以使所述输出电流与所述模拟量信号成正比;其中,j为小于等于N的正整数;The jth constant current circuit is connected to the jth clamping circuit, the jth load, the j+1th load and the current limiting component, and is configured to control the output current according to the analog signal to Make the output current proportional to the analog signal; wherein, j is a positive integer less than or equal to N;
第N+1个恒流电路,与第N+1个负载、所述分压电路以及所述限流组件连接,配置为当所述参考电压大于等于所述第N个钳位电路的钳位电压且所述参考电压小于上限电压时,对输出电流进行控制以使所述输出电流与所述参考电压成正比;The N+1 th constant current circuit is connected to the N+1 th load, the voltage dividing circuit and the current limiting component, and is configured to be configured when the reference voltage is greater than or equal to the clamping force of the N th clamping circuit When the reference voltage is less than the upper limit voltage, the output current is controlled so that the output current is proportional to the reference voltage;
所述限流组件配置为对所述恒流电路的输出电流进行限流。The current limiting component is configured to limit the output current of the constant current circuit.
在第一方面的其中一实施例,N个钳位电路均包括钳位组件,所述钳位组件包括第一运算放大器、第二运算放大器、第一场效应管和第一电阻;In one embodiment of the first aspect, each of the N clamp circuits includes a clamp component, and the clamp component includes a first operational amplifier, a second operational amplifier, a first field effect transistor, and a first resistor;
所述第一运算放大器的同相输入端为钳位电路的参考电压输入端,所述第二运算放大器的同相输入端为钳位电路的钳位电压输入端,所述第一运算放大器的反相输入端、第二运算放大器的反相输入端和第一场效应管的源极和第一电阻的第一端共同构成钳位电路的输出端,所述第一运算放大器的输出端和第二运算放大器的输出端共接于第一场效应管的栅极,所述第一场效应管的漏极与内部电源连接,所述第一电阻的第二端与电源地连接。The non-inverting input terminal of the first operational amplifier is the reference voltage input terminal of the clamping circuit, the non-inverting input terminal of the second operational amplifier is the clamping voltage input terminal of the clamping circuit, and the inverting phase of the first operational amplifier is The input end, the inverting input end of the second operational amplifier, the source of the first field effect transistor and the first end of the first resistor together form the output end of the clamping circuit, the output end of the first operational amplifier and the second The output end of the operational amplifier is commonly connected to the gate of the first field effect transistor, the drain of the first field effect transistor is connected to the internal power supply, and the second end of the first resistor is connected to the power supply ground.
在第一方面的其中一实施例,N个恒流电路均包括恒流组件,所述恒流组件包括第三运算放大器和第二场效应管;In one embodiment of the first aspect, each of the N constant current circuits includes a constant current component, and the constant current component includes a third operational amplifier and a second field effect transistor;
所述第三运算放大器的同相输入端为恒流组件的模拟量信号输入端,所述第三运算放大器的输出端与第二场效应管的栅极连接,所述第三运算放大器的负相输入端与第二场效应管的源极共同构成恒流组件的输出电流输出端,所述第二场效应管的漏极为恒流组件的输入电压输入端;The non-inverting input end of the third operational amplifier is the analog signal input end of the constant current component, the output end of the third operational amplifier is connected to the gate of the second field effect transistor, and the negative phase of the third operational amplifier is The input end and the source of the second field effect transistor together form the output current output end of the constant current component, and the drain of the second field effect transistor is the input voltage input end of the constant current component;
所述第N+1个恒流电路包括第四运算放大器和第三场效应管;The N+1th constant current circuit includes a fourth operational amplifier and a third field effect transistor;
所述第四运算放大器的同相输入端为第N+1个恒流电路的上限电压输入端,所述第四运算放大器的输出端与第三场效应管的栅极连接,所述第四运算放大器的负相输入端与第三场效应管的源极共同构成第N+1个恒流电路的输出电流输出端,所述第三场效应管的漏极为第N+1个恒流电路的输入电压输入端。The non-inverting input terminal of the fourth operational amplifier is the upper limit voltage input terminal of the N+1th constant current circuit, the output terminal of the fourth operational amplifier is connected to the gate of the third field effect transistor, and the fourth operational amplifier The negative-phase input terminal of the amplifier and the source of the third field effect transistor together form the output current output terminal of the N+1th constant current circuit, and the drain of the third field effect transistor is the output terminal of the N+1th constant current circuit. Input voltage input terminal.
在第一方面的其中一实施例,所述分压电路包括第二电阻和第三电阻,所述第二电阻的第二端与第三电阻的第一端共同构成分压电路的参考电压输出端;所述第二电阻的第一端为分压电路的直流电压第一输入端,所述第三电阻的第二端为分压电路的直流电压第二输入端。In one embodiment of the first aspect, the voltage divider circuit includes a second resistor and a third resistor, and the second end of the second resistor and the first end of the third resistor together form a reference voltage output of the voltage divider circuit The first end of the second resistor is the first input end of the DC voltage of the voltage divider circuit, and the second end of the third resistor is the second input end of the DC voltage of the voltage divider circuit.
在第一方面的其中一实施例,所述高功率因数低谐波的LED驱动电路还包括:In an embodiment of the first aspect, the high power factor and low harmonic LED driving circuit further includes:
与交流电连接,用于对交流电进行整流以生成直流电压的整流电路。A rectifier circuit that is connected to alternating current and used to rectify alternating current to generate direct current voltage.
在第一方面的其中一实施例,所述整流电路包括第一二极管、第二二极管、第三二极管和第四二极管;所述第一二极管的正极与第四二极管的正极共同构成整流电路的第二直流电压输出端,所述第一二极管的负极与第二二极管的正极共同构成整流电路的第一交流电输入端,所述第二二极管的负极与第三二极管的负极共同构成整流电路的第一直流电压输出端,所述第三二极管的正极与第四二极管的负极共同构成整流电路的第二交流电输入端。In one embodiment of the first aspect, the rectifier circuit includes a first diode, a second diode, a third diode and a fourth diode; the anode of the first diode is connected to the first diode The positive poles of the four diodes together form the second DC voltage output end of the rectifier circuit, the negative pole of the first diode and the positive pole of the second diode together form the first alternating current input end of the rectifier circuit, the second The cathode of the diode and the cathode of the third diode together constitute the first DC voltage output end of the rectifier circuit, and the anode of the third diode and the cathode of the fourth diode together constitute the second alternating current of the rectifier circuit input.
本发明实施例的第二方面提供一种LED装置,LED装置包括第一方面任一实施例所述的高功率因数低谐波的LED驱动电路。A second aspect of the embodiments of the present invention provides an LED device, where the LED device includes the LED driving circuit with high power factor and low harmonics according to any embodiment of the first aspect.
上述的高功率因数低谐波的LED驱动电路通过设置N个钳位电路和N+1个恒流电路;当参考电压小于第i个钳位电路的钳位电压且当参考电压大于等于第i-1个钳位电路的钳位电压时,第i个钳位电路输出与参考电压相等的模拟量信号给第j个恒流电路,第j个恒流电路根据模拟量信号对输出电流进行控制以使所述输出电流与模拟量信号成正比;第N+1个恒流电路当所述参考电压大于等于所述第N个钳位电路的钳位电压且所述参考电压小于上限电压时,对输出电流进行控制以使所述输出电流与参考电压成正比;因此在N个钳位电路和N+1个恒流电路因此在从而使得LED驱动电路的输出电流保持与直流电压成正比,减小了LED驱动电路的谐波失真。The above-mentioned LED drive circuit with high power factor and low harmonics is set by setting N clamping circuits and N+1 constant current circuits; when the reference voltage is less than the clamping voltage of the ith clamping circuit and when the reference voltage is greater than or equal to the ith When the clamping voltage of -1 clamping circuit, the ith clamping circuit outputs an analog signal equal to the reference voltage to the jth constant current circuit, and the jth constant current circuit controls the output current according to the analog signal so that the output current is proportional to the analog signal; when the reference voltage of the N+1th constant current circuit is greater than or equal to the clamping voltage of the Nth clamping circuit and the reference voltage is less than the upper limit voltage, The output current is controlled so that the output current is proportional to the reference voltage; therefore, the N clamp circuits and the N+1 constant current circuits are therefore in so that the output current of the LED driver circuit remains proportional to the DC voltage, minus The harmonic distortion of the LED drive circuit is reduced.
附图说明Description of drawings
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only for the present invention. In some embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.
图1为本申请的一实施例提供的高功率因数低谐波的LED驱动电路的原理框图;FIG. 1 is a schematic block diagram of an LED driving circuit with high power factor and low harmonics provided by an embodiment of the present application;
图2为本申请一实施例提供的钳位组件的电路原理图;FIG. 2 is a schematic circuit diagram of a clamping component provided by an embodiment of the present application;
图3为本申请一实施例提供的恒流组件的电路原理图;FIG. 3 is a schematic circuit diagram of a constant current component provided by an embodiment of the present application;
图4为本申请一实施例提供的第N+1个恒流电路的电路原理图;4 is a circuit schematic diagram of an N+1 th constant current circuit provided by an embodiment of the present application;
图5为本申请一实施例提供的分压电路的电路原理图;FIG. 5 is a circuit schematic diagram of a voltage divider circuit provided by an embodiment of the present application;
图6为本申请另一实施例提供的高功率因数低谐波的LED驱动电路的原理框图;6 is a schematic block diagram of an LED driving circuit with high power factor and low harmonics provided by another embodiment of the present application;
图7为本申请一实施例提供的整流电路的电路原理图;FIG. 7 is a circuit schematic diagram of a rectifier circuit provided by an embodiment of the present application;
图8为本申请一实施例提供的高功率因数低谐波的LED驱动电路的电路原理图;FIG. 8 is a circuit schematic diagram of an LED driving circuit with high power factor and low harmonics provided by an embodiment of the present application;
图9为本申请高功率因数低谐波的LED驱动电路的输出电压电流波形。FIG. 9 is the output voltage and current waveforms of the LED driving circuit with high power factor and low harmonics of the present application.
具体实施方式Detailed ways
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.
如图1所示,本发明实施例提供了一种高功率因数低谐波的LED驱动电路,为了便于说明,仅示出了与本实施例相关的部分,详述如下,一种高功率因数低谐波的LED驱动电路,高功率因数低谐波的LED驱动电路1包括分压电路101、LED组件11、N个钳位电路、N+1个恒流电路以及限流组件14。As shown in FIG. 1 , an embodiment of the present invention provides an LED driving circuit with high power factor and low harmonics. For the convenience of description, only the parts related to this embodiment are shown. The details are as follows. A high power factor Low harmonic LED drive circuit, high power factor low harmonic
分压电路101配置为当接入直流电压时,对直流电压进行分压以生成参考电压。The voltage dividing
LED组件11包括依次串联的N+1个负载,N+1个负载包括第一负载111至第N+1个负载11n+1,第一负载111的正极接入直流电压,第k个负载的负极与第k+1个负载的正极连接;其中,N为大于等于1的整数,即相当于LED组件11至少包括2个负载;其中,k为不大于N的正整数。The
N个钳位电路中的第i个钳位电路12i与分压电路101连接,第i个钳位电路12i输入参考电压,第i个钳位电路12i还配置为当参考电压小于第i个钳位电路12i的钳位电压且当参考电压大于等于第i-1个钳位电路的钳位电压时,输出与参考电压相等的模拟量信号;其中,第i-1个钳位电路的钳位电压小于第i个钳位电路12i的钳位电压;其中,i为小于等于N的正整数,因为N是大于等于1的整数,因此i的最小值为1;需要注意的是,当N为1时,即i也为1的时候,则不存在第i-1个钳位电路,此时第一个钳位电路配置为当参考电压小于第一个钳位电路121的钳位电压,输出与参考电压相等的模拟量信号。The i-
N+1个恒流电路包括N个恒流电路和第N+1个恒流电路。其中,N个恒流电路中的第j个恒流电路13j分别与第j个钳位电路、第j个负载、第j+1个负载以及限流组件14连接;第j个恒流电路13j还配置为根据模拟量信号对输出电流进行控制以使输出电流与模拟量信号成正比;其中,j为小于等于N的正整数。第j个恒流电路13j的输出电流与模拟量信号成正比,模拟量信号与参考电压相等,而参考电压由直流电压分压得到,因此当第j个恒流电路13j输出电流与直流电压成正比,LED驱动电路谐波失真较小。The N+1 constant current circuits include N constant current circuits and an N+1 th constant current circuit. Among them, the jth constant
第N+1个恒流电路13n+1分别与第N+1个负载11n+1、分压电路101以及限流组件14连接;第N+1个恒流电路13n+1还配置为当参考电压大于等于第N个钳位电路的钳位电压且参考电压小于上限电压时,对输出电流进行控制以使输出电流与参考电压成正比。其中,上限电压为参考电压在正常情况下的直流电压能到达的峰值。因为参考电压由直流电压分压得到,参考电压的波形是与直流电压的波形相同的,而且第N+1个恒流电路13n+1输出电流是与参考电压的波形成正比的,所以第N+1个恒流电路13n+1的输出电流与直流电压成正比,因此在第N+1个恒流电路13n+1输出的时候,LED驱动电路的谐波失真小。The N+1th constant
限流组件14配置为对恒流电路的输出电流进行限流。The current limiting
如图2所示,在一个实施例中,N个钳位电路均包括钳位组件,钳位组件包括:第一运算放大器U1、第二运算放大器U2、第一场效应管Q1和第一电阻R1;第一运算放大器U1的同相输入端为钳位电路的参考电压输入端;第二运算放大器U2的同相输入端为钳位电路的钳位电压输入端;第一运算放大器U1的反相输入端、第二运算放大器U2的反相输入端和第一场效应管Q1的源极和第一电阻R1的第一端共同构成钳位电路的输出端;第一运算放大器U1的输出端和第二运算放大器U2的输出端共接于第一场效应管Q1的栅极;第一场效应管Q1的漏极与内部电源连接;第一电阻R1的第二端与电源地连接。As shown in FIG. 2, in one embodiment, each of the N clamping circuits includes a clamping component, and the clamping component includes: a first operational amplifier U1, a second operational amplifier U2, a first field effect transistor Q1 and a first resistor R1; the non-inverting input terminal of the first operational amplifier U1 is the reference voltage input terminal of the clamping circuit; the non-inverting input terminal of the second operational amplifier U2 is the clamping voltage input terminal of the clamping circuit; the inverting input terminal of the first operational amplifier U1 terminal, the inverting input terminal of the second operational amplifier U2, the source of the first field effect transistor Q1 and the first terminal of the first resistor R1 together form the output terminal of the clamping circuit; the output terminal of the first operational amplifier U1 and the first terminal of the first The output terminals of the two operational amplifiers U2 are commonly connected to the gate of the first field effect transistor Q1; the drain of the first field effect transistor Q1 is connected to the internal power supply; the second end of the first resistor R1 is connected to the power supply ground.
如图3所示,在一个实施例中,N个恒流电路均包括恒流组件,恒流组件包括第三运算放大器U3和第二场效应管Q2;第三运算放大器U3的同相输入端为恒流组件的模拟量信号输入端;第三运算放大器U3的输出端与第二场效应管Q2的栅极连接;第三运算放大器U3的负相输入端与第二场效应管Q2的源极共同构成恒流组件的输出电流输出端;第二场效应管Q2的漏极为恒流组件的输入电压输入端。As shown in FIG. 3, in one embodiment, the N constant current circuits include constant current components, and the constant current components include a third operational amplifier U3 and a second field effect transistor Q2; the non-inverting input terminal of the third operational amplifier U3 is The analog signal input terminal of the constant current component; the output terminal of the third operational amplifier U3 is connected to the gate of the second field effect transistor Q2; the negative phase input terminal of the third operational amplifier U3 is connected to the source of the second field effect transistor Q2 Together they form the output current output end of the constant current component; the drain of the second field effect transistor Q2 is the input voltage input end of the constant current component.
如图4所示,在一个实施例中,第N+1个恒流电路13n+1包括第四运算放大器U4和第三场效应管Q3;第四运算放大器U4的同相输入端为第N+1个恒流电路13n+1的上限电压输入端;第四运算放大器U4的输出端与第三场效应管Q3的栅极连接;第四运算放大器U4的负相输入端与第三场效应管Q3的源极共同构成第N+1个恒流电路13n+1的输出电流输出端;第三场效应管Q3的漏极为第N+1个恒流电路13n+1的输入电压输入端。As shown in FIG. 4, in one embodiment, the N+1th constant
如图5所示,在一个实施例中,分压电路101包括第二电阻R2和第三电阻R3,第二电阻R2的第二端与第三电阻R3的第一端共同构成分压电路101的输出端;第二电阻R2的第一端为分压电路101的直流电压第一输入端,第三电阻R3的第二端为分压电路101的直流电压第二输入端。As shown in FIG. 5 , in one embodiment, the
如图6所示,在一个实施例中,高功率因数低谐波的LED驱动电路1还包括整流电路105,整流电路105与交流电连接,用于对交流电进行整流以生成直流电压。As shown in FIG. 6 , in one embodiment, the
如图7所示,在一个实施例中,整流电路105包括第一二极管D1、第二二极管D2、第三二极管D3和第四二极管D4;第一二极管D1的正极与第四二极管D4的正极共同构成整流电路105的第二输出端,第一二极管D1的负极与第二二极管D2的正极共同构成整流电路105的第一输入端,第二二极管D2的负极与第三二极管D3的负极共同构成整流电路105的第一输出端,第三二极管D3的正极与第四二极管D4的负极共同构成整流电路105的第二输入端。As shown in FIG. 7, in one embodiment, the
下面结合工作原理对图8所示的作进一步说明,其中,图7所示的是N为2时的高功率因数低谐波的LED驱动电路的电路原理图,即高功率因数低谐波的LED驱动电路1包括整流电路105、分压电路101、LED组件11、两个钳位电路、三个恒流电路及限流组件14,限流组件14为电阻R4,其中LED组件11包括第一发光二极管L1、第二发光二极管L2和第三发光二极管L3;应该注意的是,本实施例并不是对高功率因数低谐波的LED驱动电路1进行限制,而是其中一个实例性说明,不能据此认为高功率因数低谐波的LED驱动电路1的N只能取值为2。其中整流电路105对交流电进行整流输出直流电压,第二电阻R2和第三电阻R3对直流电压进行分压并且输出参考电压。The following is a further description of what is shown in FIG. 8 in conjunction with the working principle, wherein, what is shown in FIG. 7 is the circuit schematic diagram of the LED drive circuit with high power factor and low harmonics when N is 2, that is, the high power factor and low harmonics. The
当参考电压不大于第一钳位电路121的钳位电压时,第一钳位电路121的第一运算放大器U1的正相输入端输入参考电压,第二运算放大器U2的正相输入端输入钳位电压V1,因为第一运算放大器U1的负相输入端、第二运算放大器U2的负相输入端、第一场效应管Q1的源极和第一电阻R1的第一端共接,第一运算放大器U1输出高电平给第一场效应管Q1的栅极,使得第一场效应管Q1导通,从而使得第一场效应管Q1的源极输出与参考电压相等的模拟量信号给第三运算放大器U3的正相输入端,因此第三运算放大器U3的输出端输出高电平给第一恒流电路131的第二场效应管Q2的栅极,使得第一恒流电路131的第二场效应管Q2导通,同时因为第三运算放大器U3的负相输入端、第二场效应管Q2的源极和限流组件14(第四电阻R4)的第一端共接,所以使得流过第一发光二极管L1的电流与模拟量信号成正比,从而使得流过第一发光二极管L1的电流与直流电压成正比,因此当只有第一发光二极管L1导通时,LED驱动电路的输出电流与直流电压成正比,谐波失真较小。When the reference voltage is not greater than the clamping voltage of the
当参考电压大于第一钳位电路121的钳位电压时,且参考电压不大于第二钳位电路122的钳位电压时,又因为第一钳位电路121的第三运算放大器U3的负相输入端电压大于正相输入端,因此第一钳位电路121的第三运算放大器U3的输出端输出低电平使得第一恒流模块121的第二场效应管Q2截止,此时第二钳位电路122输出与参考电压相等的模拟量给第二恒流模块132的使第二恒流模块132的第二场效应管Q2导通,使得流过第一发光二极管L1和第二发光二极管L2的电流与直流电压成正比,所以当第一发光二极管L1和第二发光二极管L2均导通时,LED驱动电路的输出电流与直流电压成正比,谐波失真较小。When the reference voltage is greater than the clamping voltage of the
当参考电压大于第二钳位电路122的钳位电压时,第二钳位电路122的第三运算放大器U3的负相输入端的电压大于正相输入端的电压,第二钳位电路122的第三运算放大器U3输出端输出低电平使得第二钳位电路122的第二场效应管Q2截止,同时第四运算放大器U4输出高电平给第三场效应管Q3,使得第三场效应管Q3导通,使得流过第一发光二极管L1、第二发光二极管L2和第三发光二极管L3的电流与参考电压成正比,从而使得流过第一发光二极管L1、第二发光二极管L2和第三发光二极管L3的电流与直流电压成正比,因此在第一发光二极管L1、第二发光二极管L2和第三发光二极管L3均导通的时候,本高功率因数低谐波的LED驱动电路1的输出电流和直流电压也是成正比的,谐波失真小。综上,高功率因数低谐波的LED驱动电路1的输出电流和直流电压的波形为如图9所示波形,其谐波失真较小。When the reference voltage is greater than the clamping voltage of the
本发明实施例还提供了一种LED装置,LED装置包括上列任一实施例的高功率因数低谐波的LED驱动电路,因为本实施例中的LED装置包括了上列任一项实施例的高功率因数低谐波的LED驱动电路,因此本实施例中的LED装置至少含有上列任一项实施例的高功率因数低谐波的LED驱动电路对应的有益效果。An embodiment of the present invention also provides an LED device, the LED device includes the high power factor and low harmonic LED drive circuit of any of the above embodiments, because the LED device in this embodiment includes any of the above embodiments Therefore, the LED device in this embodiment at least includes the beneficial effects corresponding to the LED driving circuit with high power factor and low harmonics of any one of the above-mentioned embodiments.
以上仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the present invention. Inside.
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