CN111556003A - Dual network encryption system - Google Patents
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- CN111556003A CN111556003A CN201911319209.3A CN201911319209A CN111556003A CN 111556003 A CN111556003 A CN 111556003A CN 201911319209 A CN201911319209 A CN 201911319209A CN 111556003 A CN111556003 A CN 111556003A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0478—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload applying multiple layers of encryption, e.g. nested tunnels or encrypting the content with a first key and then with at least a second key
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
Abstract
The invention discloses a double network encryption system, which comprises a sending end device and a receiving end device. The sending end device converts the data packet into a first encryption sequence through a first data encryptor in sequence, converts the first encryption sequence into a second encryption sequence through a PN sequence encryptor and outputs the second encryption sequence. The receiving end device obtains at least one second encryption sequence from the sending end device, and orderly recovers the second encryption sequence into the first encryption sequence through a PN sequence decryptor and recovers the first encryption sequence into the data packet through a first data decryptor.
Description
Technical Field
The present invention relates to a network encryption system, and more particularly, to a dual network encryption system.
Background
Advanced Encryption Standard (AES), also known as Rijndael Encryption, is a sector Encryption Standard adopted by the federal government in the united states. This standard, which is used to replace the original DES, has been analyzed by many parties and is widely used throughout the world. As of 2006, the only successful attack against AES was either a side-channel attack or a social engineering attack. The united states national security agency audits all of the final entrants who participate in the competitive AES as they are deemed to be able to meet the security needs of the united states government for the delivery of non-confidential documents.
The advanced encryption standard has been cracked for many times so far, in AES, a 128-bit key version has 10 encryption cycles, a 192-bit key version has 12 encryption cycles, and a 256-bit key version has 14 encryption cycles. By 2006, the most notable attacks were against the 128-bit key version of the 7 encryption round, the 192-bit key version of the 8 encryption round and the 256-bit key version of the 9 encryption round of AES. As the efficiency of hard devices increases, it is estimated that it is not far away that AES has been completely broken by brute force attack.
Furthermore, with the continued upgrading of hardware devices, artificial intelligence is now sufficient to reach the stage of commercialization hierarchy. With the processing power of hardware devices and the powerful computing power of artificial intelligence, the encryption standard widely used today is likely to be broken by a large number of operations via artificial intelligence, such as the generative challenge network (GAN). The English cipher used in the second time of big war can be cracked in 12 min 50 sec. For the above reasons, there is a need to improve the existing encryption technology to reduce the risk of the password or the secret key being cracked.
Disclosure of Invention
The present invention provides a dual network encryption system based on advanced encryption standard, which includes a sending end device and a receiving end device. The transmitting terminal device comprises a data source module and a file encryption module, wherein the file encryption module obtains at least one data packet from the data source module, converts the data packet into a first encryption sequence through a first data encryptor in sequence, converts the first encryption sequence into a second encryption sequence through a PN sequence encryptor, and outputs the second encryption sequence. The receiving end device comprises a data target module and a file decryption module, the receiving end device obtains at least one second encryption sequence from the sending end device, and the file decryption module restores the second encryption sequence into the first encryption sequence through a PN sequence decryptor in sequence, restores the first encryption sequence into the data packet through a first data decryptor and then transmits the data packet to the data target module.
Another objective of the present invention is to provide a sending end device based on advanced encryption standard, which includes a data source module and a file encryption module, wherein the file encryption module obtains at least one data packet from the data source module, sequentially converts the data packet into a first encryption sequence through a first data encryptor, and converts the first encryption sequence into a second encryption sequence through a PN sequence encryptor for output.
Another objective of the present invention is to provide a receiving end device based on the advanced encryption standard, which includes a data destination module and a file decryption module, wherein the file decryption module obtains at least a second encryption sequence from the transmitting end device, sequentially restores the second encryption sequence to a first encryption sequence through a PN sequence decryptor, and restores the first encryption sequence to a data packet through the first data decryptor, and then transmits the data packet to the data destination module.
The invention provides a double network encryption system, comprising: a sending end device, including a data source module and a file encryption module, the file encryption module obtains at least one data packet from the data source module, converts the data packet into a first encryption sequence through a first data encryptor in sequence, and outputs the first encryption sequence after converting the data packet into a second encryption sequence through a PN sequence encryptor; and a receiving end device, including a data target module and a file decipher module, the receiving end device obtains at least one second enciphered sequence from the sending end device, the file decipher module restores the second enciphered sequence to the first enciphered sequence through PN sequence decipher device in sequence, and restores the first enciphered sequence to the data packet through first data decipher device and then transmits to the data target module.
Preferably, the PN sequence encryptor includes a key and a linear feedback shift register, the linear feedback shift register performs a logic operation on a plurality of bit taps of the key to obtain an operand, and performs a logic operation on the operand and the first encryption sequence to obtain the second encryption sequence.
Preferably, the number of bits of the tap is an even number.
Preferably, the PN sequence decryptor includes a key and a linear feedback shift register, and the linear feedback shift register performs logical operation on a plurality of bit taps of the key to finally obtain an operand, and performs logical operation on the operand and the second encryption sequence to restore and obtain the first encryption sequence.
Preferably, the number of bits of the tap is an even number.
A sending terminal device comprises a data source module and a file encryption module, wherein the file encryption module obtains at least one data packet from the data source module, converts the data packet into a first encryption sequence through a first data encryptor in sequence, converts the first encryption sequence into a second encryption sequence through a PN sequence encryptor, and then outputs the second encryption sequence.
Preferably, the PN sequence encryptor taps a plurality of bits in the bit string of the first encryption sequence before performing a logical operation, and adds the tapped bits to the bit string of the first encryption sequence to obtain the second encryption sequence.
Preferably, the number of bits of the tap is an even number.
A receiving end device comprises a data target module and a file decryption module, wherein the file decryption module obtains at least one second encryption sequence from a sending end device, sequentially restores the second encryption sequence into a first encryption sequence through a PN sequence decryptor, restores the first encryption sequence into a data packet through a first data decryptor and then transmits the data packet to the data target module.
Preferably, the PN sequence decryptor includes a key and a linear feedback shift register, and the linear feedback shift register performs logical operation on a plurality of bit taps of the key to finally obtain an operand, and performs logical operation on the operand and the second encryption sequence to restore and obtain the first encryption sequence.
Preferably, the number of bits of the tap is an even number.
Compared with the prior art, the invention has the following advantages and effects:
1. the invention can effectively avoid the doubt that the password and the data are cracked by a double encryption mode.
2. The double encryption is executed through the PN sequence encryptor, the random characteristic of the encrypted data is effectively improved, the randomness of the encrypted data can be effectively increased, and the security of the data is further improved.
Drawings
Fig. 1 is a block diagram of a dual network encryption system according to the present invention.
Fig. 2 is a block diagram of a dual network encryption system according to the present invention (ii).
FIG. 3 is a schematic diagram of the logic operation of the PN sequence encryptor of the present invention.
Fig. 4 is a schematic diagram of the logic operation of the PN sequence decryptor of the present invention.
Description of reference numerals:
100 dual network encryption system
10 sending end device
11 data source module
12 file encryption module
121 first data encryptor
122 PN sequence encryptor
20 receiving end device
21 data object module
22 archive decryption module
221 PN sequence decryptor
222 first data decryptor
DA data transport layer
PK1 data packet
PK2 original data packet
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The embodiment of the invention comprises the following steps: referring to fig. 1, a block diagram of a dual network encryption system according to a preferred embodiment of the present invention is shown, as shown in the figure:
the embodiment of the present invention mainly discloses a dual network encryption system 100, which is used for encrypting and decrypting data transmitted by a plurality of devices when the devices transmit data to each other. The devices generating or receiving data may be computers, servers, mobile devices, internet of things devices (e.g., monitors, televisions, cloud-based hard disks, lamps, etc.), mass-production equipment or machines, etc., and are not limited in the present invention. In the present invention, the devices are defined as a transmitting device 10 as a data transmission source and a receiving device 20 corresponding to the transmitting device 10 for receiving data from the transmitting device 10 according to the transmission/reception relationship of signals. It should be noted that the present invention is not limited to the transmitting device 10 only performing the data encryption function and the receiving device 20 only performing the data decryption function, and specifically, the transmitting device 10 and the receiving device 20 both have the encryption and decryption functions to ensure that data are encrypted or decrypted by the mutual key during the bidirectional transmission process, which is described in advance herein.
The transmitting device 10 and the receiving device 20 may transmit data therebetween through a wired or wireless network. In one preferred embodiment, the sending end device 10 and the receiving end device 20 can transmit data via Internet (Internet), which is not limited in the present invention. In order to complete the functions of data encryption, decryption and transmission, the sending end device 10 and the receiving end device 20 at least include a processor, a storage unit, and a communication unit cooperating with each other to complete the work of corresponding functions, such as a physical line network card, a wireless network card, a Bluetooth module (Bluetooth), a Zigbee module (Zigbee), etc., and the transmission mode and the transmission interface of these signals do not belong to the intended scope of the present invention.
The sending end device 10 includes a data source module 11 and a file encryption module 12. The data source module 11 may be, for example, a permanent memory or a temporary memory, and is used for storing and managing data to be transmitted and encrypted. The file encryption module 12 may be a processor or microprocessor for performing encryption calculation processing, and is used to encrypt the data via a secret key and transmit the encrypted data to the receiving device 20.
The receiving device 20 includes a data object module 21 and a file decryption module 22. The data destination module 21, which may be a persistent memory or a temporary memory, is the same as the data source module 11 and is used for storing and managing the received data. The file decryption module 22 may be a processor or a microprocessor for performing decryption calculation processing, and is configured to decrypt the received encrypted data with the corresponding key and store the decrypted data in the data destination module 21.
Referring to fig. 2, fig. 3 and fig. 4, a second block diagram of the dual network encryption system of the present invention, a schematic diagram of the logic operation of the PN sequence encryptor, and a schematic diagram of the logic operation of the PN sequence decryptor are shown in the following, which are detailed below:
in the encrypted portion of the sender device 10, the file encryption module 12 obtains at least one data packet PK1 from the data source module 11, and the file encryption module 12 sequentially converts the data packet PK1 into a first encryption sequence through the first data encryptor 121 and a second encryption sequence through the PN sequence encryptor 122 for output. The first encryption sequence and the second encryption sequence described herein may be one or more bits, and are not necessarily limited to two or more bits; i.e. the encryption process can be performed bit by bit.
The first data encryptor 121 may encrypt the data according to a specification, such as Advanced Encryption Standard (AES), but is not limited in the present invention. The encrypted first encryption sequence is transmitted to the PN sequence encryptor 122 for encryption.
As shown in fig. 3, the PN Sequence encryptor 122 is mainly configured to encrypt the first encryption Sequence into a PN Sequence (Pseudo-noise Sequence) and output the PN Sequence. The PN sequence encryptor 122 includes a key, which includes a plurality of bits, and a Linear Feedback Shift Register (LFSR). In the embodiment, a 23-bit key is taken as an example for illustration, however, the number of bits of the key is not limited by the scope of the invention, and the data skewness can be effectively increased by increasing the number of bits of the key.
In this embodiment, when performing encryption, the PN sequence encryptor 122 first obtains a first encryption sequence from the output of the first data encryptor 121. Then, the linear feedback shift register performs logic operation after tapping the 18 th bit and the 23 rd bit, and obtains an operand according to the operation result. In order to maximize the linear feedback shift register, the number of taps should be an even number, and in a preferred embodiment, the taps can be interleaved to obtain an operand. After obtaining the operand, the linear feedback shift register further performs a logic operation on the operand and the nth bit of the first encryption sequence to add the nth bit of the second encryption sequence. In this embodiment, the logical operation is an Exclusive Or gate (XOR), and the operand is an output obtained by performing an XOR operation on the 18 th bit and the 23 rd bit; the nth bit of the second encryption sequence is an output obtained after the nth bit of the first encryption sequence and the operand are subjected to XOR. After the nth bit of the second encryption sequence is output, the nth bit of the second encryption sequence is simultaneously stacked to the first bit of the original secret key, and the last bit of the original secret key is deleted, so that the secret key is updated.
Expressed as a calculation, the second encryption sequence is calculated as follows:
wherein, b' [ n ]]Is the nth bit of the second encryption sequence, b n]Is the nth bit of the first encryption sequence, an[18]For bit 18, a of the key at the time of conversion of bit nn[23]Is the 23 rd bit of the key at the time of the n-th bit conversion. The calculation of the key update is as follows: a isn+1[1]＝b’[n]；an+1[x]＝an[x-1],x＝2-23；an+1[1]Is the value of the first bit of the updated key, an+1[x]The value of other bits of the updated key.
The encrypted data is transmitted to the receiving device 20 through the data transport layer DA, and then must be decrypted. In the decryption portion of the receiving device 20, the receiving device 20 obtains at least one second encryption sequence from the sending device 10, and the file decryption module 22 sequentially restores the second encryption sequence to the first encryption sequence through the PN sequence decryptor 221, and restores the first encryption sequence to the data packet PK1 through the first data decryptor 222, and then transmits the data packet PK1 to the data destination module 21.
As shown in fig. 3, the PN sequence decryptor 221 is mainly used to decrypt and restore the second encryption sequence to the original first encryption sequence. The PN sequence decryptor 221 includes a key (corresponding to the PN sequence encryptor 122) and a Linear Feedback Shift Register (LFSR).
When decryption is performed, the PN sequence decryptor 221 first obtains the second encryption sequence via the transmitting-end apparatus 10. Then, like the PN sequence encryptor 122, the linear feedback shift register performs a logic operation after tapping the 18 th bit and the 23 rd bit, and obtains an operand according to the operation result. It should be noted that the taps of the PN sequence decryptor 221 must be the same as the PN sequence encryptor 122. After obtaining the operand, the linear feedback shift register further performs a logic operation on the operand and the nth bit of the second encryption sequence and then restores the operand to the nth bit of the first encryption sequence. In the embodiment, corresponding to the file encryption module 12, the logical operation is Exclusive Or gate (XOR), the operand is the output obtained by the XOR of the 18 th bit AND the 23 rd bit, AND in principle, the PN sequence decryptor 221 must perform the inverse logical operation with the PN sequence encryptor 122 (for example, the encryptor is AND, the decryptor must be NAND); and the n-th bit of the first encryption sequence after restoration is an output obtained after the n-th bit of the second encryption sequence and the operand are subjected to XOR. The nth bit of the second encryption sequence received by the sender apparatus 10 is directly stacked to the first bit of the original key, and the last bit of the original key is deleted, thereby synchronously updating the key.
Expressed as a calculation formula, the first encrypted sequence is restored as follows:
wherein, b' [ n ]]For the second encryptionN-th position of the sequence, b [ n ]]Is the nth bit of the first encryption sequence, an[18]For bit 18, a of the key at the time of conversion of bit nn[23]Is the 23 rd bit of the key at the time of the n-th bit conversion. The calculation of the key update is as follows: a isn+1[1]＝b’[n]；an+1[x]＝an[x-1],x＝2-23；an+1[1]Is the value of the first bit of the updated key, an+1[x]The value of other bits of the updated key.
Through the above calculation process, the PN sequence decryptor 221 finally obtains the recovered first encrypted sequence. The obtained first encrypted sequence is recovered by the first data decryptor 222 into the original data packet PK2 and then transmitted to the data destination module 21 for storage in the data destination module 21.
In summary, the present invention can effectively avoid the doubt of password and data being cracked through a double encryption manner. In addition, the double encryption is executed through the PN sequence encryptor, the random characteristic of the encrypted data is effectively improved, the randomness of the encrypted data can be effectively increased, and the security of the data is further improved.
Although the present invention has been described in detail, it should be understood that the foregoing is only illustrative of the preferred embodiments of the present invention, and that various changes and modifications can be made herein without departing from the spirit and scope of the invention.
Claims (11)
1. A dual network encryption system comprising: a sending end device, including a data source module and a file encryption module, the file encryption module obtains at least one data packet from the data source module, converts the data packet into a first encryption sequence through a first data encryptor in sequence, and outputs the first encryption sequence after converting the data packet into a second encryption sequence through a PN sequence encryptor; and a receiving end device, including a data target module and a file decipher module, the receiving end device obtains at least one second enciphered sequence from the sending end device, the file decipher module restores the second enciphered sequence to the first enciphered sequence through PN sequence decipher device in sequence, and restores the first enciphered sequence to the data packet through first data decipher device and then transmits to the data target module.
2. The dual network encryption system of claim 1, wherein: the PN sequence encryptor includes a key and a linear feedback shift register, the linear feedback shift register performs logic operation on a plurality of bit taps of the key to finally obtain an operand, and performs logic operation on the operand and the first encryption sequence to obtain the second encryption sequence.
3. The dual network encryption system of claim 2, wherein: the number of bits of the tap is an even number.
4. The dual network encryption system of claim 1, wherein: the PN sequence decryptor includes a key and a linear feedback shift register, the linear feedback shift register performs logic operation on a plurality of bit taps of the key to finally obtain an operand, and performs logic operation on the operand and the second encryption sequence to restore and obtain the first encryption sequence.
5. The dual network encryption system of claim 4, wherein: the number of bits of the tap is an even number.
6. A sending terminal device comprises a data source module and a file encryption module, wherein the file encryption module obtains at least one data packet from the data source module, converts the data packet into a first encryption sequence through a first data encryptor in sequence, converts the first encryption sequence into a second encryption sequence through a PN sequence encryptor, and then outputs the second encryption sequence.
7. The sender apparatus according to claim 6, wherein: the PN sequence encryptor performs logic operation after tapping a plurality of bits in the bit string of the first encryption sequence, and adds the bit string of the first encryption sequence to obtain the second encryption sequence.
8. The sender apparatus according to claim 7, wherein: the number of bits of the tap is an even number.
9. A receiving end device comprises a data target module and a file decryption module, wherein the file decryption module obtains at least one second encryption sequence from a sending end device, sequentially restores the second encryption sequence into a first encryption sequence through a PN sequence decryptor, restores the first encryption sequence into a data packet through a first data decryptor and then transmits the data packet to the data target module.
10. The receiving-end apparatus according to claim 9, wherein: the PN sequence decryptor includes a key and a linear feedback shift register, the linear feedback shift register performs logic operation on a plurality of bit taps of the key to finally obtain an operand, and performs logic operation on the operand and the second encryption sequence to restore and obtain the first encryption sequence.
11. The receiving-end apparatus according to claim 10, wherein: the number of bits of the tap is an even number.
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| TW108104307 | 2019-02-01 | ||
| TW108104307A TWI705685B (en) | 2019-02-01 | 2019-02-01 | A double encryption and decryption system |
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| TWI728933B (en) * | 2020-10-30 | 2021-05-21 | 香港商吉達物聯科技股份有限公司 | Hybrid multistage algorithm encryption and decryption system, transmitting device thereof, and receiving device thereof |
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| US5365585A (en) * | 1993-08-30 | 1994-11-15 | Motorola, Inc. | Method and apparatus for encryption having a feedback register with selectable taps |
| US20090296928A1 (en) * | 2005-05-13 | 2009-12-03 | Ochanomizu University | Pseudorandom number generating system, encryption system, and decryption system |
| CN105119715A (en) * | 2015-07-03 | 2015-12-02 | 合肥工业大学 | FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm |
| CN105429748A (en) * | 2015-10-28 | 2016-03-23 | 济南知芯集成电路技术有限公司 | Data encryption method and system |
| CN106230580A (en) * | 2016-08-31 | 2016-12-14 | 福州福大海矽微电子有限公司 | A kind of changeable key multiple encryption method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7676733B2 (en) * | 2006-01-04 | 2010-03-09 | Intel Corporation | Techniques to perform forward error correction for an electrical backplane |
| US8675864B2 (en) * | 2010-09-14 | 2014-03-18 | CompuGroup Medical AG | Apparatus for encrypting data |
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- 2019-02-01 TW TW108104307A patent/TWI705685B/en active
- 2019-12-19 CN CN201911319209.3A patent/CN111556003A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5365585A (en) * | 1993-08-30 | 1994-11-15 | Motorola, Inc. | Method and apparatus for encryption having a feedback register with selectable taps |
| US20090296928A1 (en) * | 2005-05-13 | 2009-12-03 | Ochanomizu University | Pseudorandom number generating system, encryption system, and decryption system |
| CN105119715A (en) * | 2015-07-03 | 2015-12-02 | 合肥工业大学 | FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm |
| CN105429748A (en) * | 2015-10-28 | 2016-03-23 | 济南知芯集成电路技术有限公司 | Data encryption method and system |
| CN106230580A (en) * | 2016-08-31 | 2016-12-14 | 福州福大海矽微电子有限公司 | A kind of changeable key multiple encryption method |
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| TW202031009A (en) | 2020-08-16 |
| TWI705685B (en) | 2020-09-21 |
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