CN106230580A - A kind of changeable key multiple encryption method - Google Patents
A kind of changeable key multiple encryption method Download PDFInfo
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- CN106230580A CN106230580A CN201610768318.3A CN201610768318A CN106230580A CN 106230580 A CN106230580 A CN 106230580A CN 201610768318 A CN201610768318 A CN 201610768318A CN 106230580 A CN106230580 A CN 106230580A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
Abstract
The present invention relates to a kind of changeable key multiple encryption method, generate including key, clear data encryption and ciphertext data deciphering；Described key generates and generates 128 bit pseudo-random sequences as key 1 by 7 bit seeds, described 128 bit pseudo-random sequence backwards is exported, obtains key 2；The encryption of described clear data uses key 1, key 2 that 64 bits carry out triple TEA AES process in plain text and tries to achieve 64 bit ciphertexts；Described ciphertext data deciphering uses key 1, key 2 that 64 bit ciphertexts carry out the process of triple TEA decipherment algorithm and tries to achieve 64 bits in plain text.The present invention solves the problem that Most current AES is difficult to take into account in software and hardware expense and safety simultaneously.
Description
Technical field
The present invention relates to a kind of changeable key multiple encryption method.
Background technology
The calculating process of current most of AES is complex, and the Embedded Application limited for processing speed is come
Saying, the hardware logic generally requiring complexity carries out computing acceleration, thus result in the increase in cost and power consumption.The most traditional
AES is difficult to take into account in low software and hardware expense and high security simultaneously.
Summary of the invention
In view of this, it is an object of the invention to provide a kind of changeable key multiple encryption method, solve Most current and add
The problem that close algorithm is difficult to take into account on cost and safety simultaneously.
For achieving the above object, the present invention adopts the following technical scheme that a kind of changeable key multiple encryption method, its feature
It is: include that key generates, clear data encryption and ciphertext data deciphering；Described key generates and generates 128 by 7 bit seeds
Bit pseudo-random sequence, as key 1, by described 128 bit pseudo-random sequence backward outputs, obtains key 2；Described plaintext number
Use key 1, key 2 that 64 bits carry out triple TEA AES process in plain text according to encryption and try to achieve 64 bit ciphertexts；Described close
Literary composition data deciphering uses key 1, key 2 that 64 bit ciphertexts carry out the process of triple TEA decipherment algorithm and tries to achieve 64 bits in plain text.
Further, described key 1 and key 2 are generated by 7 rank m-sequence generating algorithms by 7 bit seeds, concrete steps
As follows:
Step S11: input 7 bit seeds, be loaded into 7 rank linear feedback shift register circuits as initial value
In, described 7 rank linear feedback shift register circuits are formed by 7 depositor concatenations, are defined as 1 to 7 by direction of displacement order
Rank depositor, often one clock cycle of input makees a shifting function；
Step S12: the clock signal generating a cycle is supplied to described 7 rank linear feedback shift register circuits；
Step S13: the value of depositor is shifted toward high-order direction, the output valve of the 3rd rank depositor and the 7th rank depositor is carried out
The value of XOR gained moves into the 1st rank depositor, using the 7th rank depositor i.e. output valve of afterbody depositor as circuit
The bit value of output；
Step S14: judge the accumulative clock periodicity generated, if less than 128, then returns step S12, if equal to 128
Perform step S15；
Step S15: 128 bit sequences arranged in order by the bit value of output are designated as key 1；Bit by key 1
Sequence backward exports, and obtains another 128 bit sequence, is designated as key 2.
Further, described triple TEA AES includes three below step:
Step S21: with key 1, in plain text 64 bits being done TEA encryption, result is designated as C1；
Step S22: with key 2, C1 being done TEA decryption processing, result is designated as C2；
Step S23: with key 1, C2 being done TEA encryption, result is required 64 bit ciphertexts.
Further, described triple TEA decipherment algorithm includes three below step:
Step S31: with key 1,64 bit ciphertexts being done TEA decryption processing, result is designated as P1；
Step S32: with key 2, P1 being done TEA encryption, result is designated as P2；
Step S33: with key 1, P2 being done TEA decryption processing, result is required 64 bits in plain text.
Further, the specifically comprising the following steps that of described TEA encryption
Step S41: data to be encrypted are divided into v (0) and v (l) two parts, each 32 bits, and define intermediate variable y=v (0),
z=v(l)；Key 1 or key 2 are divided into k (0), k (1), k (2) and k (3) four part, each 32 bits, and define intermediate variable a=
K (0), b=k (1), c=k (2), d=k (3)；Definition intermediate variable also composes initial value: Sum=0, Delta=0X9E3779B9, n=16；
Step S42: judge the value of n, if n > 0, performs step S43, otherwise performs step S44；
Step S43: the lower column operations of order execution assignment:
Sum=Sum+Delta,
Y=y+ (((z<<4)+a) ∧ (z+Sum) ∧ ((z>>5)+b)),
Z=z+ (((y<<4)+c) ∧ (y+Sum) ∧ ((y>>5)+d)),
N=n-1,
Turn after completing and jump to step S42；
Step S44: result of calculation is preserved: v (0)=y, v (1)=z, now ciphertext in v (0) and v (1) totally 64, TEA
Encryption terminates.
Further, the specifically comprising the following steps that of described TEA decryption processing
Step S51: data to be decrypted are divided into v (0) and v (l) two parts, each 32 bits, and define intermediate variable y=v (0),
z=v(l)；Key 1 or key 2 are divided into k (0), k (1), k (2) and k (3) four part, each 32 bits, and define intermediate variable a=
K (0), b=k (1), c=k (2), d=k (3)；Definition intermediate variable also composes initial value: Sum=0XC6EF3720, Delta=
0X9E3779B9, n=16；
Step S52: judge the value of n, if n > 0, performs step S53, otherwise performs step S54；
Step S53: the lower column operations of order execution assignment:
Z=z-(((y<<4)+c) ∧ (y+Sum) ∧ ((y>>5)+d)),
Y=y-(((z<<4)+a) ∧ (z+Sum) ∧ ((z>>5)+b)),
Sum=Sum-Delta,
N=n-1,
Turn after completing and jump to step S52；
Step S54: result of calculation is preserved: v (0)=y, v (1)=z, now in plain text in v (0) and v (1) totally 64, TEA
Decryption processing terminates.
Further, the transmission passing through described 7 bit seeds of described key 1 and key 2 realizes.
The present invention compared with prior art has the advantages that the key of the present invention passes through the seed that data volume is the least
Generating, facilitate transmission and the keeping of key, key is with pseudo-random characteristics simultaneously, adds and cracks difficulty；Encryption process makes
With multiple TEA computing, it is greatly improved encryption safe performance；Algorithm is simplified at a high speed, is very suitable for low-power consumption and low cost
Application demand.
Accompanying drawing explanation
Fig. 1 is the key schedule flow chart of the present invention.
Fig. 2 is triple TEA AES flow charts of the present invention.
Fig. 3 is triple TEA decipherment algorithm flow charts of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings and embodiment the present invention will be further described.
The present invention provides a kind of changeable key multiple encryption method, generates including key, clear data encryption and ciphertext number
According to deciphering；Described key generates and is generated 128 bit pseudo-random sequences as close by 7 bit seeds by 7 rank m-sequence generating algorithms
Key 1, by described 128 bit pseudo-random sequence backward outputs, obtains key 2；Refer to Fig. 1, specifically comprise the following steps that
Step S11: input 7 bit seeds, be loaded into 7 rank linear feedback shift register circuits as initial value
In, described 7 rank linear feedback shift register circuits are formed by 7 depositor concatenations, are defined as 1 to 7 by direction of displacement order
Rank depositor, often one clock cycle of input makees a shifting function；
Step S12: the clock signal generating a cycle is supplied to described 7 rank linear feedback shift register circuits；
Step S13: the value of depositor is shifted toward high-order direction, the output valve of the 3rd rank depositor and the 7th rank depositor is carried out
The value of XOR gained moves into the 1st rank depositor, the output valve of the i.e. afterbody depositor of the 7th rank depositor is exported as
The bit value of circuit output；
Step S14: judge the accumulative clock periodicity generated, if less than 128, then returns step S12, if equal to 128
Perform step S15；
Step S15: 128 bit sequences arranged in order by the bit value of output are designated as key 1；Bit by key 1
Sequence backward exports, and obtains another 128 bit sequence, is designated as key 2.
The encryption of described clear data uses key 1, key 2 that 64 bits carry out triple TEA AES process in plain text and asks
Obtain 64 bit ciphertexts；Refer to Fig. 2, specifically include three below step:
Step S21: with key 1, in plain text 64 bits being done TEA encryption, result is designated as C1；
Step S22: with key 2, C1 being done TEA decryption processing, result is designated as C2；
Step S23: with key 1, C2 being done TEA encryption, result is required 64 bit ciphertexts.
Described ciphertext data deciphering uses key 1, key 2 that 64 bit ciphertexts carry out the process of triple TEA decipherment algorithm and asks
Obtain 64 bits in plain text；Refer to Fig. 3, specifically include three below step:
Step S31: with key 1,64 bit ciphertexts being done TEA decryption processing, result is designated as P1；
Step S32: with key 2, P1 being done TEA encryption, result is designated as P2；
Step S33: with key 1, P2 being done TEA decryption processing, result is required 64 bits in plain text.
Further, the specifically comprising the following steps that of described TEA encryption
Step S41: data to be encrypted are divided into v (0) and v (l) two parts, each 32 bits, and define intermediate variable y=v (0),
z=v(l)；Key 1 or key 2 are divided into k (0), k (1), k (2) and k (3) four part, each 32 bits, and define intermediate variable a=
K (0), b=k (1), c=k (2), d=k (3)；Definition intermediate variable also composes initial value: Sum=0, Delta=0X9E3779B9, n=16；
Step S42: judge the value of n, if n > 0, performs step S43, otherwise performs step S44；
Step S43: the lower column operations of order execution assignment:
Sum=Sum+Delta,
Y=y+ (((z<<4)+a) ∧ (z+Sum) ∧ ((z>>5)+b)),
Z=z+ (((y<<4)+c) ∧ (y+Sum) ∧ ((y>>5)+d)),
N=n-1,
Turn after completing and jump to step S42；
Step S44: result of calculation is preserved: v (0)=y, v (1)=z, now ciphertext in v (0) and v (1) totally 64, TEA
Encryption terminates.
Further, the specifically comprising the following steps that of described TEA decryption processing
Step S51: data to be decrypted are divided into v (0) and v (l) two parts, each 32 bits, and define intermediate variable y=v (0),
z=v(l)；Key 1 or key 2 are divided into k (0), k (1), k (2) and k (3) four part, each 32 bits, and define intermediate variable a=
K (0), b=k (1), c=k (2), d=k (3)；Definition intermediate variable also composes initial value: Sum=0XC6EF3720, Delta=
0X9E3779B9, n=16；
Step S52: judge the value of n, if n > 0, performs step S53, otherwise performs step S54；
Step S53: the lower column operations of order execution assignment:
Z=z-(((y<<4)+c) ∧ (y+Sum) ∧ ((y>>5)+d)),
Y=y-(((z<<4)+a) ∧ (z+Sum) ∧ ((z>>5)+b)),
Sum=Sum-Delta,
N=n-1,
Turn after completing and jump to step S52；
Step S54: result of calculation is preserved: v (0)=y, v (1)=z, now in plain text in v (0) and v (1) totally 64, TEA
Decryption processing terminates.
Particularly, the variable n in above-mentioned TEA encryption and decrypting process represents the iterations that computing performs, this iteration time
Number can need to be set to 8 times, 16 times or 32 times according to safety.
Further, the transmission passing through described 7 bit seeds of described key 1 and key 2 realizes, and facilitates key
Transmission and keeping.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent with
Modify, all should belong to the covering scope of the present invention.
Claims (7)
1. a changeable key multiple encryption method, it is characterised in that: include that key generates, clear data encryption and ciphertext data
Deciphering；Described key generates and generates 128 bit pseudo-random sequences as key 1 by 7 bit seeds, will described 128 bits puppets
Random sequence backward exports, and obtains key 2；The encryption of described clear data uses key 1, key 2 that in plain text 64 bits are carried out three
Weight TEA AES processes and tries to achieve 64 bit ciphertexts；Described ciphertext data deciphering uses key 1, key 2 to enter 64 bit ciphertexts
The triple TEA decipherment algorithms of row process tries to achieve 64 bits in plain text.
Changeable key multiple encryption method the most according to claim 1, it is characterised in that: described key 1 and key 2 are by 7
Bit seed is generated by 7 rank m-sequence generating algorithms, specifically comprises the following steps that
Step S11: input 7 bit seeds, be loaded into 7 rank linear feedback shift register circuits as initial value
In, described 7 rank linear feedback shift register circuits are formed by 7 depositor concatenations, are defined as 1 to 7 by direction of displacement order
Rank depositor, often one clock cycle of input makees a shifting function；
Step S12: the clock signal generating a cycle is supplied to described 7 rank linear feedback shift register circuits；
Step S13: the value of depositor is shifted toward high-order direction, the output valve of the 3rd rank depositor and the 7th rank depositor is carried out
The value of XOR gained moves into the 1st rank depositor, using the 7th rank depositor i.e. output valve of afterbody depositor as circuit
The bit value of output；
Step S14: judge the accumulative clock periodicity generated, if less than 128, then returns step S12, if equal to 128
Perform step S15；
Step S15: 128 bit sequences arranged in order by the bit value of output are designated as key 1；Bit by key 1
Sequence backward exports, and obtains another 128 bit sequence, is designated as key 2.
Changeable key multiple encryption method the most according to claim 1, it is characterised in that: described triple TEA AESs
Including three below step:
Step S21: with key 1, in plain text 64 bits being done TEA encryption, result is designated as C1；
Step S22: with key 2, C1 being done TEA decryption processing, result is designated as C2；
Step S23: with key 1, C2 being done TEA encryption, result is required 64 bit ciphertexts.
Changeable key multiple encryption method the most according to claim 1, it is characterised in that: described triple TEA decipherment algorithms
Including three below step:
Step S31: with key 1,64 bit ciphertexts being done TEA decryption processing, result is designated as P1；
Step S32: with key 2, P1 being done TEA encryption, result is designated as P2；
Step S33: with key 1, P2 being done TEA decryption processing, result is required 64 bits in plain text.
5. according to the described changeable key multiple encryption method described in claim 3 or 4, it is characterised in that: at described TEA encryption
Specifically comprising the following steps that of reason
Step S41: data to be encrypted are divided into v (0) and v (l) two parts, each 32 bits, and define intermediate variable y=v (0),
z=v(l)；Key 1 or key 2 are divided into k (0), k (1), k (2) and k (3) four part, each 32 bits, and define intermediate variable a=
K (0), b=k (1), c=k (2), d=k (3)；Definition intermediate variable also composes initial value: Sum=0, Delta=0X9E3779B9, n=16；
Step S42: judge the value of n, if n > 0, performs step S43, otherwise performs step S44；
Step S43: the lower column operations of order execution assignment:
Sum=Sum+Delta,
Y=y+ (((z<<4)+a) ∧ (z+Sum) ∧ ((z>>5)+b)),
Z=z+ (((y<<4)+c) ∧ (y+Sum) ∧ ((y>>5)+d)),
N=n-1,
Turn after completing and jump to step S42；
Step S44: result of calculation is preserved: v (0)=y, v (1)=z, now ciphertext in v (0) and v (1) totally 64, TEA
Encryption terminates.
6. according to the described changeable key multiple encryption method described in claim 3 or 4, it is characterised in that: at described TEA deciphering
Specifically comprising the following steps that of reason
Step S51: data to be decrypted are divided into v (0) and v (l) two parts, each 32 bits, and define intermediate variable y=v (0),
z=v(l)；Key 1 or key 2 are divided into k (0), k (1), k (2) and k (3) four part, each 32 bits, and define intermediate variable a=
K (0), b=k (1), c=k (2), d=k (3)；Definition intermediate variable also composes initial value: Sum=0XC6EF3720, Delta=
0X9E3779B9, n=16；
Step S52: judge the value of n, if n > 0, performs step S53, otherwise performs step S54；
Step S53: the lower column operations of order execution assignment:
Z=z-(((y<<4)+c) ∧ (y+Sum) ∧ ((y>>5)+d)),
Y=y-(((z<<4)+a) ∧ (z+Sum) ∧ ((z>>5)+b)),
Sum=Sum-Delta,
N=n-1,
Turn after completing and jump to step S52；
Step S54: result of calculation is preserved: v (0)=y, v (1)=z, now in plain text in v (0) and v (1) totally 64, TEA
Decryption processing terminates.
Changeable key multiple encryption method the most according to claim 1, it is characterised in that: described key 1 and the biography of key 2
Pass and realized by the transmission of described 7 bit seeds.
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| CN111556003A (en) * | 2019-02-01 | 2020-08-18 | 益力半导体股份有限公司 | Dual network encryption system |
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Application publication date: 20161214 |