CN111554822A - Organic light emitting diode panel, preparation method thereof and display device - Google Patents
Organic light emitting diode panel, preparation method thereof and display device Download PDFInfo
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
- H10K50/18—Carrier blocking layers
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
- H10K50/17—Carrier injection layers
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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Abstract
An organic light emitting diode panel and a preparation method thereof, and a display device, wherein the organic light emitting diode panel comprises a plurality of pixel units arranged in a matrix, each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a hole injection layer and a pixel definition layer, the pixel definition layer comprises a plurality of opening regions and hole blocking regions arranged at intervals, an organic light emitting element is arranged in each opening region, and the hole blocking regions are used for blocking or increasing transmission paths of holes in the hole injection layers of adjacent sub-pixels. According to the method, the hole blocking region is used for blocking or increasing the transmission path of the hole in the hole injection layer of the adjacent sub-pixel, so that the hole in the hole injection layer can not be transversely transmitted or the path of the hole transverse transmission among the sub-pixels is increased, the low gray level crosstalk among different sub-pixels is reduced, the preparation process is simple, and the method has a good application prospect.
Description
Technical Field
The present disclosure relates to but not limited to the field of display technologies, and in particular, to an organic light emitting diode panel, a method for manufacturing the same, and a display device.
Background
An Organic Light Emitting Diode (OLED) is an active Light Emitting display device, and has the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed. With the continuous development of display technology, OLED technology is increasingly applied to flexible display devices.
Currently, in most OLED device structures, commonly used red, green, blue (RGB) three-color light emitting units share a Hole Injection Layer (HIL). As shown in fig. 1, in general, the voltage of the blue (B) pixel is the largest among the turn-on voltages of the RGB three-color light-emitting units, and the voltages of the green (G) pixel and the red (R) pixel are smaller. When a turn-on voltage is applied to one of the light emitting cells of one color having a large turn-on voltage, adjacent light emitting cells of the other color or colors having a low turn-on voltage generate low gray scale Crosstalk (Crosstalk) due to a large carrier mobility of the hole injection layer. For example, as shown in fig. 2, when a large voltage is applied across the blue organic light emitting material, most of the current Ib flows to the blue organic light emitting material, and the blue pixel is lit; but also a part of the currents Ig and Ir will flow to the green organic light emitting material and the red organic light emitting material, respectively, through the hole injection layer, lighting up the green and red pixels, resulting in low gray-scale crosstalk.
Disclosure of Invention
The embodiment of the application provides an organic light emitting diode panel, a preparation method thereof and a display device, which can reduce low gray scale crosstalk between different sub-pixels.
The embodiment of the application provides an organic light-emitting diode panel, which comprises a plurality of pixel units arranged in a matrix manner, wherein each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a hole injection layer and a pixel definition layer, each pixel definition layer comprises a plurality of opening regions and hole blocking regions which are arranged at intervals, an organic light-emitting element is arranged in each opening region, and the hole blocking regions are used for cutting off or increasing transmission paths of holes in the hole injection layers of the adjacent sub-pixels.
Optionally, the hole injection layer is arranged at intervals between adjacent sub-pixels; the hole blocking area comprises a blocking part in a protruding structure, and the opening area is formed between every two adjacent blocking parts.
Optionally, the hole blocking region includes two or more blocking portions in a protruding structure, and one of the opening regions is formed between two blocking portions adjacent to the organic light emitting element.
Optionally, in the hole blocking region, the interval between two adjacent blocking portions is greater than or equal to 3 micrometers, the width of each blocking portion is greater than or equal to 3 micrometers, and the width of the hole blocking region is greater than or equal to 14 micrometers.
Optionally, the hole injection layer is arranged at intervals between adjacent sub-pixels, or the hole injection layer is connected with each other to form an integral structure between adjacent sub-pixels.
Optionally, each sub-pixel further comprises a pixel structure layer, a flat layer, a first electrode, a hole transport layer, a light emitting layer, a second electrode and an encapsulation layer, wherein the flat layer is disposed on the pixel structure layer; the first electrode is arranged on the flat layer and is connected with the thin film transistor in the pixel structure layer through a through hole formed in the flat layer; the pixel defining layer is arranged on the flat layer and defines an opening area for exposing the first electrode; the hole injection layer is arranged on the first electrode; the hole transport layer is arranged on the hole injection layer; the light-emitting layer is arranged on the hole transport layer; the second electrode is arranged on the light-emitting layer; the encapsulation layer is arranged on the second electrode.
The embodiment of the application also provides a display device, which comprises the organic light emitting diode panel.
The embodiment of the application also provides a preparation method of the organic light-emitting diode panel, which comprises the following steps: forming a pixel defining layer in each sub-pixel, the pixel defining layer including a plurality of opening regions and hole blocking regions disposed at intervals; and forming a hole injection layer, wherein the hole blocking region is used for cutting off or increasing the transmission path of the holes in the hole injection layer of the adjacent sub-pixel.
Optionally, the hole blocking region includes a blocking portion in a protruding structure, and an opening region is formed between two adjacent blocking portions; the forming of the hole injection layer includes: and forming the hole injection layer in the opening region by using a fine metal mask.
Optionally, the hole blocking region includes a blocking portion in a protruding structure, and an opening region is formed between two adjacent blocking portions; the forming of the hole injection layer includes: coating photoresist on the substrate on which the pixel defining layer is formed, exposing the photoresist, forming an unexposed region in the hole blocking region, forming a complete exposure region in the opening region, and developing to remove the photoresist in the complete exposure region; and forming a hole injection layer on the substrate with the photoresist pattern, and stripping and removing the photoresist and the hole injection layer in the hole blocking area.
Optionally, the hole blocking region includes two or more blocking portions in a protruding structure, and one of the opening regions is formed between two blocking portions adjacent to the organic light emitting element.
The embodiment of the application provides an OLED panel, a preparation method thereof and a display device, wherein a hole blocking area is used for blocking or increasing a transmission path of a hole in a hole injection layer of an adjacent sub-pixel, so that the hole in the hole injection layer can not be transversely transmitted or the path of transverse hole transmission among the sub-pixels is increased, low-gray-scale crosstalk among different sub-pixels is reduced, the preparation process is simple, the production efficiency is high, the advantages of low production cost, high yield and the like are achieved, and the OLED panel has a good application prospect.
Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application. Additional features and advantages of the application will be set forth in the description of the embodiments that follow, and in part will be apparent from the description, or may be learned by practice of the application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the claimed subject matter and are incorporated in and constitute a part of this specification, illustrate embodiments of the subject matter and together with the description serve to explain the principles of the subject matter and not to limit the subject matter. The shapes and sizes of the various elements in the drawings are not to be considered as true proportions, but rather are merely intended to illustrate the context of the application.
FIG. 1 is a schematic voltage-current curve of an OLED device in some techniques;
FIG. 2 is a schematic diagram of the cross talk between sub-pixels of an OLED device in some techniques;
fig. 3 is a schematic structural diagram of an OLED panel according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a pixel structure layer pattern according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating a planarized layer pattern formed according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram illustrating a first electrode pattern formed according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram illustrating a pixel defining layer pattern formed according to an embodiment of the present disclosure;
FIG. 8 is a schematic view of a hole injection layer patterned according to an embodiment of the present disclosure;
FIG. 8(a) is a schematic diagram of a structure for exposing a photoresist during formation of a hole injection layer;
FIG. 8(b) is a schematic diagram showing the structure of a photoresist after exposure during the formation of a hole injection layer;
FIG. 8(c) is a schematic structural diagram of a hole injection layer formed by evaporation during the formation of the hole injection layer;
FIG. 8(d) is a schematic structural diagram of a hole injection layer with a hole blocking region stripped away during the formation of the hole injection layer;
fig. 9 is a schematic structural view after a light-emitting functional layer pattern is formed according to an embodiment of the present application;
FIG. 10 is a schematic structural diagram of a second electrode pattern formed according to an embodiment of the present disclosure;
FIG. 11 is a schematic structural diagram of another OLED panel according to an embodiment of the present disclosure;
FIG. 12 is a schematic view of another embodiment of the present disclosure after forming a pixel defining layer pattern;
FIG. 13 is a schematic view of another embodiment of the present disclosure after patterning a hole injection layer;
fig. 14 is a schematic flowchart of a method for manufacturing an OLED panel according to an embodiment of the present application.
Description of reference numerals:
10-a substrate; 20-pixel structure layer; 21-a thin film transistor;
30-a flat layer; 40-a first electrode; 50-pixel definition layer;
60-a hole injection layer; 70-a hole transport layer; 80-a light-emitting layer;
90-electron transport layer; 100 — a second electrode; 110-an encapsulation layer;
51-photoresist; d 1-d 3-width; ib, Ig and Ir-current.
Detailed Description
The following detailed description of embodiments of the present application will be described in detail with reference to the accompanying drawings and examples. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The embodiment of the application provides an OLED panel, a preparation method thereof and a display device, and the micro-cavity structure of the large-size OLED panel is constructed on the premise of not using an evaporation process or an ink-jet printing process of a fine metal mask plate.
The embodiment of the application provides an OLED panel, which comprises a plurality of pixel units arranged in a matrix, wherein each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a hole injection layer and a pixel definition layer, each pixel definition layer comprises a plurality of opening regions and hole blocking regions which are arranged at intervals, an organic light-emitting element is arranged in each opening region, and the hole blocking regions are used for blocking or increasing transmission paths of holes in the hole injection layers of the adjacent sub-pixels.
The OLED panel provided by the embodiment of the application, through setting up the adjusting layer, the transmission path of the hole in the hole injection layer of the adjacent sub-pixel is cut off or increased through the hole blocking area, so that the hole can not be transversely transmitted in the hole injection layer or the path of the hole transverse transmission between the sub-pixels is increased, the low-gray-scale crosstalk between different sub-pixels is reduced, the preparation process is simple, the production efficiency is high, the advantages of low production cost, high yield and the like are achieved, and the good application prospect is achieved.
The technical solution of the present application will be described in detail by specific examples.
Fig. 3 is a schematic structural diagram of an OLED panel according to a first embodiment of the present application, where the OLED panel of the present embodiment is a top emission structure. The main body structure of the OLED panel of this embodiment includes a plurality of pixel units arranged in a matrix, each pixel unit includes 3 sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, and the hole injection layer is disposed at intervals between adjacent sub-pixels, so that the holes cannot be transversely transmitted in the hole injection layer, and low gray level crosstalk between different sub-pixels is reduced. As shown in fig. 3, the OLED panel of the present embodiment includes:
a substrate 10;
a pixel structure layer 20 disposed on the substrate 10, the pixel structure layer 20 in each sub-pixel including a thin film transistor 21;
a planarization layer 30 disposed on the pixel structure layer 20;
a light emitting structure layer disposed on the planarization layer 30, the light emitting structure layer in each sub-pixel including a first electrode 40, a pixel defining layer 50, a hole injection layer 60, a light emitting function layer, a second electrode 100, and an encapsulation layer 110, wherein,
the first electrode 40 is arranged on the flat layer 30 and is connected with the drain electrode of the thin film transistor through a through hole formed in the flat layer 30;
a pixel defining layer 50 disposed on the planarization layer 30, defining an opening region exposing the first electrode 40;
a hole injection layer 60 disposed on the first electrode 40 and spaced between the different sub-pixels, the hole injection layer 60 being disposed in an opening region defined by the pixel defining layer 50 within one sub-pixel;
a light emitting functional layer disposed on the hole injection layer 60;
a second electrode 100 disposed on the light emitting function layer;
and an encapsulation layer 110 disposed on the second electrode 100 and covering the entire substrate 10.
The technical solution of this embodiment is further illustrated by the preparation process of the OLED panel of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and the "photolithography process" in this embodiment includes processes such as film coating, mask exposure, and development, and is a mature preparation process in the related art. The deposition may be performed by a known process such as sputtering, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
(1) First, a pixel structure layer 20 pattern is prepared on a substrate 10, as shown in fig. 4. The pixel structure layer 20 includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines are vertically crossed to define a plurality of pixel units arranged in a matrix, each pixel unit includes at least 3 sub-pixels, and each sub-pixel includes a Thin Film Transistor (TFT) 21. In this embodiment, one pixel unit includes 3 sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, the scheme of the present embodiment is also applicable to the case where one pixel unit includes 4 sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W). In this embodiment, the structure and the manufacturing process of the pixel structure layer 20 are the same as those of the conventional structure and manufacturing process. For example, the preparation process may include: the method comprises the steps of cleaning a substrate, preparing an active layer on the substrate through a composition process, forming a first insulating layer covering the active layer, forming a grid line and a grid electrode on the first insulating layer, forming a second insulating layer covering the grid line and the grid electrode, and forming a data line, a source electrode and a drain electrode on the second insulating layer. The thin film transistor may have a bottom gate structure or a top gate structure, and may be an amorphous silicon (a-Si) thin film transistor, or may be a Low Temperature Polysilicon (LTPS) thin film transistor or an Oxide (Oxide) thin film transistor, which is not limited herein. In practice, the substrate may be made of a high-light-transmitting material such as glass, quartz, a polyolefin resin, a polyethylene naphthalate resin, a polyimide resin, a poly (terephthalic acid) plastic, a phenol resin, or a surface-treated polymer film.
(2) A first planarization film is coated on the flexible substrate on which the aforementioned pattern is formed, a Planarization (PLN) layer 30 covering the entire flexible substrate 10 is formed, a via hole is formed on the first planarization layer 30 through a patterning process, the planarization layer 30 in the via hole is etched away, and the surface of the drain electrode of the thin film transistor 21 is exposed, as shown in fig. 5.
(3) A first electrode 40 pattern is formed on the substrate on which the aforementioned pattern is formed. Forming the first electrode 40 pattern includes: depositing a first metal film on the substrate on which the patterns are formed, coating a layer of photoresist on the first metal film, exposing the photoresist by using a single-tone mask, forming a non-exposure region at the position of the first electrode, forming a complete exposure region at other positions, developing to remove the photoresist in the complete exposure region, etching away the first metal film in the complete exposure region, stripping the photoresist to form a first electrode 40 pattern, wherein the first electrode 40 of each sub-pixel is connected with the drain electrode of the thin film transistor 21 in the sub-pixel, as shown in fig. 6. Since the OLED panel of this embodiment has a top emission structure, the first electrode is a reflective electrode, and a metal with high reflectivity, such as Ag, Au, Pd, Pt, or an alloy thereof, or a composite layer thereof, may be used. In practical implementation, a composite layer structure of an Indium Tin Oxide (ITO) layer and a metal reflecting layer can be adopted, and the ITO film has good conductivity, high reflectivity and good form stability.
(4) A pixel defining layer 50 pattern is formed on the substrate on which the aforementioned pattern is formed. Forming the pixel defining layer 50 pattern includes: a pixel defining film is coated on the substrate on which the pattern is formed, the pixel defining film is exposed and developed by using a single-tone mask to form a pixel defining layer 50 pattern, the pixel defining layer 50 includes a plurality of opening regions and hole blocking regions which are arranged at intervals, each hole blocking region includes a blocking portion which is in a convex structure, and an opening region is formed between every two adjacent blocking portions, as shown in fig. 7. The pixel defining layer 50 serves to define a light emitting region at each sub-pixel, the light emitting region exposing the first electrode 40. In this embodiment, the Pixel definition Layer (Pixel Define Layer) may be made of polyimide, acryl, or polyethylene terephthalate.
(5) A pattern of hole injection layers 60 is formed on the substrate on which the aforementioned pattern is formed, and the hole injection layer 60 of each sub-pixel is connected to the first electrode 40 of the sub-pixel, as shown in fig. 8. In the embodiment of the present application, the hole injection layer 60 may be patterned by the following two methods:
(a) the hole injection layer 60 of the pixel opening region is patterned on the substrate on which the foregoing pattern is formed using a Fine Metal Mask (FMM).
For example, a fine mask is aligned with the opening region, and then a hole injection layer is formed on the substrate on which the pixel defining layer is formed by using a process such as evaporation so that the hole injection layer 60 is spaced between adjacent sub-pixels.
(b) The hole injection layer 60 of the pixel opening region is patterned on the substrate on which the aforementioned pattern is formed using a photoresist patterning method.
For example, a layer of photoresist 51 is coated on the substrate on which the pattern is formed, the photoresist 51 is exposed by using a single-tone mask, an unexposed region is formed in the hole blocking region, a fully exposed region is formed in the opening region, and the photoresist 51 in the fully exposed region is removed by development; the hole injection layer 60 is evaporated on the substrate on which the photoresist 51 pattern is formed, the photoresist 51 is stripped and removed using a stripping solution, the hole injection layer 60 in the hole blocking region is stripped and removed at the same time as the photoresist 51 is removed, and only the hole injection layer 60 in the opening region is left, i.e., the patterned hole injection layer 60 pattern is formed, as shown in fig. 8(a) to 8 (d).
(6) And forming a luminous functional layer pattern on the substrate on which the pattern is formed. Forming the light emitting function layer pattern includes: a Hole Transport Layer (HTL)70 pattern is formed on the substrate on which the hole injection layer 60 pattern is formed, an emission layer (EML)80 pattern is formed on the hole transport layer 70 of each sub-pixel, and an Electron Transport Layer (ETL)90 is formed on the substrate on which the emission layer 80 pattern is formed, as shown in fig. 9. In the present embodiment, the light emitting function layer 70 mainly includes a hole transport layer 70, a light emitting layer 80, and an electron transport layer 90. Further, in order to improve efficiency of injecting electrons and holes into the light emitting layer, the light emitting function layer 70 may further include an Electron Injection Layer (EIL) (not shown in the drawings) disposed between the second electrode and the electron transport layer. Among them, a Hole Transport Layer (HTL)70, an emission layer (EML)80, an Electron Transport Layer (ETL)90, and an Electron Injection Layer (EIL) are sequentially disposed on the hole injection layer 60.
(7) A second electrode 100 pattern is formed on the substrate on which the aforementioned pattern is formed. Forming the second electrode 100 pattern includes: a second metal film is deposited on the substrate on which the aforementioned pattern is formed, and the second metal film is patterned through a patterning process to form a second electrode 100 pattern, as shown in fig. 10. Since the OLED panel of this embodiment has a top emission structure, the second electrode may be a transmissive electrode or a transflective electrode, the transmissive electrode may be made of one of metal materials such as Mg, Ag, Al, Cu, Li, or an alloy of the foregoing metals, and the transflective electrode may be made of a metal made of a transflective material.
(8) The pattern of the encapsulation layer 110 is formed on the substrate on which the pattern is formed. Patterning the encapsulation layer 110 includes: a film layer of an organic material, such as tetrafluoroethylene, is coated on the substrate on which the aforementioned pattern is formed, and the film layer covers the entire substrate to form an encapsulation layer 110 for protecting the OLED panel, thereby completing the OLED panel structure of this embodiment, as shown in fig. 3.
According to the OLED panel provided by the embodiment, the hole injection layers are arranged between the adjacent sub-pixels at intervals, and the hole injection layers are only formed in the opening regions, so that holes cannot be transversely transmitted in the hole injection layers, the problem of low gray scale crosstalk between different sub-pixels is solved, the preparation process is simple, the production efficiency is high, and the OLED panel has the advantages of low production cost, high yield and the like, and has a good application prospect.
Although the OLED panel of the present embodiment is illustrated in a top-emission structure, the solution of the present embodiment is also applicable to a bottom-emission structure or a dual-emission structure, and is also applicable to a large-sized or small-sized OLED panel.
Fig. 11 is a schematic structural diagram of an OLED panel according to a second embodiment of the present application, where the OLED panel of this embodiment has a top emission structure. The main structure of the OLED panel of this embodiment includes a plurality of pixel units arranged in a matrix, each pixel unit includes 3 sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, and two or more blocking portions with a protruding structure are disposed in a hole blocking region between adjacent organic light emitting elements, so that a path for lateral hole transmission between the sub-pixels is increased, and the occurrence probability of low gray-scale crosstalk is reduced. As shown in fig. 11, the OLED panel of the present embodiment includes:
a substrate 10;
a pixel structure layer 20 disposed on the substrate 10, the pixel structure layer 20 in each sub-pixel including a thin film transistor 21;
a planarization layer 30 disposed on the pixel structure layer 20;
a light emitting structure layer disposed on the planarization layer 30, the light emitting structure layer in each sub-pixel including a first electrode 40, a pixel defining layer 50, a hole injection layer 60, a light emitting function layer, a second electrode 100, and an encapsulation layer 110, wherein,
the first electrode 40 is arranged on the flat layer 30 and is connected with the drain electrode of the thin film transistor through a through hole formed in the flat layer 30;
a pixel defining layer 50 disposed on the planarization layer 30 and defining a light emitting region exposing the first electrode 40;
a hole injection layer 60 disposed on the first electrode 40 and the pixel defining layer 50;
a light emitting functional layer disposed on the hole injection layer 60;
a second electrode 80 disposed on the light emitting function layer;
and an encapsulation layer 90 disposed on the second electrode 80 and covering the entire substrate 10.
The technical solution of this embodiment is further illustrated by the preparation process of the OLED panel of this embodiment. The "patterning process" in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and the "photolithography process" in this embodiment includes processes such as film coating, mask exposure, and development, and is a mature preparation process in the related art. The deposition may be performed by a known process such as sputtering, chemical vapor deposition, etc., the coating may be performed by a known coating process, and the etching may be performed by a known method, which is not particularly limited herein.
(1) First, a pixel structure layer 20 pattern is prepared on a substrate 10, as shown in fig. 4. The pixel structure layer 20 includes a plurality of gate lines and a plurality of data lines, the plurality of gate lines and the plurality of data lines are vertically crossed to define a plurality of pixel units arranged in a matrix, each pixel unit includes at least 3 sub-pixels, and each sub-pixel includes a Thin Film Transistor (TFT) 21. In this embodiment, one pixel unit includes 3 sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, the scheme of the present embodiment is also applicable to the case where one pixel unit includes 4 sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W). In this embodiment, the structure and the manufacturing process of the pixel structure layer 20 are the same as those of the conventional structure and manufacturing process. For example, the preparation process may include: the method comprises the steps of cleaning a substrate, preparing an active layer on the substrate through a composition process, forming a first insulating layer covering the active layer, forming a grid line and a grid electrode on the first insulating layer, forming a second insulating layer covering the grid line and the grid electrode, and forming a data line, a source electrode and a drain electrode on the second insulating layer. The thin film transistor may have a bottom gate structure or a top gate structure, and may be an amorphous silicon (a-Si) thin film transistor, or may be a Low Temperature Polysilicon (LTPS) thin film transistor or an Oxide (Oxide) thin film transistor, which is not limited herein. In practice, the substrate may be made of a high-light-transmitting material such as glass, quartz, a polyolefin resin, a polyethylene naphthalate resin, a polyimide resin, a poly (terephthalic acid) plastic, a phenol resin, or a surface-treated polymer film.
(2) A first planarization film is coated on the flexible substrate on which the aforementioned pattern is formed, a Planarization (PLN) layer 30 covering the entire flexible substrate 10 is formed, a via hole is formed on the planarization layer 30 through a patterning process, the planarization layer 30 in the via hole is etched away, and the surface of the drain electrode of the thin film transistor 21 is exposed, as shown in fig. 5.
(3) A first electrode 40 pattern is formed on the substrate on which the aforementioned pattern is formed. Forming the first electrode 40 pattern includes: depositing a first metal film on the substrate on which the patterns are formed, coating a layer of photoresist on the first metal film, exposing the photoresist by using a single-tone mask, forming a non-exposure region at the position of the first electrode, forming a complete exposure region at other positions, developing to remove the photoresist in the complete exposure region, etching away the first metal film in the complete exposure region, stripping the photoresist to form a first electrode 40 pattern, wherein the first electrode 40 of each sub-pixel is connected with the drain electrode of the thin film transistor 21 in the sub-pixel, as shown in fig. 6. Since the OLED panel of this embodiment has a top emission structure, the first electrode is a reflective electrode, and a metal with high reflectivity, such as Ag, Au, Pd, Pt, or an alloy thereof, or a composite layer thereof, may be used. In practical implementation, a composite layer structure of an Indium Tin Oxide (ITO) layer and a metal reflecting layer can be adopted, and the ITO film has good conductivity, high reflectivity and good form stability.
(4) A pixel defining layer 50 pattern is formed on the substrate on which the aforementioned pattern is formed. Forming the pixel defining layer 50 pattern includes: a pixel defining film is coated on the substrate on which the pattern is formed, and the pixel defining film is exposed and developed by using a single-tone mask to form a pattern of a pixel defining layer 50, as shown in fig. 12. The pixel defining layer 50 serves to define an opening region at each sub-pixel, the opening region exposing the first electrode 40. In this embodiment, the Pixel definition Layer (Pixel Define Layer) may be made of polyimide, acryl, or polyethylene terephthalate.
The pixel definition layer comprises a plurality of opening regions and hole blocking regions which are arranged at intervals, the hole blocking regions comprise two or more than two blocking parts which are in a protruding structure, and an opening region is formed between the two blocking parts adjacent to the organic light-emitting element.
As shown in fig. 12, in one hole blocking region, the interval d1 between adjacent two barriers is greater than or equal to 3 micrometers, the width d2 of each barrier is greater than or equal to 3 micrometers, and the width d3 of one hole blocking region is greater than or equal to 14 micrometers.
Illustratively, a hole blocking region includes two raised barriers having a spacing d1 equal to 6 microns, a single barrier width d2 equal to 4 microns, and a total width of the hole blocking region (i.e., the total width of the two barriers) d3 equal to 14 microns.
(5) A pattern of hole injection layers 60 is formed on the substrate on which the pattern is formed, and the hole injection layer 60 of each sub-pixel is connected to the first electrode 40 of the sub-pixel, as shown in fig. 13, in the present embodiment, the hole injection layers 60 are connected to each other between adjacent sub-pixels in an integrated structure. In other embodiments, the hole injection layer 60 may be disposed at intervals between adjacent sub-pixels.
(6) And sequentially forming a light-emitting functional layer, a second electrode and a packaging layer pattern on the substrate on which the patterns are formed. Forming the light emitting function layer pattern includes: a Hole Transport Layer (HTL)70 is formed on the substrate on which the hole injection layer 60 is patterned, an emission layer (EML)80 is formed on the hole transport layer 70 of each sub-pixel, and an Electron Transport Layer (ETL)90 is formed on the substrate on which the emission layer 80 is patterned, as shown in fig. 11. In this embodiment, the light emitting function layer mainly includes a hole transport layer 70, a light emitting layer 80, and an electron transport layer 90. Further, in order to improve efficiency of injecting electrons and holes into the light emitting layer, the light emitting function layer may further include an Electron Injection Layer (EIL) (not shown in the drawings) disposed between the second electrode and the electron transport layer. Among them, a Hole Transport Layer (HTL)70, an emission layer (EML)80, an Electron Transport Layer (ETL)90, and an Electron Injection Layer (EIL) are sequentially disposed on the hole injection layer 60.
Forming the second electrode 100 pattern includes: a second metal film is deposited on the substrate on which the aforementioned pattern is formed, and the second metal film is patterned through a patterning process to form a second electrode 100 pattern, as shown in fig. 11. Since the OLED panel of this embodiment has a top emission structure, the second electrode may be a transmissive electrode or a transflective electrode, the transmissive electrode may be made of one of metal materials such as Mg, Ag, Al, Cu, Li, or an alloy of the foregoing metals, and the transflective electrode may be made of a metal made of a transflective material.
Patterning the encapsulation layer 110 includes: a film layer of an organic material, such as tetrafluoroethylene, is coated on the substrate on which the aforementioned pattern is formed, and the film layer covers the entire substrate to form an encapsulation layer 110 for protecting the OLED panel, thereby completing the OLED panel structure of this embodiment, as shown in fig. 11.
It can be seen from the above preparation process that the OLED panel provided in this embodiment has two or more blocking portions with protruding structures disposed in the hole blocking region between the adjacent organic light emitting elements, so that the paths for lateral hole transmission in the hole injection layer between the sub-pixels are increased, the occurrence probability of low gray scale crosstalk between different sub-pixels is reduced, the preparation process is simple, the production efficiency is high, and the OLED panel has the advantages of low production cost, high yield and the like, and has a good application prospect.
Although the OLED panel of the present embodiment is illustrated in a top-emission structure, the solution of the present embodiment is also applicable to a bottom-emission structure or a dual-emission structure, and is also applicable to a large-sized or small-sized OLED panel.
The embodiment of the application also provides a preparation method of the OLED panel. As shown in fig. 14, the method for manufacturing an OLED panel according to the embodiment of the present application includes:
s1, forming a pixel defining layer in each sub-pixel, the pixel defining layer including a plurality of spaced opening regions and hole blocking regions;
and S2, forming a hole injection layer, wherein the hole blocking region is used for cutting off or increasing the transmission path of the holes in the hole injection layer of the adjacent sub-pixel.
In an exemplary embodiment, the hole blocking region includes a protruding blocking portion, and an opening region is formed between two adjacent blocking portions.
In an exemplary embodiment, step S2 includes: a hole injection layer is formed in the opening region using a fine metal mask.
In another exemplary embodiment, step S2 includes:
s21, coating photoresist on the substrate on which the pixel defining layer is formed, exposing the photoresist, forming an unexposed region in the hole blocking region, forming a complete exposure region in the opening region, and developing to remove the photoresist in the complete exposure region;
and S22, forming a hole injection layer on the substrate with the photoresist pattern, and stripping and removing the photoresist and the hole injection layer in the hole blocking area.
In another exemplary embodiment, the hole blocking region includes two or more blocking portions in a protruding structure, and an opening region is formed between two blocking portions adjacent to the organic light emitting element.
In an exemplary embodiment, in one hole blocking region, a space between two adjacent blocking portions is greater than or equal to 3 micrometers, a width of each blocking portion is greater than or equal to 3 micrometers, and a width of one hole blocking region is greater than or equal to 14 micrometers.
In an exemplary embodiment, the hole injection layer may be disposed at intervals between the adjacent sub-pixels, or the hole injection layer may be connected to each other in an integrated structure between the adjacent sub-pixels.
In this embodiment, the structures, materials, related parameters, and detailed preparation processes of the pixel defining layer and the hole injection layer have been described in detail in the foregoing embodiments, and are not described herein again.
The embodiment provides a preparation method of an OLED panel, which cuts off or increases a hole transmission path in a hole injection layer of an adjacent sub-pixel through a hole blocking region, so that the hole cannot be transversely transmitted in the hole injection layer or the path of transverse hole transmission between sub-pixels is increased, low gray scale crosstalk between different sub-pixels is reduced, the preparation process is simple, the production efficiency is high, and the preparation method has the advantages of low production cost, high yield and the like, and has a good application prospect.
The embodiment of the application also provides an OLED display device which comprises the OLED panel of the previous embodiment. The OLED display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In the description of the embodiments of the present application, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and therefore, should not be construed as limiting the present application.
In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless explicitly stated or limited otherwise; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Claims (11)
1. An organic light emitting diode panel comprises a plurality of pixel units arranged in a matrix, each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a hole injection layer and a pixel definition layer, each pixel definition layer comprises a plurality of opening regions and hole blocking regions which are arranged at intervals, an organic light emitting element is arranged in each opening region, and each hole blocking region is used for cutting off or increasing the transmission path of holes in the hole injection layer of the adjacent sub-pixel.
2. The panel according to claim 1, wherein the hole injection layer is spaced between adjacent sub-pixels;
the hole blocking area comprises a blocking part in a protruding structure, and the opening area is formed between every two adjacent blocking parts.
3. The panel according to claim 1, wherein the hole blocking region comprises two or more blocking portions in a protruding structure, and one of the opening regions is formed between two of the blocking portions adjacent to the organic light emitting element.
4. The panel according to claim 3, wherein in the hole blocking region, a space between adjacent two of the blocking portions is greater than or equal to 3 micrometers, a width of each of the blocking portions is greater than or equal to 3 micrometers, and a width of the hole blocking region is greater than or equal to 14 micrometers.
5. The panel according to claim 3, wherein the hole injection layer is spaced between adjacent sub-pixels, or the hole injection layer is connected to each other in an integrated structure between adjacent sub-pixels.
6. The panel of claim 1, wherein each sub-pixel further comprises a pixel structure layer, a planarization layer, a first electrode, a hole transport layer, a light emitting layer, a second electrode, and an encapsulation layer, wherein,
the flat layer is arranged on the pixel structure layer;
the first electrode is arranged on the flat layer and is connected with the thin film transistor in the pixel structure layer through a through hole formed in the flat layer;
the pixel defining layer is arranged on the flat layer and defines an opening area for exposing the first electrode;
the hole injection layer is arranged on the first electrode;
the hole transport layer is arranged on the hole injection layer;
the light-emitting layer is arranged on the hole transport layer;
the second electrode is arranged on the light-emitting layer;
the encapsulation layer is arranged on the second electrode.
7. A display device comprising the organic light emitting diode panel according to any one of claims 1 to 6.
8. A method for manufacturing an organic light emitting diode panel is characterized by comprising the following steps:
forming a pixel defining layer in each sub-pixel, the pixel defining layer including a plurality of opening regions and hole blocking regions disposed at intervals;
and forming a hole injection layer, wherein the hole blocking region is used for cutting off or increasing the transmission path of the holes in the hole injection layer of the adjacent sub-pixel.
9. The method for preparing the porous ceramic material according to claim 8, wherein the hole blocking region comprises a protruding blocking portion, and an opening region is formed between two adjacent blocking portions;
the forming of the hole injection layer includes: and forming the hole injection layer in the opening region by using a fine metal mask.
10. The method for preparing the porous ceramic material according to claim 8, wherein the hole blocking region comprises a protruding blocking portion, and an opening region is formed between two adjacent blocking portions;
the forming of the hole injection layer includes:
coating photoresist on the substrate on which the pixel defining layer is formed, exposing the photoresist, forming an unexposed region in the hole blocking region, forming a complete exposure region in the opening region, and developing to remove the photoresist in the complete exposure region;
and forming a hole injection layer on the substrate with the photoresist pattern, and stripping and removing the photoresist and the hole injection layer in the hole blocking area.
11. The method according to claim 8, wherein the hole blocking region comprises two or more protruding blocking portions, and one of the opening regions is formed between two of the blocking portions adjacent to the organic light emitting device.
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