CN111554735A - Method for manufacturing field plate of semiconductor device - Google Patents
Method for manufacturing field plate of semiconductor device Download PDFInfo
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- CN111554735A CN111554735A CN202010396763.8A CN202010396763A CN111554735A CN 111554735 A CN111554735 A CN 111554735A CN 202010396763 A CN202010396763 A CN 202010396763A CN 111554735 A CN111554735 A CN 111554735A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 238000002161 passivation Methods 0.000 claims description 27
- 230000004888 barrier function Effects 0.000 claims description 20
- 238000001312 dry etching Methods 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 12
- 238000007740 vapor deposition Methods 0.000 claims description 11
- 238000001039 wet etching Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 238000001883 metal evaporation Methods 0.000 claims description 7
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000002207 thermal evaporation Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 8
- 238000009616 inductively coupled plasma Methods 0.000 description 7
- 230000005669 field effect Effects 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
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- 238000005530 etching Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 241001391944 Commicarpus scandens Species 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
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- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 238000005137 deposition process Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the invention discloses a method for manufacturing a field plate of a semiconductor device, which comprises the following steps: forming a first dielectric layer on the surface of the semiconductor epitaxial wafer; forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer; forming a second dielectric layer on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole; forming a second positioning hole exposing the surface of the semiconductor epitaxial wafer on the second dielectric layer in the first positioning hole; and forming a field plate structure on the surface of the second dielectric layer and at the first positioning hole and the second positioning hole. According to the embodiment of the invention, the first positioning hole is formed first, and then the second dielectric layer and the second positioning hole are formed, so that the finally formed field plate structure has the edge of an arc-shaped structure, the electric field at the edge of the field plate is not easy to be locally concentrated, a semiconductor device is not easy to be broken down, and the reliability of the semiconductor device is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a field plate of a semiconductor device.
Background
A conventional semiconductor device having three ports usually uses one port as a control terminal to control the on and off of the other two ports, such as a transistor, a field effect transistor, etc. In high power and high frequency device applications, one of the two conducting ports is often biased at a higher voltage, and in order to avoid breakdown of the device due to a higher electric field under the high voltage, a field plate structure of the electrode is often used to reduce the extreme value of the local electric field at the edge of the electrode.
Taking a field effect transistor as an example, in the fabrication of a gate field plate, especially a gate multi-level field plate, it is usually necessary to first grow a multi-layer dielectric layer on the surface of a semiconductor epitaxial wafer, then remove the dielectric layer at the gate window portion by a dry etching or wet etching method, and finally cover a metal field plate on the gate window. The manufacturing method is difficult to accurately control the thickness of the residual dielectric layer in etching or corrosion, and the residual dielectric layer is possibly etched excessively and invaded into the next dielectric layer, so that the distance between the metal field plate and the surface barrier layer of the semiconductor epitaxial wafer is difficult to accurately control, and the electric field distribution is not uniform. In addition, the etching of the method enables the dielectric layer of the gate window part to have sharp-edged corners, so that the corners of the formed metal field plate also have sharp edges, the sharp edges can cause the local electric field to be greatly increased, and the local over-high electric field can cause the semiconductor device to be broken down, so that the performance of the semiconductor device is limited, and the reliability is poor.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for manufacturing a field plate of a semiconductor device, so as to accurately control a gap between the field plate and a barrier layer of the semiconductor device and improve reliability of the semiconductor device.
The embodiment of the invention provides a manufacturing method of a field plate of a semiconductor device, which comprises the following steps:
forming a first dielectric layer on the surface of the semiconductor epitaxial wafer;
forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer;
forming a second dielectric layer on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole;
forming a second positioning hole exposing the surface of the semiconductor epitaxial wafer on the second dielectric layer in the first positioning hole;
and forming a field plate structure on the surface of the second dielectric layer and at the first positioning hole and the second positioning hole.
Further, the forming a first dielectric layer on the surface of the semiconductor epitaxial wafer includes:
and depositing a first dielectric layer on the surface of the semiconductor epitaxial wafer by one of plasma vapor deposition, quasi-atmospheric vapor deposition, low-pressure vapor deposition, sputtering evaporation and atomic layer deposition.
Further, the semiconductor epitaxial wafer includes: the semiconductor epitaxial wafer comprises a substrate, a buffer layer, an electronic channel layer, a barrier layer and a passivation layer, wherein the surface of the passivation layer is the surface of the semiconductor epitaxial wafer.
Further, after the first dielectric layer is formed on the surface of the semiconductor epitaxial wafer, the method further includes:
forming a first electrode hole and a second electrode hole exposing the barrier layer or the passivation layer on the first dielectric layer;
forming a metal layer on the surface of the first dielectric layer and the surfaces of the barrier layer or the passivation layer exposed by the first electrode hole and the second electrode hole through metal evaporation, wherein the surface of the metal layer is a flat surface;
and forming a hole exposing the surface of the first dielectric layer on the metal layer, wherein the metal layers at two ends of the hole form a first electrode and a second electrode of the semiconductor device.
Further, a first distance from a first end of the field plate structure to the first electrode is not more than half of a second distance from a first edge of the first positioning hole to the first electrode, a third distance from a second end of the field plate structure to the second electrode is not more than half of a fourth distance from a second edge of the first positioning hole to the second electrode, wherein the first end of the field plate structure is an end close to the first electrode, the second end of the field plate structure is an end close to the second electrode, the first edge of the first positioning hole is close to the edge of the first electrode, and the second edge of the first positioning hole is close to the edge of the second electrode.
Further, the metal evaporation comprises: including one of magnetron sputtering, electron beam evaporation, thermal evaporation and electroplating.
Further, forming a first positioning hole on the first dielectric layer to expose the surface of the semiconductor epitaxial wafer includes:
and forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer by combining a photoetching process and at least one of dry etching or wet etching.
Further, the thickness of the second dielectric layer is smaller than that of the first dielectric layer.
Furthermore, a corner formed by the second dielectric layer at the edge of the first positioning hole is of an arc-shaped structure.
Further, the width of the second positioning hole is the width of a third electrode of the semiconductor device.
According to the manufacturing method of the field plate of the semiconductor device, the first positioning hole is formed first, and then the second dielectric layer and the second positioning hole are formed, so that the finally formed field plate structure has the edge of the arc-shaped structure, the electric field at the edge of the field plate is not easy to be locally concentrated, the semiconductor device is not easy to break down, and the reliability of the semiconductor device is improved.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a field plate of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a field plate of a semiconductor device according to a second embodiment of the present invention;
fig. 3A is a schematic structural diagram of a semiconductor epitaxial wafer according to a second embodiment of the present invention;
fig. 3B is a schematic structural diagram of a semiconductor device for forming an electrode hole according to a second embodiment of the present invention;
fig. 3C is a schematic structural diagram of a semiconductor device for forming a metal layer according to a second embodiment of the present invention;
fig. 3D is a schematic structural diagram of a semiconductor device for forming a metal electrode according to a second embodiment of the present invention;
fig. 3E is a schematic structural diagram of a semiconductor device for forming a first positioning hole according to a second embodiment of the present invention;
fig. 3F is a schematic structural diagram of the semiconductor device for forming the second positioning hole according to the second embodiment of the present invention;
fig. 3G is a schematic structural diagram of a first corner according to a second embodiment of the present invention;
fig. 3H is a schematic structural diagram of a semiconductor device for forming a field plate structure according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first electrode can be referred to as a second electrode, and similarly, a second electrode can be referred to as a first electrode, without departing from the scope of the present application. The first electrode and the second electrode are both electrodes, but they are not the same electrode. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "plurality", "batch" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a schematic flow chart of a method for manufacturing a field plate of a semiconductor device according to an embodiment of the present invention, which may be applied to manufacturing a field plate structure of a semiconductor device, in particular, a field plate structure of a high-power semiconductor device, for example, a high-power semiconductor device made of materials such as gallium nitride, silicon carbide, gallium oxide, aluminum nitride, and the like. As shown in fig. 1, a method for manufacturing a field plate of a semiconductor device according to an embodiment of the present invention includes:
and S110, forming a first dielectric layer on the surface of the semiconductor epitaxial wafer.
In particular, the substrate refers to a silicon, silicon carbide or sapphire wafer, typically a passivation layer of a silicon compound deposited on the uppermost surface of the epitaxial wafer. The structure of the semiconductor epitaxial wafer comprises: the electron channel layer is arranged on the substrate and comprises a substrate, a buffer layer, an electron channel layer, a barrier layer and a passivation layer; the electronic channel layer is a device structure layer of the field effect transistor; the barrier layer is generally made of a material containing AlN components and serves to limit the electron distribution interval inside the electron channel layer. The passivation layer is a dielectric compound deposited on the surface of the semiconductor device, such as a semi-insulating or insulating material such as GaN, SiNx (representing polysilicon nitride), and the like.
The first dielectric layer can further passivate the surface of the semiconductor device, make the surface of the semiconductor device not easy to be oxidized, and isolate the inside of the semiconductor device from the outside, so as to prevent external impurities from entering the inside of the semiconductor device, for example, the first dielectric layer is SiOx (which represents polysilicon oxide).
Generally, the first dielectric layer may be deposited on the surface of the semiconductor epitaxial wafer by a deposition method, and the deposition method generally includes: plasma Enhanced Chemical Vapor Deposition (PECVD), Sub-atmospheric Chemical Vapor Deposition (SCVD), Low Pressure Vapor Deposition (LPCVD), sputter evaporation, Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD), among others.
And S120, forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer.
Specifically, the field plate structure is different according to the performance requirements of the semiconductor device, and generally speaking, the field plate structure of the semiconductor device requiring higher withstand voltage generally includes multiple stages, and the more the number of the stages of the field plate is, the higher the withstand voltage is. The size of the first positioning hole represents the positioning size of the primary field plate. And forming a first positioning hole on the first dielectric layer to expose the surface of the semiconductor epitaxial wafer, namely removing the first dielectric layer deposited on the surface of the semiconductor epitaxial wafer at the first positioning hole. Generally, the method for forming the first positioning hole includes photolithography, dry Etching and wet Etching, and the dry Etching may be implemented by using an inductively Coupled Plasma Emission Spectrometer (ICP), a Reactive Ion Etcher (RIE), and the like.
S130, forming a second dielectric layer on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole.
Specifically, after the first positioning hole is formed, a second dielectric layer is grown in a deposition mode, and the second dielectric layer completely covers the surface of the semiconductor epitaxial wafer on which the first dielectric layer has been grown during growth, that is, the second dielectric layer is formed on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole. The second dielectric layer is of a plate-type structure with uniform thickness, that is, the thickness of the second dielectric layer formed on the surface of the semiconductor epitaxial wafer exposed by the first positioning hole is equal to the thickness of the second dielectric layer formed on the surface of the first dielectric layer, and the second dielectric layer formed on the surface of the semiconductor epitaxial wafer exposed by the first positioning hole does not completely fill the first positioning hole in the height direction, which requires that the thickness of the second dielectric layer is smaller than that of the first dielectric layer, and generally, the thicknesses of the first dielectric layer and the second dielectric layer are both 0.1-2 micrometers.
The second dielectric layer is the same as the first dielectric layer, and may be formed by deposition, but a step-covering type dielectric growth method, such as PECVD, SACVD, etc., is required. By adopting a medium growing method with better step coverage, the corner formed by the second medium layer at the edge of the first positioning hole is of an arc-shaped structure.
And S140, forming a second positioning hole exposing the surface of the semiconductor epitaxial wafer on the second dielectric layer in the first positioning hole.
Specifically, the size of the second positioning hole is generally the size of the electrode at the field plate structure, and since the second positioning hole is formed on the second dielectric layer in the first positioning hole, the size of the second positioning hole is smaller than that of the first positioning hole. And forming a second positioning hole exposing the surface of the semiconductor epitaxial wafer on the second dielectric layer in the first positioning hole, namely removing the second dielectric layer deposited on the surface of the semiconductor epitaxial wafer at the second positioning hole in the first positioning hole. Generally, the method for forming the second positioning hole includes dry etching, wet etching, and the like, and the dry etching may be implemented by ICP, RIE, and the like.
S150, forming a field plate structure on the surface of the second dielectric layer and at the first positioning hole and the second positioning hole.
Specifically, the first positioning hole and the second positioning hole enable the surface of the semiconductor epitaxial wafer on which the first dielectric layer and the second dielectric layer are deposited to form a groove, the side wall of the groove is the second dielectric layer, the bottom of the groove comprises the surface of the semiconductor epitaxial wafer exposed by the second dielectric layer and the second positioning hole, and the field plate structure is arranged at the groove. The field plate structure can be realized by metal evaporation, such as magnetron sputtering, electron beam evaporation, thermal evaporation, electroplating and other methods. Because the corner that the second dielectric layer formed at the border of first locating hole is the arc structure, so the corner that field plate structure formed along the second dielectric layer of first locating hole border also is the arc structure, and the right angle that the second dielectric layer of lateral wall and bottom of field plate structure formed has the edge of arc structure to make field plate fringe electric field be difficult for local concentration.
According to the manufacturing method of the field plate of the semiconductor device, the first positioning hole is formed first, and then the second dielectric layer and the second positioning hole are formed, so that the finally formed field plate structure has the edge of the arc-shaped structure, the electric field at the edge of the field plate is not easy to be locally concentrated, the semiconductor device is not easy to break down, and the reliability of the semiconductor device is improved.
Example two
Fig. 2 is a schematic flow chart of a method for manufacturing a field plate of a semiconductor device according to a second embodiment of the present invention, which is a further refinement of the above embodiments. As shown in fig. 2, a method for manufacturing a field plate of a semiconductor device according to a second embodiment of the present invention includes:
s210, depositing a first dielectric layer on the surface of a semiconductor epitaxial wafer by one method of plasma vapor deposition, quasi-atmospheric vapor deposition, low-pressure vapor deposition, sputtering evaporation and atomic layer deposition, wherein the semiconductor epitaxial wafer comprises: the semiconductor epitaxial wafer comprises a substrate, a buffer layer, an electronic channel layer, a barrier layer and a passivation layer, wherein the surface of the passivation layer is the surface of the semiconductor epitaxial wafer.
Specifically, the surface of the semiconductor epitaxial wafer is usually a dielectric passivation layer deposited on the outermost surface of the semiconductor epitaxial wafer. As shown in fig. 3A, the semiconductor epitaxial wafer structure includes: a substrate and buffer layer 311, an electron channel layer 312, a barrier layer 313, and a passivation layer 314, wherein the substrate and buffer layer 311 is located at the lowermost; the electron channel layer 312 is a device structure layer of the field effect transistor; the barrier layer 313 is generally made of a material containing an AlN component for restricting an electron distribution interval inside the electron channel layer 312; the passivation layer 314 is a dielectric compound such as SiNx (representing polysilicon nitride) deposited on the surface of the barrier layer.
Generally, the first dielectric layer 320 may be deposited on the surface of the semiconductor epitaxial wafer by a deposition method, and the deposition method generally includes: plasma Enhanced Chemical Vapor Deposition (PECVD), Sub-atmospheric Chemical Vapor Deposition (SCVD), Low Pressure Vapor Deposition (LPCVD), sputter evaporation, Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD), among others. The first dielectric layer 320 may passivate the surface of the semiconductor device, make the surface of the semiconductor device less susceptible to oxidation, and isolate the inside of the semiconductor device from the outside, preventing external impurities from entering the inside of the semiconductor device, for example, the first dielectric layer 320 is SiOx (which means polysilicon oxide).
And S220, forming a first electrode hole and a second electrode hole which expose the barrier layer or the passivation layer on the first dielectric layer.
Specifically, as shown in fig. 3B, the first electrode hole 331 (shown by a dotted line in the figure for visual representation) and the second electrode hole 332 (shown by a dotted line in the figure for visual representation) are respectively located at two ends of the semiconductor device, the first electrode hole 331 and the second electrode hole 332 may be formed by dry Etching or wet Etching, and the dry Etching may be implemented by an inductively Coupled Plasma Emission Spectrometer (ICP), a Reactive Ion Etcher (RIE), or the like. The etching depth of the first electrode hole 331 and the second electrode hole 332 is from the surface of the first dielectric layer 320 to the surface of the barrier layer 313, i.e., the etching depth is the sum of the thicknesses of the first dielectric layer 320 and the passivation layer 314. In an alternative embodiment, the etch depth may also be from the surface of first dielectric layer 320 to the surface of passivation layer 314.
And S230, forming a metal layer on the surface of the first dielectric layer and the surface of the barrier layer or the passivation layer exposed by the first electrode hole and the second electrode hole through metal evaporation, wherein the surface of the metal layer is a flat surface.
Specifically, as shown in fig. 3C, after the first electrode hole 331 and the second electrode hole 332 are formed, a metal layer 330 is formed on the surface of the semiconductor epitaxial wafer by metal deposition, wherein the surface of the metal layer 330 is a flat surface, that is, the surface of the metal layer 330 is a non-porous plane, and the metal deposition method for forming the metal layer 330 includes magnetron sputtering, electron beam evaporation, thermal deposition, electroplating, and the like.
And S240, forming a hole exposing the surface of the first dielectric layer on the metal layer, wherein the metal layers at two ends of the hole form a first electrode and a second electrode of the semiconductor device.
Specifically, as shown in fig. 3D, a hole 333 (shown by a dotted line for visual representation) exposing the surface of the first dielectric layer 320 is formed in the metal layer 330, that is, the metal layer 330 in the hole 333 is removed, so that the metal layer 330 only remains at two ends of the semiconductor device, that is, only the metal layer 330 at the first electrode hole 331 and the metal layer 330 at the second electrode hole 332 remain, the metal layer 330 at the first electrode hole 331 forms a first electrode 334 of the semiconductor device, and the metal layer 330 at the second electrode hole 332 forms a second electrode 335 of the semiconductor device. The first electrode and the second electrode are electrically isolated from each other. Illustratively, the semiconductor device is a field effect transistor, then the first electrode 334 is a source and the second electrode 335 is a drain.
Further, after the first electrode 334 and the second electrode 335 are formed, the semiconductor device is subjected to an annealing process to form ohmic contacts between the first electrode 334 and the second electrode 335 and the semiconductor device. The annealing temperature is generally between 400 ℃ and 870 ℃, and the annealing environment is a less reactive gas, such as a nitrogen environment.
And S250, forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer by combining a photoetching process and at least one of dry etching or wet etching.
Specifically, the field plate structure is different according to the performance requirements of the semiconductor device, and generally speaking, the field plate structure of the semiconductor device requiring higher withstand voltage generally includes multiple stages, and the more the number of the stages of the field plate is, the higher the withstand voltage is. The size of the first positioning hole represents the positioning size of the primary field plate. As shown in fig. 3E, a first positioning hole 321 exposing the surface of the semiconductor epitaxial wafer is formed on the first dielectric layer 320, that is, the first dielectric layer 320 deposited on the surface of the semiconductor epitaxial wafer at the first positioning hole 321 is removed, so that the surface of the passivation layer 314 at the first positioning hole 321 is exposed. Generally, the first positioning hole 321 is formed by combining a photolithography process with a dry etching method or a wet etching method, and the dry etching method may be implemented by ICP, RIE, or the like.
And S260, forming a second dielectric layer on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole.
Specifically, after the first positioning hole is formed, a second dielectric layer is grown in a deposition mode, and the second dielectric layer completely covers the surface of the semiconductor epitaxial wafer on which the first dielectric layer has been grown during growth, that is, the second dielectric layer is formed on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole. As shown in fig. 3F, the second dielectric layer 340 is a plate-type structure with uniform thickness, that is, the thickness of the second dielectric layer 340 formed on the surface of the passivation layer 314 exposed by the first positioning hole 321 is equal to the thickness of the second dielectric layer 340 formed on the surface of the first dielectric layer 320, and the second dielectric layer 340 formed on the surface of the passivation layer 314 exposed by the first positioning hole 321 does not completely fill the first positioning hole 321 in the height direction, which requires that the thickness of the second dielectric layer 340 is smaller than the thickness of the first dielectric layer 320, and generally, the thicknesses of the first dielectric layer 320 and the second dielectric layer 340 are both 0.1 to 2 micrometers.
The second dielectric layer 340 is the same as the first dielectric layer 320, and may be formed by a deposition method, but a step-covering type dielectric growth method, such as PECVD, SACVD, etc., is required. By adopting a step-coverage type relatively good dielectric growth method, a first corner 341 formed by the second dielectric layer 340 at the edge of the first positioning hole 321 is in an arc-shaped structure, and the structure of the first corner 341 is shown in fig. 3G.
And S270, forming a second positioning hole exposing the surface of the semiconductor epitaxial wafer on the second dielectric layer in the first positioning hole.
Specifically, as shown in fig. 3F, a second positioning hole 342 exposing the surface of the semiconductor epitaxial wafer is formed on the second dielectric layer 340 in the first positioning hole 321, that is, in the first positioning hole 321, the second dielectric layer 340 deposited on the surface of the passivation layer 314 at the second positioning hole 342 is removed. The dimension of the second positioning hole 342 is generally the dimension of the electrode at the field plate structure, and for the exemplary semiconductor device being a field effect transistor, the electrode at the field plate structure is a gate, and the dimension of the second positioning hole 342 is the gate dimension. Since the second positioning hole 342 is formed on the second dielectric layer 340 in the first positioning hole 321, the size of the second positioning hole 342 is smaller than that of the first positioning hole 321.
Generally, the method for forming the second positioning hole 342 includes dry etching or wet etching, and the dry etching may be implemented by ICP, RIE, or the like. Preferably, in the present embodiment, the second positioning hole 342 is formed by using a wet etching method, and since the thickness of the second dielectric layer 340 is smaller than the thickness of the first dielectric layer 320, that is, the thickness of the second dielectric layer 340 at the edge of the second positioning hole 342 is smaller, the second corner 343 formed at the edge of the second positioning hole 342 can be made to be an arc-shaped structure by using the wet etching method.
And S280, forming a field plate structure on the surface of the second dielectric layer and at the first positioning hole and the second positioning hole.
Specifically, as shown in fig. 3H, the first positioning hole 321 and the second positioning hole 340 enable the surface of the semiconductor epitaxial wafer on which the first dielectric layer 320 and the second dielectric layer 340 are deposited to form a groove, the sidewalls of the groove are the second dielectric layer 340, the bottom of the groove includes the surface of the semiconductor epitaxial wafer (i.e., the surface of the passivation layer 314) exposed by the second dielectric layer 340 and the second positioning hole 342, and the field plate structure 350 is disposed in the groove. The field plate structure 350 may be implemented by metal evaporation, such as magnetron sputtering, electron beam evaporation, thermal evaporation, electroplating, or the like. Since the first corner 341 formed by the second dielectric layer 340 at the edge of the first positioning hole 321 is an arc-shaped structure, the field plate corner formed by the field plate structure 350 along the second dielectric layer 340 at the edge of the first positioning hole 321 is also an arc-shaped structure, that is, a right angle formed by the sidewall and the bottom of the field plate structure 350 has an edge of the arc-shaped structure, so that the electric field at the edge of the field plate is not easy to be locally concentrated.
Further, an end of the field plate structure 350 from the first electrode hole 331 is a first end 351, and an end of the field plate structure 350 from the second electrode hole 332 is a second end 352. In manufacturing the field plate structure 350, a distance between the first end 351 of the field plate structure 350 and the first electrode 334 is a first distance, and a distance between the first edge 321-1 of the first positioning hole 321 (i.e., the edge of the first positioning hole 321 close to the first electrode 334) and the first electrode 334 is a second distance, so that the first distance is less than or equal to half of the second distance. The distance between the second end 352 of the field plate structure 350 and the second electrode 335 is a third distance, and the distance between the second edge 321-2 of the first positioning hole 321 (i.e., the edge of the first positioning hole 321 close to the second electrode 335) and the second electrode 335 is a fourth distance, and then the third distance is less than or equal to half of the fourth distance.
The field plate structure 350 in this embodiment is a secondary field plate structure, that is, the field plate formed in the first positioning hole 321 is referred to as a primary field plate 353, and the field plate formed on the first dielectric layer 320 and the second dielectric layer 340 is referred to as a secondary field plate 354, when more stages of field plate structures need to be fabricated, a third dielectric layer, a fourth dielectric layer, and the like can continue to grow on the second dielectric layer, and corners formed by the multi-stage field plates are all arc-shaped structures by the fabrication method, so that local electric field concentration is avoided.
Further, as can be seen from fig. 3H, the distance between the primary field plate 353 of the field plate structure 350 and the barrier layer 313 of the semiconductor device is the sum of the thicknesses of the passivation layer 313 and the second dielectric layer 340, and generally, the thickness of the passivation layer 313 is fixed, so that the distance between the primary field plate 353 and the barrier layer 313 of the semiconductor device can be controlled by the thickness of the second dielectric layer 340, and the second dielectric layer 340 is formed by deposition through a dielectric growth method, and the thickness of the second dielectric layer 340 can be precisely controlled during the deposition process, so that the distance between the primary field plate 353 and the barrier layer 313 of the semiconductor device can be precisely controlled.
According to the manufacturing method of the field plate of the semiconductor device provided by the second embodiment of the invention, the first positioning hole is formed firstly, and then the second dielectric layer and the second positioning hole are formed, so that the finally formed field plate structure has the edge of an arc-shaped structure, the electric field at the edge of the field plate is not easy to be locally concentrated, the semiconductor device is not easy to break down, and the reliability of the semiconductor device is improved. In the manufacturing method of the field plate of the semiconductor device provided by the embodiment of the invention, no fixed limit is imposed on the selection of the materials of the first dielectric layer and the second dielectric layer, and even if the materials of the first dielectric layer and the second dielectric layer are the same, the distance between the field plate and the barrier layer can be accurately controlled, so that the electric field distribution is uniform, and the performance of the semiconductor device is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for manufacturing a field plate of a semiconductor device is characterized by comprising the following steps:
forming a first dielectric layer on the surface of the semiconductor epitaxial wafer;
forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer;
forming a second dielectric layer on the surface of the first dielectric layer and the surface of the semiconductor epitaxial wafer exposed by the first positioning hole;
forming a second positioning hole exposing the surface of the semiconductor epitaxial wafer on the second dielectric layer in the first positioning hole;
and forming a field plate structure on the surface of the second dielectric layer and at the first positioning hole and the second positioning hole.
2. The method of claim 1, wherein forming a first dielectric layer on a surface of the semiconductor epitaxial wafer comprises:
and depositing a first dielectric layer on the surface of the semiconductor epitaxial wafer by one of plasma vapor deposition, quasi-atmospheric vapor deposition, low-pressure vapor deposition, sputtering evaporation and atomic layer deposition.
3. The method of claim 1, wherein the semiconductor epitaxial wafer comprises: the semiconductor epitaxial wafer comprises a substrate, a buffer layer, an electronic channel layer, a barrier layer and a passivation layer, wherein the surface of the passivation layer is the surface of the semiconductor epitaxial wafer.
4. The method of claim 3, wherein after forming the first dielectric layer on the surface of the semiconductor epitaxial wafer, further comprising:
forming a first electrode hole and a second electrode hole exposing the barrier layer or the passivation layer on the first dielectric layer;
forming a metal layer on the surface of the first dielectric layer and the surfaces of the barrier layer or the passivation layer exposed by the first electrode hole and the second electrode hole through metal evaporation, wherein the surface of the metal layer is a flat surface;
and forming a hole exposing the surface of the first dielectric layer on the metal layer, wherein the metal layers at two ends of the hole form a first electrode and a second electrode of the semiconductor device.
5. The method of claim 4, wherein a first end of the field plate structure is a first distance from the first electrode that is no more than half of a second distance from a first edge of the first positioning hole to the first electrode, a second end of the field plate structure is a third distance from the second electrode that is no more than half of a fourth distance from a second edge of the first positioning hole to the second electrode, wherein the first end of the field plate structure is an end proximate to the first electrode, the second end of the field plate structure is an end proximate to the second electrode, the first edge of the first positioning hole is proximate to the edge of the first electrode, and the second edge of the first positioning hole is proximate to the edge of the second electrode.
6. The method of claim 4, wherein the metal evaporation comprises: including one of magnetron sputtering, electron beam evaporation, thermal evaporation and electroplating.
7. The method of claim 1, wherein forming a first locating hole in the first dielectric layer that exposes a surface of the semiconductor epitaxial wafer comprises:
and forming a first positioning hole exposing the surface of the semiconductor epitaxial wafer on the first dielectric layer by combining a photoetching process and at least one of dry etching or wet etching.
8. The method of claim 1, wherein a thickness of the second dielectric layer is less than a thickness of the first dielectric layer.
9. The method of claim 1, wherein a corner formed by the second dielectric layer at an edge of the first positioning hole is in an arc-shaped structure.
10. The method of claim 1, wherein a width of the second positioning hole is a width of a third electrode of the semiconductor device.
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| CN109786453A (en) * | 2018-04-25 | 2019-05-21 | 苏州捷芯威半导体有限公司 | Semiconductor devices and preparation method thereof |
| US20200066889A1 (en) * | 2016-09-30 | 2020-02-27 | Intel Corporation | Layered spacer formation for ultrashort channel lengths and staggered field plates |
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| CN1748320A (en) * | 2002-12-16 | 2006-03-15 | 日本电气株式会社 | Field-effect transistor |
| JP2016162879A (en) * | 2015-03-02 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
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