CN111554687B - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN111554687B CN111554687B CN202010322523.3A CN202010322523A CN111554687B CN 111554687 B CN111554687 B CN 111554687B CN 202010322523 A CN202010322523 A CN 202010322523A CN 111554687 B CN111554687 B CN 111554687B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides a preparation method of a semiconductor structure, which comprises the following steps: providing a semiconductor substrate comprising adjacent channel hole regions and gate spacer regions; forming an etching mask layer which comprises a plurality of channel hole patterns corresponding to the channel hole regions and virtual shallow trenches corresponding to the grid isolation groove regions; and etching the semiconductor substrate to form a channel hole in the channel hole region. In addition, the characteristic size of the etching mask layer is reduced by controlling the size relationship between the virtual shallow trench and the channel hole pattern, the structural environment of an inner row hole and an outer row hole of the channel hole can be further improved, so that the connectivity and the roundness of the channel hole can be improved, and the consistency of the inner row hole and the outer row hole can be improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a preparation method of a semiconductor structure.
Background
The memory cells of the three-dimensional memory are formed in the channel holes with high aspect ratio, the channel holes with high aspect ratio are usually realized by plasma dry etching, the roundness and the connectivity of the channel holes with high aspect ratio of the memory cells directly determine the memory performance of the device, the arrangement of the channel holes is various at present, for example, the channel holes are formed in 9 rows, and of course, other arrangement channel holes also exist, however, in the process of forming the channel holes, some channel holes, for example, the outer row holes in 9 rows, are easily affected by the surrounding structure environment, so that the connectivity and the circularity of the channel holes in the region are greatly affected.
Therefore, it is necessary to provide a semiconductor structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for fabricating a semiconductor structure, which is used to solve the problems in the prior art that some channel holes are easily affected by the surrounding structure environment, so that the connectivity and roundness of the channel holes in this area are greatly affected.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel hole region and a grid separating groove region which are adjacent;
forming an etching mask layer on the semiconductor substrate, wherein the etching mask layer comprises a plurality of channel hole patterns corresponding to the channel hole region and a virtual shallow trench corresponding to the grid isolation groove region; and
and etching the semiconductor substrate by taking the etching mask layer as a mask so as to form a channel hole in the channel hole region based on the channel hole pattern.
Optionally, a preset thickness is formed between the bottom of the dummy shallow trench and the upper surface of the semiconductor substrate, so that the gate isolation trench region is protected from being etched based on the etching mask layer with the preset thickness in the process of forming the channel hole.
Optionally, the preset thickness is greater than 80% of the thickness of the etching mask layer.
Optionally, the step of forming the etching mask layer includes:
sequentially forming a first mask layer and a second mask layer on the semiconductor substrate;
forming a graphical photoresist layer on the second mask layer, wherein graphs corresponding to the channel hole graph and the virtual shallow trench are formed in the graphical photoresist layer, and a photoresist residual layer is also formed in the graph at the position corresponding to the virtual shallow trench;
etching the second mask layer based on the patterned photoresist layer so as to form a pattern corresponding to the channel hole pattern and the virtual shallow trench in the second mask layer, and forming a mask residual layer corresponding to the photoresist residual layer;
and etching the first mask layer based on the etched second mask layer to form the channel hole pattern and the virtual shallow trench in the first mask layer to obtain the etched mask layer, wherein the virtual shallow trench is formed based on the mask residual layer.
Optionally, the step of forming the dummy shallow trench in the first mask layer based on the mask residual layer includes:
forming the channel hole pattern in the first mask layer, wherein the semiconductor substrate is exposed by the channel hole pattern;
and removing the mask residual layer and simultaneously forming the virtual shallow trench in the corresponding first mask layer below the mask residual layer.
Optionally, the mask residual layer is removed by an etching process, and the depth of the virtual shallow trench is controlled by controlling etching parameters of the etching process.
Optionally, the first mask layer includes a carbon layer, and the second mask layer includes a silicon oxynitride layer.
Optionally, the thickness of the photoresist residual layer is between 50 angstroms and 200 angstroms.
Optionally, the step of forming an anti-reflection layer on the second mask layer is further included after the second mask layer is formed, and the patterned photoresist layer is formed on the anti-reflection layer.
Optionally, after the channel hole is formed, the thickness of the etching mask layer remaining at the position corresponding to the virtual shallow trench is greater than 2000 angstroms.
Optionally, the trench hole patterns are uniformly spaced, and a distance between the dummy shallow trench and the adjacent trench hole pattern is equal to a distance between the adjacent trench hole patterns.
Optionally, the semiconductor substrate includes a semiconductor substrate and a stacked structure formed on the semiconductor substrate, the stacked structure includes dielectric layers and sacrificial layers stacked alternately, and the channel hole penetrates through the stacked structure.
Optionally, the method for manufacturing a semiconductor structure further includes: and forming a channel structure in the channel hole, and/or forming a grid separating groove in the laminated structure corresponding to the grid separating groove region, and replacing the sacrificial layer with a grid layer through the grid separating groove.
Optionally, an X direction and a Y direction perpendicular to each other are defined in a plane parallel to the upper surface of the semiconductor substrate, the X direction is parallel to the arrangement direction of the gate spacer region and the channel region, the Y direction is parallel to the direction in which the gate spacer region extends, wherein a distance between an edge of the dummy shallow trench and an edge of the gate spacer region adjacent thereto in the X direction is defined as a first distance, a distance between an edge of the dummy shallow trench and an edge of the gate spacer region adjacent thereto in the Y direction is defined as a second distance, and the first distance is 45 times to 55 times the second distance.
As described above, according to the method for manufacturing a semiconductor structure of the present invention, the dummy shallow trench is formed on the etching mask layer corresponding to the gate spacer region, so that the etching mask material at the position can be reduced, by-products generated by etching the mask material can be reduced, and the influence of the by-products on the etching of the trench hole can be reduced during the etching of the trench hole.
Drawings
FIG. 1 is a process flow diagram illustrating the fabrication of a semiconductor structure according to the present invention.
FIG. 2 is a schematic diagram of a semiconductor substrate provided in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram illustrating formation of an etching mask layer in the semiconductor structure fabrication according to an embodiment of the present invention.
FIG. 4 is a schematic diagram illustrating the formation of a channel hole in the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a first mask layer and a second mask layer in the semiconductor structure fabrication according to an embodiment of the invention.
FIG. 6 is a schematic diagram illustrating a structure of an anti-reflective layer formed in the semiconductor structure manufacturing process according to an embodiment of the invention.
FIG. 7 is a schematic diagram illustrating a patterned photoresist layer formed during the fabrication of a semiconductor structure according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram illustrating etching of a second mask layer in the semiconductor structure fabrication according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram illustrating etching of a first mask layer in the semiconductor structure fabrication according to an embodiment of the present invention.
Fig. 10 is a schematic structural diagram illustrating formation of an etching mask layer in the semiconductor structure fabrication according to an embodiment of the present invention.
FIG. 11 is a schematic diagram of the semiconductor substrate, the gate spacer region and the trench hole in accordance with an embodiment of the present invention.
FIG. 12 is a schematic diagram showing the effect of the material of the etching mask layer on the trench hole when the trench hole etching is performed in a comparative manner according to the present invention.
Fig. 13 is a scanned view of the structure at the dummy trench after etching the trench hole in the embodiment of the present invention.
Description of the element reference numerals
100 semiconductor substrate
101 semiconductor substrate
102. 104, 106, 108, 110, dielectric layer
112、114、116
103. 105, 107, 109, 111, sacrificial layer
113、115
117 first mask layer
118 second mask layer
119 anti-reflection layer
120 patterned photoresist layer
121 pattern corresponding to the trench hole pattern
122 corresponding to the dummy shallow trench
123 photoresist residual layer
124 corresponding to the trench hole pattern
125 pattern corresponding to the dummy shallow trench
126 mask residual layer
200 laminated structure
300 etch mask layer
301 channel hole pattern
302 dummy shallow trench
400 channel hole
d. Distance w, s1, s2
S1-Sn step
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel hole region and a grid separating groove region which are adjacent;
forming an etching mask layer on the semiconductor substrate, wherein the etching mask layer comprises a plurality of channel hole patterns corresponding to the channel hole region and a virtual shallow trench corresponding to the grid isolation groove region; and
and etching the semiconductor substrate by taking the etching mask layer as a mask so as to form a channel hole in the channel hole region based on the channel hole pattern.
The method for fabricating the semiconductor structure of the present invention will be described in detail with reference to the accompanying drawings.
As shown in S1 in fig. 1 and fig. 2, a semiconductor substrate 100 is provided, and adjacent channel hole regions a and gate spacer regions B are defined in the semiconductor substrate 100.
Specifically, the structure of the semiconductor substrate 100 including the adjacent channel hole region a and the adjacent gate spacer region B can be seen from the top view of fig. 11, in an example, both sides of the channel hole region a are the gate spacer regions B. In one example, the semiconductor substrate 100 is provided, for example, a memory, in which gate spacer regions B are formed on two sides of a channel hole region a for forming a channel hole of the device, and gate spacer regions B are formed subsequently for forming gate spacers to be further used for preparing a gate of the device, for example, a 9-row hole structure in a three-dimensional memory, in which 8 rows of functional channel holes are separated by two gate spacer regions B, and in addition, a row of dummy holes are formed in the middle, and a top gate Cut (TSG Cut) is formed above the dummy holes.
The semiconductor substrate 100 may be a single-layer material layer, or a stacked structure composed of multiple material layers, and may be a Silicon material layer, a germanium material layer, an SOI (Silicon-on-insulator), or the like. In one example, as shown in fig. 2, the semiconductor substrate 100 includes a semiconductor substrate 101 and a stacked structure 200 formed on the semiconductor substrate 101, wherein the stacked structure 200 includes dielectric layers 102, 104, 106, 108, 110, 112, 114, 116 and sacrificial layers 103, 105, 107, 109, 111, 113, 115 that are alternately stacked. Wherein the subsequently formed channel hole passes through the stacked structure.
In this example, the semiconductor substrate 101 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, a GOI (Germanium-on-Insulator) substrate, and the like, in other embodiments, the semiconductor substrate 101 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, silicon carbide, and the like, the semiconductor substrate 101 may also be a stacked structure, such as a silicon/Germanium-silicon stacked structure, and the like, and in this embodiment, the semiconductor substrate 101 includes a single crystal silicon substrate. The semiconductor substrate 101 may be an ion-doped substrate, may be P-doped or N-doped, and the semiconductor substrate 101 may further include a plurality of peripheral devices, such as field effect transistors, capacitors, inductors, and/or pn junction diodes, and the semiconductor substrate 101 may further include a peripheral circuit.
In addition, the dielectric layer of the stacked structure 200 includes, but is not limited to, a silicon dioxide layer, and the sacrificial layer of the stacked structure 200 includes, but is not limited to, a silicon nitride layer, optionally, the dielectric layer and the sacrificial layer have a certain selection ratio in the same etching/etching process to ensure that the dielectric layer is hardly removed when the sacrificial layer is removed. The stacked structure 200 may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or an Atomic Layer Deposition (ALD) process. In an example, the stacked structure 200 may include the dielectric layers and the sacrificial layers that are alternately stacked from bottom to top in sequence, both the bottom layer and the top layer of the stacked structure 200 are the dielectric layers, such as the dielectric layer 102 and the dielectric layer 116 in fig. 2, and the upper surface of the dielectric layer 116 located at the top layer is the upper surface of the stacked structure 200. The number of layers of the dielectric layer and the sacrificial layer in the stacked structure 200 may include 32 layers, 64 layers, 96 layers, 128 layers, or the like, and specifically, the number of layers and the thickness of the dielectric layer and the sacrificial layer in the stacked structure 200 may be set according to actual needs, which is not limited herein.
As shown in S2 of fig. 1 and fig. 3-10, an etching mask layer 300 is formed on the semiconductor substrate 100, wherein the etching mask layer 300 includes a plurality of trench hole patterns 301 corresponding to the trench hole regions a and dummy shallow trenches 302 corresponding to the gate spacer regions B, as shown in fig. 3. The etching mask is used as a mask layer for subsequently etching the semiconductor substrate 100, the trench hole pattern 301 is used for transferring the pattern to the semiconductor substrate 100 to form a trench hole 400, and a functional sidewall layer and a channel layer may be subsequently prepared in the trench hole 400, for example, the functional sidewall layer may be a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer which are sequentially formed on the sidewall of the trench hole 400, and the channel layer may be a polysilicon layer, so as to further complete the preparation of the device.
In this step, the dummy shallow trench 302 is formed at a position of the etching mask layer 300 corresponding to the gate isolation trench region B, so that the material of the position on the etching mask layer 300 used for etching the channel hole 400 is reduced, that is, the material of the mask layer adjacent to the channel hole region a is reduced, thereby being beneficial to reducing the formation of by-products caused by the material of the mask layer entering the channel hole during the subsequent etching formation process of the channel hole 400, and affecting the etching effect.
As an example, as shown in fig. 5-10, the step of forming the etch mask layer 300 includes:
first, as shown in fig. 5, a first mask layer 117 and a second mask layer 118 are sequentially formed on the semiconductor substrate 100, for example, the material of the first mask layer 117 includes C, the material of the second mask layer 118 includes SION, and the forming process includes, but is not limited to, a chemical vapor deposition process. In another alternative example, as shown in fig. 6, after forming the second mask layer 118, a step of forming an anti-reflective layer 119(BARC) on the second mask layer 118 is further included, and the patterned photoresist layer 120 is formed on the anti-reflective layer 119.
Next, as shown in fig. 7, a patterned photoresist layer 120 is formed on the second mask layer 118, wherein a pattern 121 corresponding to the trench hole pattern and a pattern 122 corresponding to the dummy shallow trench are formed in the patterned photoresist layer 120, and a photoresist residual layer 123 is formed in the pattern 122 corresponding to the dummy shallow trench. Wherein, the photoresist residual layer 123 can be obtained by controlling exposure and development parameters. As an example, the thickness of the photoresist residual layer 123 is between 50 a and 200 a, such as 60 a, 80 a, 100 a, and 150 a, so as to facilitate the subsequent formation of the dummy shallow trench 302 with a desired depth.
As an example, referring to fig. 11, an X direction and a Y direction perpendicular to each other are defined in a plane parallel to the upper surface of the semiconductor substrate 100, the X direction is parallel to the arrangement direction of the gate spacer region B and the channel hole region a, the Y direction is parallel to the direction in which the gate spacer region B extends, wherein a distance between an edge of the dummy shallow trench 302 and an edge of the gate spacer region B adjacent to the edge of the dummy shallow trench 302 in the X direction is k, i.e., the first distance k, a distance between an edge of the dummy shallow trench 302 and an edge of the gate spacer region B adjacent to the edge of the dummy shallow trench 302 in the Y direction is h, i.e., the second distance h, and the first distance k is between 45 times and 55 times, for example, 50 times, the first distance k is equal to the second distance h, and the formation of the dummy shallow trench 302 in the above shape is advantageous for the patterned photoresist layer 120 having a pattern corresponding to the channel hole pattern 301 and the dummy shallow trench 302 in the present invention In the conventional exposure and development process, the photoresist residual layer 123 is formed, for example, the shape of the dummy shallow trench 302 is rectangular, the pattern of the formed trench hole is circular, and both the dummy shallow trench 302 and the trench hole are prepared based on the same process when forming a pattern on the patterned photoresist layer 120, so that the photoresist residual layer 123 can be obtained at a position corresponding to the dummy shallow trench 302 under the same exposure and development conditions with the same exposure energy, and in an optional example, the exposure setting for performing the above process may be: immersion lithography implantation with a light source of 193 set to Freeform was used. Energy 29mj, Focu0, and OVL selects CPE (correction Per exposure), but not limited thereto.
Continuing, as shown in fig. 8, the second mask layer 118 is etched based on the patterned photoresist layer 120, so as to form a pattern 124 corresponding to a trench hole pattern and a pattern 125 corresponding to a dummy shallow trench in the second mask layer 118, and a mask residual layer 126 corresponding to the photoresist residual layer 123. The material of the second mask layer can be selected to be SION, and etching gas can be selected to be SF6/CH2F2/N2/HE, CF + SIO-SIF 4+ CO2, SIF4 and CO2 which are taken as gas to be pumped away by Pump. In an example, when the anti-reflection layer 119 is formed, the anti-reflection layer 119 may be etched based on the same process as the second mask layer 118. In addition, in an optional example, after the second mask layer 118 is etched, a step of removing the anti-reflection layer 119 and the patterned photoresist layer 120 on the second mask layer 118 is further included, as shown in fig. 9.
Finally, as shown in fig. 10, the first mask layer 117 is etched based on the etched second mask layer 118 to form the trench hole pattern 301 and the dummy shallow trench 302 in the first mask layer 117, thereby obtaining the etched mask layer 300, and the dummy shallow trench 302 is formed based on the mask residual layer 126, wherein when the first mask layer is selected to be C, O2/COS is used for reactive etching, at this time, when the mask residual layer is remained, if there is a SION remained, the SION is not yet completely opened, the rest of the SION cannot be opened by using the gas O2/COS later, and finally, the dummy shallow trench is formed in the mask residual layer 126.
As an example, the step of forming the dummy shallow trench 302 in the first mask layer 117 based on the mask residual layer 126 includes:
firstly, etching the first mask layer 117 based on the etched second mask layer 118 to form the channel hole pattern 301 in the first mask layer 117, wherein the channel hole etching pattern 301 exposes the semiconductor substrate 100;
then, the mask residual layer 126 is removed and the dummy shallow trench 302 is formed in the corresponding first mask layer 117 below the mask residual layer 126 at the same time, that is, in the process of removing the mask residual layer 126 after forming the trench hole pattern, a portion of the first mask layer 117 below the mask residual layer 126 is consumed, so that the dummy shallow trench 302 is formed in the first mask layer 117. In an example, the mask residual layer 126 is removed by an etching process, and the depth of the dummy shallow trench 302 is controlled by controlling an etching parameter of the etching process. For example, in the present embodiment, the mask residual layer 126 is selected as a silicon oxynitride SION layer, and the optional removal process may be: source Power600W, Bias Power300V, CF4/CHF 350/50 sccm Time30s.
As shown in S3 of fig. 1 and fig. 4, the semiconductor substrate 100 is etched using the etching mask layer 300 as a mask to form a trench hole 400 in the trench hole region a based on the trench hole pattern 301. In this step, the semiconductor substrate 100 is etched based on the etching mask layer 300 formed in the previous step, wherein under the action of the virtual shallow trench 302, the material of the etching mask layer 300 in this trench portion is removed due to the formation of the groove, so that in the etching process of the channel hole 400, by-products generated based on this portion of the material layer are reduced, for example, the formed C-F by-products are reduced, thereby reducing the influence of the formed by-products falling into the channel hole 400 and etching the channel hole 400, especially reducing the influence of etching the outer discharge hole adjacent to the gate spacer region B corresponding to the virtual shallow trench 302, thereby improving the connectivity and roundness of this portion of the channel hole 400, improving the uniformity of the whole channel hole 400 in the channel region a, and improving the performance of the device. In a comparative example, referring to fig. 12, the mask material corresponding to the gate spacer region B is not removed, so that the amount of the formed by-products 704 falling into the outer row holes 701 and 702 in the channel hole region a is greater than the amount falling into the inner row hole 703, thereby affecting the uniformity of the entire channel hole, easily causing the outer row holes to be etched incompletely, and affecting the connectivity and roundness of the outer row holes.
In addition, the dummy shallow trench 302 is formed in the etching mask layer 300, and may expose the upper surface of the semiconductor substrate 101, but of course, a part of the material layer under the gate spacer region B may be sacrificed in the etching of the channel hole 400, and may be filled in a subsequent process or directly used. In addition, in a preferred example, a preset thickness d is provided between the bottom of the dummy shallow trench 302 and the upper surface of the semiconductor substrate 100, so that the gate isolation region B is protected from being etched based on the etching mask layer 300 with the preset thickness d in the process of forming the channel hole 400, that is, the etching mask layer 300 with the preset thickness exists on the semiconductor substrate 100, and when the channel hole 400 is formed by subsequent etching, the material layer in the gate isolation region B is kept intact and is not etched, wherein the preset thickness value may be set according to a material etching selection ratio, etching process parameters, and the like. Optionally, the preset thickness d is greater than 80% of the thickness of the etching mask layer 300, for example, may be 85% or 90%, so as to be beneficial to protecting the material layer in the gate spacer region B during the etching process.
As an example, after the channel hole 400 is formed, the thickness w of the etching mask layer 300 remaining at the position corresponding to the dummy shallow trench 302 is greater than 2000 angstroms. For example, 2500 angstroms or 3000 angstroms may be used to maintain a certain safety margin, which is advantageous for protecting the lower lamination material and further advantageous for improving the penetration and roundness of the channel hole 400. Fig. 13 shows a scanning photograph of the virtual shallow trench after the etching of the channel hole 400 in an example, and it can be seen that a certain material of the etching mask layer 300 exists.
In addition, the formation of the dummy shallow trenches 302 is also beneficial to reducing the feature size of the etching mask layer 300, in an example, the trench hole patterns 301 are uniformly spaced apart from each other, and the distance between the dummy shallow trenches 302 and the adjacent trench hole patterns 301 is equal to the distance between the adjacent trench hole patterns 301, that is, along the direction perpendicular to the extension direction of the gate spacer region B, for example, as can be seen from fig. 11, which shows the gate spacer region B, the trench hole region a, the outer rows of holes 601, 602, the inner row of holes 603 and the top gate partition 500, and the inner row of holes and the outer row of holes at other positions are not shown, as will be understood by those skilled in the art according to the present invention, in this example, the trench holes 400 in the trench hole region a are arranged in a periodic array, for example, a 9-row hole structure is formed, and the distance s1 between the adjacent trench hole patterns 301 is equal to the distance s1 between the dummy trench holes 302 and the adjacent trench hole patterns 301 The distance s2 between the trench hole patterns 301 enables the etching environment of each inner row of the trench holes 400 to be consistent with that of each outer row of the trench holes, which is further beneficial to improving the uniformity of each trench hole 400.
As an example, the method for manufacturing a semiconductor structure further includes the steps of: forming a channel structure in the channel hole 400 may form a NAND string in the device channel hole 401, which is capable of storing data.
As an example, gate spacers are formed in the semiconductor substrate 100 (the stacked structure 200 when the stacked structure 200 is included) corresponding to the gate spacer region B, and the sacrificial layer is replaced with a gate layer through the gate spacers to prepare gates of devices. Further, a spacer filling structure, such as a filling structure comprising a W material or a polysilicon material, is also formed in the gate spacer to lead out the source of the device.
In summary, according to the method for manufacturing a semiconductor structure of the present invention, the dummy shallow trench is formed on the etching mask layer corresponding to the gate spacer region, so that the etching mask material at the position can be reduced, by-products generated by etching the mask material can be reduced, and the influence of the by-products on the etching of the trench hole can be reduced during the etching process of the trench hole. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. A method for fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel hole region and a grid separating groove region which are adjacent;
forming an etching mask layer on the semiconductor substrate, wherein the etching mask layer comprises a plurality of channel hole patterns corresponding to the channel hole regions and a virtual shallow trench corresponding to the grid isolation groove region, and a preset thickness is formed between the bottom of the virtual shallow trench and the upper surface of the semiconductor substrate and is greater than 80% of the thickness of the etching mask layer; and
and etching the semiconductor substrate by taking the etching mask layer as a mask so as to form a channel hole in the channel hole region based on the channel hole pattern.
2. The method of claim 1, wherein the step of forming the etch mask layer comprises:
sequentially forming a first mask layer and a second mask layer on the semiconductor substrate;
forming a graphical photoresist layer on the second mask layer, wherein graphs corresponding to the channel hole graph and the virtual shallow trench are formed in the graphical photoresist layer, and a photoresist residual layer is also formed in the graph at the position corresponding to the virtual shallow trench;
etching the second mask layer based on the patterned photoresist layer so as to form a pattern corresponding to the channel hole pattern and the virtual shallow trench in the second mask layer, and forming a mask residual layer corresponding to the photoresist residual layer;
and etching the first mask layer based on the etched second mask layer to form the channel hole pattern and the virtual shallow trench in the first mask layer to obtain the etched mask layer, wherein the virtual shallow trench is formed based on the mask residual layer.
3. The method of claim 2, wherein the step of forming the dummy shallow trench in the first mask layer based on the mask residual layer comprises:
etching the first mask layer based on the etched second mask layer to form a channel hole pattern in the first mask layer, wherein the channel hole pattern exposes the semiconductor substrate;
and removing the mask residual layer and simultaneously forming the virtual shallow trench in the corresponding first mask layer below the mask residual layer.
4. The method of claim 3, wherein the mask residue layer is removed by an etching process, and the depth of the dummy shallow trench is controlled by controlling etching parameters of the etching process.
5. The method of claim 2, wherein the first mask layer comprises a carbon layer and the second mask layer comprises a silicon oxynitride layer.
6. The method of claim 2, wherein the photoresist residue layer has a thickness of between 50 angstroms and 200 angstroms.
7. The method of claim 2, further comprising a step of forming an anti-reflective layer on the second mask layer after the second mask layer is formed, and wherein the patterned photoresist layer is formed on the anti-reflective layer.
8. The method as claimed in claim 1, wherein the thickness of the etching mask layer remaining at the position corresponding to the dummy shallow trench after the formation of the trench hole is greater than 2000 angstroms.
9. The method as claimed in claim 1, wherein the trench hole patterns are uniformly spaced apart from each other, and a distance between the dummy shallow trench and the adjacent trench hole pattern is equal to a distance between the adjacent trench hole patterns.
10. The method of claim 1, wherein the semiconductor substrate comprises a semiconductor substrate and a stacked structure formed on the semiconductor substrate, the stacked structure comprising alternately stacked dielectric layers and sacrificial layers, wherein the channel hole penetrates through the stacked structure.
11. The method of claim 10, further comprising the steps of: and forming a channel structure in the channel hole, and/or forming a grid separating groove in the laminated structure corresponding to the grid separating groove region, and replacing the sacrificial layer with a grid layer through the grid separating groove.
12. The method according to any one of claims 1 to 11, wherein an X direction and a Y direction are defined in a plane parallel to the upper surface of the semiconductor substrate, the X direction being parallel to the direction in which the gate spacer region and the channel hole region are arranged, the Y direction being parallel to the direction in which the gate spacer region extends, and wherein a distance between an edge of the dummy shallow trench and an edge of the gate spacer region adjacent thereto in the X direction is defined as a first distance, and a distance between an edge of the dummy shallow trench and an edge of the gate spacer region adjacent thereto in the Y direction is defined as a second distance, and the first distance is 45 to 55 times the second distance.
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| CN101937832A (en) * | 2009-07-03 | 2011-01-05 | 中芯国际集成电路制造(上海)有限公司 | Dry etching method |
| CN105824202A (en) * | 2016-05-11 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Photoresist removal method and semiconductor device manufacturing method |
| CN108493191A (en) * | 2018-04-12 | 2018-09-04 | 长江存储科技有限责任公司 | The photomask for forming the method for the grid separate slot of three-dimensional storage part and its using |
| CN109585281A (en) * | 2018-12-05 | 2019-04-05 | 扬州扬杰电子科技股份有限公司 | A kind of method for etching wafer |
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| KR20090069054A (en) * | 2007-12-24 | 2009-06-29 | 주식회사 동부하이텍 | Method of fabricating semiconductor device |
| CN107731846B (en) * | 2017-08-31 | 2019-01-01 | 长江存储科技有限责任公司 | Improve the three-dimensional storage forming method of channel through-hole homogeneity |
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| CN101937832A (en) * | 2009-07-03 | 2011-01-05 | 中芯国际集成电路制造(上海)有限公司 | Dry etching method |
| CN105824202A (en) * | 2016-05-11 | 2016-08-03 | 上海华虹宏力半导体制造有限公司 | Photoresist removal method and semiconductor device manufacturing method |
| CN108493191A (en) * | 2018-04-12 | 2018-09-04 | 长江存储科技有限责任公司 | The photomask for forming the method for the grid separate slot of three-dimensional storage part and its using |
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