CN111554673A - Multilayer chip stacking packaging structure and multilayer chip stacking packaging method - Google Patents
Multilayer chip stacking packaging structure and multilayer chip stacking packaging method Download PDFInfo
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- CN111554673A CN111554673A CN202010406039.9A CN202010406039A CN111554673A CN 111554673 A CN111554673 A CN 111554673A CN 202010406039 A CN202010406039 A CN 202010406039A CN 111554673 A CN111554673 A CN 111554673A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention provides a multilayer chip stacking and packaging structure and a multilayer chip stacking and packaging method, which relate to the technical field of chip packaging, wherein the multilayer chip stacking and packaging structure comprises a substrate, a base chip set stacked on the substrate, a first stacking chip set stacked on the left side of the base chip set and inclined to the left in a step shape, a second stacking chip set stacked on the first stacking chip set and inclined to the right in a step shape, a third stacking chip set stacked on the right side of the base chip set and inclined to the right in a step shape, a fourth stacking chip set stacked on the third stacking chip set and inclined to the left in a step shape, and a middle stacking chip set stacked in the middle of the base chip set; wherein the second stacked chipset portion is stacked on a left side of the middle stacked chipset and the fourth stacked chipset portion is stacked on a right side of the middle stacked chipset. Compared with the prior art, the invention adopts a novel stacking structure, has stable structure and more chips, and greatly reduces the packaging size.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a multilayer chip stacking packaging structure and a multilayer chip stacking packaging method.
Background
With the rapid development of the semiconductor industry, electronic products are miniaturized more and more thinly to meet the requirements of users and product performance and memory are higher and higher, so that a semiconductor packaging structure adopts a multi-chip Stack-Die (Stack-Die) technology or a chip fow (flow over wire) stacking technology to Stack two or more chips in a single packaging structure, thereby realizing the reduction of the packaging volume of the product and the improvement of the product performance. Such stacked products (memory cards/cards) usually have 2 types of chips, memory chips and chips, and are packaged in the same substrate unit by stacking.
The stacking mode in the prior art generally has the problems of large product packaging size, unstable structure, difficulty in lifting the stacking layer number, limited stacking quantity and the like.
Disclosure of Invention
The invention aims to provide a multilayer chip stacking and packaging structure which is stable in structure, can greatly increase the number of stacking layers and the stacking number and greatly reduce the packaging size.
Another objective of the present invention is to provide a method for stacking and packaging multiple chips, which has a stable stacking structure, can greatly increase the number of stacked layers and the number of stacked chips, and greatly reduce the packaging size.
The invention is realized by adopting the following technical scheme.
In one aspect, the present invention provides a multi-layered chip stack package structure, comprising:
a substrate;
a base chip set stacked on the substrate;
a first stacked chip group stacked on the left side of the base chip group and inclined to the left in a step shape;
a second stacked chip group stacked on the first stacked chip group and inclined to the right in a step shape;
a third stacked chip group stacked on the right side of the substrate chip group and inclined towards the right in a step shape;
a fourth stacked chip set stacked on the third stacked chip set and inclined to the left in a stair shape;
and an intermediate laminated chip set stacked in the middle of the base chip set;
wherein the second stacked chipset portion is stacked on a left side of the middle stacked chipset and the fourth stacked chipset portion is stacked on a right side of the middle stacked chipset.
Further, the middle laminated chip group comprises a laminated chip unit and a structural chip unit, the laminated chip unit comprises a plurality of laminated chips which are vertically stacked on the substrate chip group in sequence, the structural chip unit is stacked on the laminated chip unit and extends out towards the left side and the right side, the second laminated chip group part is stacked on the left side of the structural chip unit, and the fourth laminated chip group part is stacked on the right side of the structural chip unit.
Further, the structure chip unit comprises a first structure chip, a second structure chip and a third structure chip, the first structure chip is stacked on the laminated chip unit, the second structure chip and the third structure chip are stacked on the first structure chip side by side, the first structure chip, the second structure chip and the third structure chip form a T-shaped structure, so that the second structure chip and the third structure chip extend towards the left side and the right side respectively, the second stacked chip group is partially stacked on the second structure chip, and the fourth stacked chip group is partially stacked on the third structure chip.
Further, each of the stacked chips is connected to the first stacked chip group and the third stacked chip group through stacked connection lines on two sides, respectively.
Further, the first stacked chip group comprises a plurality of first stacked chips stacked layer by layer in a stepped manner to the left, and each first stacked chip is electrically connected with the adjacent first stacked chip or the base chip group through a first connecting line; the second stacked chip group comprises second stacked chips stacked layer by layer rightwards in a stepped manner, each second stacked chip is electrically connected with the adjacent second stacked chip or the first stacked chip through a second connecting line, and one second stacked chip is partially stacked on the left side of the middle stacked chip group.
Further, the third stacked chip group comprises third stacked chips stacked layer by layer rightwards in a stepped manner, and each third stacked chip is electrically connected with the adjacent third stacked chip or the base chip group through a third connecting line; the fourth stacked chip group comprises fourth stacked chips stacked layer by layer leftwards in a stepped mode, each fourth stacked chip is electrically connected with the adjacent fourth stacked chip or the third stacked chip through a fourth connecting line, and one fourth stacked chip is partially stacked on the right side of the middle laminated chip group.
Further, the base chip set includes a control chip, a first base chip, a second base chip and a third base chip, the control chip is attached to the substrate, the first base chip is stacked on the control chip, the second base chip is stacked on the left half of the first base chip, the third base chip is stacked on the right half of the first base chip, the first stacked chip set is stacked on the left half of the second base chip, the third stacked chip set is stacked on the right half of the third base chip, and the middle stacked chip set is stacked on the right half of the second base chip and the left half of the third base chip.
Furthermore, a groove is formed in the substrate, the base chip set is partially accommodated in the groove, and glue is filled in the groove.
Further, the multi-chip stacked package structure further includes a plastic package body, and the plastic package body is wrapped outside the base chip set, the first stacked chip set, the second stacked chip set, the third stacked chip set, the fourth stacked chip set, and the middle stacked chip set.
In another aspect, the present invention provides a multilayer chip stack packaging method, including the steps of:
stacking the base chip set on the substrate;
stacking the middle laminated chip set in the middle of the substrate chip set;
stacking a first stacked chip set on the left side of the base chip set in a manner of inclining towards the left in a step shape;
stacking a second stacked chip set on the first stacked chip set in a step shape and inclining to the right;
stacking a third stacked chip set on the right side of the substrate chip set in a step shape and inclining rightwards;
stacking a fourth stacked chip set on the third stacked chip set in a step shape and inclining to the left;
wherein the second stacked chipset portion is stacked on a left side of the middle stacked chipset and the fourth stacked chipset portion is stacked on a right side of the middle stacked chipset.
The invention has the following beneficial effects:
the invention provides a multilayer chip stacking and packaging structure.A left-side staggered laminated structure is formed by adopting a first stacked chip group which is inclined to the left in a step shape and a second stacked chip group which is stacked on the first stacked chip group and is inclined to the right in a step shape; a right side staggered laminated structure is formed by adopting a third stacked chip set which is inclined towards the right in a step shape and a fourth stacked chip set which is stacked on the third stacked chip set and inclined towards the left in a step shape; and then stacking the middle laminated chip group on the substrate chip group to form a middle laminated structure, wherein the second laminated chip group is partially stacked on the left side of the middle laminated chip group, and the fourth laminated chip group is partially stacked on the right side of the middle laminated chip group. Through adopting left side dislocation stromatolite structure, middle stromatolite structure, right side dislocation stromatolite structure to combine together, can realize that the chip piles up simultaneously, its structure is more firm, can pile up more quantity of chip, avoids the unstable problem that influences product quality of structure among the traditional lamination technology. Compared with the prior art, the multilayer chip stacking and packaging structure provided by the invention is a novel stacking structure, is stable in structure, increases the number of stacking layers, and greatly reduces the packaging size.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic overall structure diagram of a multi-layer chip stack package structure according to a first embodiment of the invention;
fig. 2 is a partial structural schematic view of a multi-layer chip stack package structure according to a first embodiment of the invention;
fig. 3 is a block diagram illustrating steps of a method for packaging a stacked multi-chip package according to a second embodiment of the invention.
Icon: 100-multilayer chip stack package structure; 110-a substrate; 111-grooves; 130-base chipset; 131-a control chip; 133-a first substrate chip; 135-a second base chip; 137-third base chip; 140-a plastic package body; 150-a first stacked chip set; 151 — first stacked chip; 153-a first connection line; 160-a second stacked chipset; 161-a second stacked chip; 163-second connection line; 170-a third stacked chipset; 171-a third stacked chip; 173-third connecting line; 180-a fourth stacked chipset; 181-fourth stacked chip; 183-fourth connecting line; 190-middle stacked chipset; 191-intermediate laminated chip; 193-first structural chip; 195-a second structural chip; 197-a third structural chip; 199-stacked bond wires.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships conventionally put on the products of the present invention when used, and are only used for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," "mounted," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the prior art, the inventor researches and discovers that the following chip stacking methods are generally adopted, 1, the chips are obliquely mounted by adopting the existing stack-die technology, the longer the chip wire bonding at the top layer is, the more difficult the control is, the wire bonding is unstable (bridging/breaking) easily caused, and the product packaging size is large. 2. By adopting the existing FOW stacking technology, stacking is carried out through a FOW (on-line circulation) film, after the chips are stacked, when the chips are wire-bonded to the top stacked chips, the longer the wire-bonding is, the more difficult the control is, the instable the wire-bonding (bridging/wire breaking) is easily caused, and the product packaging size is large. 3. The chip is obliquely mounted left and right by adopting the existing staggered laminated packaging technology, the chip is more overlapped and higher, the inclination of the left chip and the right chip is larger, and the bottom layer structure of the chip is more unstable, so that the structure of the stacked chip is collapsed or collapsed, and the product is damaged.
That is to say, the adoption of the FOW stacking technology/stack-die technology in the prior art can result in a large product packaging size, a small number of stacked chips in a unit volume, and unstable routing, while the adoption of the staggered stacking packaging technology can easily result in an unstable stacking structure, even influence the packaging quality. The multilayer chip stacking and packaging structure provided by the invention can solve the problems, and has the advantages of large stacking quantity, small packaging size, stable structure, difficulty in damage, good product quality and high yield.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. Features in the embodiments described below may be combined with each other without conflict.
First embodiment
Referring to fig. 1 and fig. 2 in combination, the present embodiment provides a multi-chip stacked package structure 100, which combines a left-side staggered stacked structure, a middle stacked structure, and a right-side staggered stacked structure, so that chips can be stacked simultaneously, the structure is firmer, a greater number of chips can be stacked, and the problem that the product quality is affected due to the unstable structure in the conventional stacked technology is avoided.
The multi-chip stacked package structure 100 provided by the present embodiment includes a substrate 110, a base chip set 130 stacked on the substrate 110, a first stacked chip set 150 stacked on the left side of the base chip set 130 and inclined to the left in a step shape, a second stacked chip set 160 stacked on the first stacked chip set 150 and inclined to the right in a step shape, a third stacked chip set 170 stacked on the right side of the base chip set 130 and inclined to the right in a step shape, a fourth stacked chip set 180 stacked on the third stacked chip set 170 and inclined to the left in a step shape, and a middle stacked chip set 190 stacked in the middle of the base chip set 130; the second stacked chipset 160 is partially stacked on the left side of the middle stacked chipset 190, and the fourth stacked chipset 180 is partially stacked on the right side of the middle stacked chipset 190.
In this embodiment, the base chipset 130, the first stacked chipset 150, the second stacked chipset 160, the third stacked chipset 170, the fourth stacked chipset 180 and the middle stacked chipset 190 are composed of at least two sub-chips, and by adopting the left-side staggered stacked structure, the middle stacked structure and the right-side staggered stacked structure, a plurality of chips can be stacked simultaneously, and are overlapped with each other, so that the structure is firmer, more chips can be stacked, and the problem that the product quality is influenced by the structural instability in the conventional stacked technology is avoided. Compared with the prior art, the package structure provided by the embodiment has a smaller package size under the condition of the same stacking number, and can stack more chips under the condition of the same package size.
In the present embodiment, the multi-chip stacked package structure 100 further includes a plastic package body 140, and the plastic package body 140 covers the base chip set 130, the first stacked chip set 150, the second stacked chip set 160, the third stacked chip set 170, the fourth stacked chip set 180, and the middle stacked chip set 190. Specifically, the stacked chips are protected by the plastic package body 140, and the plastic package body 140 is arranged, so that the stacked structure can be effectively protected, stable support is provided, and subsequent packaging actions are facilitated.
It should be noted that, in the present embodiment, the left side and the right side refer to the left side and the right side in the drawing, which indicate a relative direction, and do not indicate an absolute direction, and the left inclination refers to the left inclination of the stepped structure formed by the first stacked chip set 150 or the fourth stacked chip set 180, and the right inclination refers to the right inclination of the stepped structure formed by the second stacked chip set 160 or the third stacked chip set 170.
In this embodiment, the substrate 110 is provided with a groove 111, the base chip set 130 is partially accommodated in the groove 111, and the groove 111 is filled with glue. By placing part of the substrate chip group 130 in the groove 111 on the substrate 110, the whole chip structure can sink, the routing distance of the chip is effectively reduced, the problem that routing is unstable due to a traditional lamination process is solved, and the product yield is improved.
It should be noted that, in the stacking process mentioned in this embodiment, all the stacking processes are performed by attaching the FOW film during actual stacking, so as to ensure the stability of the structure. Of course, the chips can be mounted by other methods such as silver paste or heat-resistant glue, but any mounting method that can realize the mutual bonding and fixation of the chips is within the protection scope of the present invention.
The middle stacked chip set 190 includes a stacked chip unit and a structural chip unit, the stacked chip unit includes a plurality of stacked chips vertically stacked on the base chip set 130 in sequence, the structural chip unit is stacked on the stacked chip unit and extends to the left and right, the second stacked chip set 160 is partially stacked on the left side of the structural chip unit, and the fourth stacked chip set 180 is partially stacked on the right side of the structural chip unit.
In the present embodiment, the stacked chip units are disposed between the first stacked chip group 150 and the third stacked chip group 170, and a plurality of stacked chips are stacked layer by layer and vertically stacked upward to form a stacked structure, and the structural chip units are stacked on the topmost stacked chip. It should be noted that the height of the structural chip unit compared to the substrate 110 is greater than the height of the first stacked chip set 150 and the third stacked chip set 170 compared to the substrate 110, so that the second stacked chip set 160 and the fourth stacked chip set 180 can be partially stacked on the left and right sides of the structural chip unit, and the structural chip unit supports and limits the second stacked chip set 160 and the fourth stacked chip set 180.
The structural chip unit comprises a first structural chip 193, a second structural chip 195 and a third structural chip 197, the first structural chip 193 is stacked on the laminated chip unit, the second structural chip 195 and the third structural chip 197 are stacked on the first structural chip 193 side by side, the first structural chip 193, the second structural chip 195 and the third structural chip 197 form a T-shaped structure, so that the second structural chip 195 and the third structural chip 197 respectively extend towards the left side and the right side, the second stacked chip group 160 is partially stacked on the second structural chip 195, and the fourth stacked chip group 180 is partially stacked on the third structural chip 197.
It should be noted that, in the present embodiment, the first structural chip 193, the second structural chip 195 and the third structural chip 197 form a T-shaped structure, which means that the second structural chip 195 is stacked on the left side of the first structural chip 193 and protrudes to the left, and the third structural chip 197 is stacked on the right side of the second structural chip 195 and protrudes to the right, so as to form an overall structure substantially in a T shape.
In this embodiment, the first structural chip 193, the second structural chip 195 and the third structural chip 197 are dummy chips, which only serve as structural supports and are not electrically connected to other chips.
In the present embodiment, each stacked chip is connected to the first stacked chip set 150 and the third stacked chip set 170 through the stacked connection lines 199 on both sides.
It should be noted that, in this embodiment, the second structural chip 195 and the third structural chip 197 respectively bear a part of the second stacked chip set 160 and a part of the fourth stacked chip set 180, and a bearing force is exerted on the middle stacked chip 191 through the first structural chip 193, wherein the first structural chip 193, the second structural chip 195 and the third structural chip 197 together form a T-shaped structure, so that a bottom structure of a bottom layer of a misaligned chip is added, and more chips on the second stacked chip set 160 and the fourth stacked chip set 180 are stacked upward.
In another preferred embodiment of the present invention, in order to ensure the stability of the T-shaped structure, a top chip may be stacked on the second structural chip 195 and the third structural chip 197, and the top chips are stacked on the right side of the second structural chip 195 and the left side of the third structural chip 197, respectively, so that the T-shaped structure is stressed more uniformly and stably.
The first stacked chip group 150 includes a plurality of first stacked chips 151 stacked layer by layer in a stepped manner to the left, and each first stacked chip 151 is electrically connected to an adjacent first stacked chip 151 or the base chip group 130 through a first connection line 153. Specifically, the bottom first stacked chip 151 is electrically connected to the base chip group 130 through the first connection line 153, and the other first stacked chips 151 are electrically connected to the next first stacked chip 151 through the first connection line 153.
The second stacked chip set 160 includes second stacked chips 161 stacked one by one rightward in a stepwise manner, each of the second stacked chips 161 being electrically connected to an adjacent second stacked chip 161 or the first stacked chip 151 by a second connection line 163, wherein one of the second stacked chips 161 is partially stacked on the left side of the intermediate stacked chip set 190. Specifically, the second stacked chip 161 at the bottom is electrically connected to the first stacked chip 151 at the top by the second connection line 163, and the other second stacked chips 161 are electrically connected to the second stacked chip 161 at the next layer by the second connection line 163, while the right side of one second stacked chip 161 at the middle layer is stacked on the left side of the second structural chip 195.
The third stacked chip set 170 includes a plurality of third stacked chips 171 stacked one by one rightward in a stepwise manner, and each of the third stacked chips 171 is electrically connected to an adjacent third stacked chip 171 or the base chip set 130 through a third connection line 173. Specifically, the bottom third stacked chip 171 is electrically connected to the base chipset 130 through a third connecting line 173, and all other third stacked chips 171 are electrically connected to the next third stacked chip 171 through the third connecting line 173.
The fourth stacked chip set 180 includes a plurality of fourth stacked chips 181 stacked layer by layer in a staircase pattern to the left, each of the fourth stacked chips 181 is electrically connected to an adjacent fourth stacked chip 181 or third stacked chip 171 by a fourth connection line 183, wherein one of the fourth stacked chips 181 is partially stacked on the right side of the intermediate stacked chip set 190. Specifically, the bottom fourth stacked chip 181 is electrically connected to the top third stacked chip 171 through a fourth connection line 183, and the other fourth stacked chips 181 are electrically connected to the next fourth pair of stacked chips through the fourth connection line 183, while the left side of one fourth stacked chip 181 located in the middle layer is stacked on the right side of the third structural chip 197.
Specifically, the number of layers of the intermediate laminated chip 191 in the present embodiment is the same as the number of layers of the first and third stacked chips 151 and 171, thereby enabling the second and fourth stacked chips 161 and 181 of the intermediate layer to be stacked on the second and third structural chips 195 and 197, respectively. In addition, the stacked connection lines 199 on both sides of the middle stacked chip 191 on the middle and top sides are connected to the first stacked chip 151 or the third stacked chip 171 on the next layer, respectively, and the stacked connection lines 199 on both sides of the middle stacked chip 191 on the bottom side are connected to the base chipset.
It should be noted that, in the present embodiment, the plurality of first stacked chips 151 gradually increases from layer to layer in a stepped manner to the left, which means that the first stacked chip 151 at the bottom is stacked on the left side of the base chip set 130, and all the other first stacked chips 151 are stacked on the left side of the first stacked chip 151 at the next layer, so that the whole is inclined to the left, and a stepped structure is formed at the right side. The second stacked chip 161, the third stacked chip 171, and the fourth stacked chip 181 form a stepped structure similar to the first stacked chip 151 in principle.
The base chip set 130 includes a control chip 131, a first base chip 133, a second base chip 135 and a third base chip 137, the control chip 131 is attached to the substrate 110, the first base chip 133 is stacked on the control chip 131, the second base chip 135 is stacked on the left half of the first base chip 133, the third base chip 137 is stacked on the right half of the first base chip 133, the first stacked chip set 150 is stacked on the left half of the second base chip 135, the third stacked chip set 170 is stacked on the right half of the third base chip 137, and the middle stacked chip set 190 is stacked on the right half of the second base chip 135 and the left half of the third base chip 137.
In this embodiment, the control chip 131, the first base chip 133, the second base chip 135 and the third base chip 137 are all connected to the substrate 110 through a connection line to realize electrical connection, and in addition, the second base chip 135 and the third base chip 137 are also connected to the first base chip 133 through a connection line, so that the second base chip 135 and the third base chip 137 are electrically connected to the first base chip 133.
It should be noted that the connecting wires mentioned in the present embodiment refer to conventional bonding wires, such as gold wires, copper wires, or alloy wires.
In the present embodiment, the control chip 131 is attached to the bottom wall of the recess 111, the first base chip 133 is stacked on the control chip 131, and the height of the first base chip 133 is equal to the depth of the recess 111, so that the first base chip 133 is flush with the surface of the substrate 110 around the recess 111, the right bottom of the second base chip 135 is stacked on the left side of the first base chip 133, the left bottom of the second base chip 135 is stacked on the surface of the substrate 110 on the left side of the recess 111, the left bottom of the third base chip 137 is stacked on the right side of the first base chip 133, and the right bottom of the third base chip 137 is stacked on the surface of the substrate 110 on the right side of the recess 111.
In this embodiment, the groove 111 is filled with glue, and a glue layer is formed, where the thickness of the glue layer is the same as the depth of the groove 111, so that the glue layer is flush with the surface of the substrate 110 around the groove 111, and when stacking, the bottoms of the second base chip 135 and the third base chip 137 can also be abutted against the glue layer, and the glue layer can also play a certain role in bearing.
It should be noted that, in this embodiment, the first base chip 133, the second base chip 135, the third base chip 137, the first stacked chip 151, the second stacked chip 161, the third stacked chip 171, the fourth stacked chip 181, and the intermediate stacked chip 191 are all memory chips, and the stacking number is increased or the stacking height is reduced through the whole stacking structure, so that the package size is reduced, the product packaging process is reduced, the packaging material is reduced, and the packaging cost is reduced. Of course, the chip may be other types of chips, such as a processor or an LED chip, and is not limited in detail herein.
It should be noted that, in the present embodiment, the number of stacked layers of the first stacked chip 151, the second stacked chip 161, the third stacked chip 171, the fourth stacked chip 181, and the intermediate stacked chip 191 may be set according to actual requirements, and the illustration of the present embodiment is merely an example, and the number of stacked layers is not limited.
In summary, the present embodiment provides a multilayer chip stacking structure, which has a stable structure, can greatly increase the stacking number, reduce the package size, and effectively reduce the chip wire bonding distance, thereby solving the problem of unstable wire bonding (bridging/wire breaking) easily caused by the conventional lamination process, improving the product yield, realizing simultaneous stacking of chips, reducing the product packaging process, reducing the packaging material, and reducing the packaging cost.
Second embodiment
Referring to fig. 3, the present embodiment provides a multilayer chip stack packaging method for molding the multilayer chip stack structure provided by the first embodiment, the method comprising the steps of:
s1: the base chipset 130 is stacked on the substrate 110.
Specifically, the base chip set 130 includes a control chip 131, a first base chip 133, a second base chip 135 and a third base chip 137, the control chip 131 is attached to the bottom wall of the groove 111 on the substrate 110 by using the FOW film to reduce the chip wire bonding distance, and the control chip 131 is attached to the FOW film to achieve chip stacking, wherein the stacking height of the chip stacking is consistent with the depth of the groove 111 on the substrate 110. The second base chip 135 and the third base chip 137 are stacked on the first base chip 133.
Operations such as wire bonding, dispensing, baking and the like are inserted in the process of stacking the substrate chipset 130, which can be referred to in the following description.
S2: the first stacked chip set 150 is stacked on the left side of the base chip set 130 in a step-like manner.
Specifically, the first stacked chip set 150 includes a plurality of first stacked chips 151, and the plurality of first stacked chips 151 are stacked on the left side of the second base chip 135 in a step-like manner by using the FOW film, and then wire bonding, baking, and the like are completed.
S3: the third stacked chip set 170 is stacked to be inclined to the right in a step shape on the right side of the base chip set 130.
Specifically, the third stacked chip set 170 includes a plurality of third stacked chips 171, and the plurality of third stacked chips 171 are stacked rightward on the right side of the third base chip 137 in a step shape by using the FOW film, and then wire bonding, baking, and the like are completed.
S4: the middle laminate chipset 190 is stacked in the middle of the base chipset 130.
Specifically, the middle stacked chip set 190 includes a stacked chip unit including a plurality of stacked chips and a structural chip unit including a first structural chip 193, a second structural chip 195 and a third structural chip 197, the plurality of stacked chips are stacked on the right side of the first base chip 133 and the left side of the second base chip 135 layer by layer using a FOW film, the first structural chip 193 is stacked on the top stacked chip, and the second structural chip 195 and the third structural chip 197 are stacked on the left side of the first structural chip 193 and the right side of the first structural chip 193, respectively.
During the process of stacking the middle stacked chip set 190, operations such as wire bonding and baking are performed, which can be referred to in the following description.
S5: the second stacked chip set 160 is stacked on the first stacked chip set 150 in a step-like manner with a right slant.
Specifically, the second stacked chip set 160 includes a plurality of second stacked chips 161, and the plurality of second stacked chips 161 are stacked right on the right side of the top first stacked chip 151 in a step shape by using the FOW film, and the middle second stacked chip 161 is stacked on the left side of the second structural chip 195, and then wire bonding, baking and other operations are completed.
S6: the fourth stacked chip set 180 is stacked on the third stacked chip set 170 in a staircase shape inclined to the left.
Specifically, the fourth stacked chip set 180 includes a plurality of fourth stacked chips 181, and the plurality of fourth stacked chips 181 are stacked left on the top of the third stacked chip 171 in a step shape by using the FOW film, and the middle of the fourth stacked chip 181 is stacked on the right of the third structural chip 197, and then the operations such as wire bonding and baking are completed.
It should be noted that the second stacked chipset 160 is partially stacked on the left side of the middle stacked chipset 190, and the fourth stacked chipset 180 is partially stacked on the right side of the middle stacked chipset 190. Specifically, the second stacked chip 161 of the intermediate layer is stacked on the left side of the second structural chip 195, and the fourth stacked chip 181 of the intermediate layer is stacked on the right side of the third structural chip 197.
It should be noted that in the present embodiment, the first base chip 133, the second base chip 135, the third base chip 137, the first stacked chip 151, the second stacked chip 161, the third stacked chip 171, the fourth stacked chip 181, and the intermediate stacked chip 191 are all memory chips, and when the memory chips are actually stacked, the steps S2, S3, and S4 may be performed simultaneously or sequentially, and no actual sequence thereof is included, and the following detailed description of the entire stacking process may be specifically referred to.
In practical operation, the multilayer chip stacking and packaging method provided by the embodiment includes the steps of wafer cutting, mounting the control chip 131, baking, routing, mounting the first substrate chip 133, routing, dispensing, baking, mounting the second substrate chip 135, the third substrate chip 137, the plurality of first stacked chips 151 and the plurality of second stacked chips 161, baking, routing, mounting the intermediate stacked chip 191, baking, routing, mounting the first structure chip 193, the second structure chip 195 and the third structure chip 197, mounting the plurality of second stacked chips 161 and the plurality of fourth stacked chips 181, baking, routing, plastic packaging, printing, cutting and packaging, which are specifically as follows.
Wafer cleavage: and cutting the whole wafer into single wafers along the cutting path by using laser/diamond, and attaching the FOW film to the back surface of the chip.
2. Chip mounting: the FOW film is used to mount the control chip 131 on the bottom surface of the groove 111 on the substrate 110, so as to reduce the chip wire bonding distance.
3. Baking: the FOW film is cured by baking to fix the control chip 131 on the bottom surface of the groove 111 of the substrate 110.
4. Routing: the chip is connected with the substrate 110 by a wire bonding method by using copper wires, alloy wires and gold wires.
5. Mounting the first base chip 133: the FOW film chip is stacked on the control chip 131 to achieve chip stacking, and the stacking height of the FOW film chip needs to be consistent with the height of the groove 111 on the substrate 110.
6. Routing: the first base chip 133 is connected to the substrate 110 by a wire bonding method using copper/alloy/gold wires.
7. Dispensing: glue is filled in the groove 111 of the substrate 110, so that the glue surface is consistent with the surface of the substrate 110 around the groove 111, and the surface mounting horizontal plane is completed.
8. Baking: and glue is cured by a baking mode, so that the wire arc is protected and the surface mounting horizontal plane is completed.
9. Mounting the second base chip 135, the third base chip 137, the plurality of first stacked chips 151, and the plurality of second stacked chips 161: mounting the second base die 135 and the plurality of first stacked dies 151 with the FOW film, wherein the second base die 135 is mounted on the left side of the first base die 133 and the plurality of first stacked dies 151 are mounted on the left side to achieve a left side offset stack, and mounting the third base die 137 and the plurality of second stacked dies 161 with the FOW film, wherein the third base die 137 is mounted on the right side of the first base die 133 and the plurality of second stacked dies 161 are mounted on the right side to achieve a right side offset stack. The intermediate laminated chip 191 of the bottom side is then attached to the second base chip 135 and the third base chip 137.
10. Baking: and curing the FOW film at the bottom of the chip in a baking mode to fix the chip on the surface of the chip.
11. Routing: the connection of the chip circuits is achieved by means of copper wires, alloy wires and gold wires in a routing mode.
12. Mounting the middle laminated chip 191: the middle laminated chip 191 in the middle is attached to the middle laminated chip 191 on the bottom side by using the FOW film, so that the FOW chip middle lamination is realized.
13. Baking: and curing the FOW film at the bottom of the chip in a baking mode to fix the chip on the surface of the chip.
14. Routing: and the connection of the chip circuit is achieved by a copper wire/alloy wire/gold wire in a routing mode.
15. Mount top-side intermediate laminated chip 191: the middle laminated chip 191 on the top side is attached on the middle laminated chip 191 on the middle side by using the FOW film, so that the FOW chip middle lamination is realized.
16. Baking: and curing the FOW film at the bottom of the chip in a baking mode to fix the chip on the surface of the chip.
17. Routing: and the connection of the chip circuit is achieved by a copper wire/alloy wire/gold wire in a routing mode.
18. Mounting a dummy chip: the first structural chip 193, the second structural chip 195 and the third structural chip 197 are attached on the middle laminated chip 191 on the top side by using the FOW film, so that a T-shaped structure is realized, and a staggered chip laminated bottom structure is increased.
19. Mounting the plurality of second stacked chips 161 and the plurality of fourth stacked chips 181: a plurality of second stacked chips 161 are attached to the right side of the first stacked chip 151 on the top side using the FOW film to realize a right side offset lamination, and a plurality of fourth stacked chips 181 are attached to the left side of the third stacked chip 171 on the top side using the FOW film to realize a left side offset lamination.
20. Baking: and curing the FOW film at the bottom of the chip in a baking mode to fix the chip on the surface of the chip.
21. Routing: and the connection of the chip circuit is achieved by a copper wire/alloy wire/gold wire in a routing mode.
22. Plastic packaging: and protecting the stacked chips by using a plastic packaging material.
23. Printing: the required characters are engraved on the surface of the plastic package body 140 by using laser.
24. Cutting: and cutting the plastic-sealed product into single pieces by using a cutting knife.
Package: and (4) putting the cut single products into a Tray, and packaging and delivering the products out of the warehouse.
The embodiment provides a multilayer chip stacking and packaging method, the control chip 131 is placed in the groove 111 at the bottom of the substrate 110, so that the chip routing distance can be effectively reduced, the problem of unstable routing (bridging/breaking) easily caused by the traditional lamination process is solved, and the product yield is improved; by combining the left-side staggered laminated structure, the middle laminated structure and the right-side staggered laminated structure, the chips can be simultaneously stacked, the structure is firmer, the problems that the stacked chip structure collapses/collapses and the product is damaged due to the fact that stacked chips are attached in a left-right inclined mode in the traditional laminated technology, the chip bottom layer structure is unstable when the left-right chip inclination is larger when the stacked chips are stacked higher are solved, and the product yield and the number of stacked layers are improved; through adopting dummy chip structure to constitute T word structure, its function is for increasing dislocation chip stromatolite bottom structure, realizes that more chips upwards pile up, adopts novel stacked structure, can realize that the chip piles up simultaneously, reduces the product encapsulation flow to reduce packaging material, reduce the encapsulation cost.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A multi-layer chip stack package structure, comprising:
a substrate;
a base chip set stacked on the substrate;
a first stacked chip group stacked on the left side of the base chip group and inclined to the left in a step shape;
a second stacked chip group stacked on the first stacked chip group and inclined to the right in a step shape;
a third stacked chip group stacked on the right side of the substrate chip group and inclined towards the right in a step shape;
a fourth stacked chip set stacked on the third stacked chip set and inclined to the left in a stair shape;
and an intermediate laminated chip set stacked in the middle of the base chip set;
wherein the second stacked chipset portion is stacked on a left side of the middle stacked chipset and the fourth stacked chipset portion is stacked on a right side of the middle stacked chipset.
2. The stacked multi-chip package structure of claim 1, wherein the middle stacked chip set comprises a stacked chip unit and a structural chip unit, the stacked chip unit comprises a plurality of stacked chips vertically stacked on the base chip set in sequence, the structural chip unit is stacked on the stacked chip unit and protrudes to both sides, the second stacked chip set is partially stacked on the left side of the structural chip unit, and the fourth stacked chip set is partially stacked on the right side of the structural chip unit.
3. The multi-layered chip stacking and packaging structure of claim 2, wherein the structural chip unit comprises a first structural chip, a second structural chip and a third structural chip, the first structural chip is stacked on the stacked chip unit, the second structural chip and the third structural chip are stacked side by side on the first structural chip, and the first structural chip, the second structural chip and the third structural chip form a T-shaped structure, such that the second structural chip and the third structural chip respectively protrude towards two sides, the second stacked chip set is partially stacked on the second structural chip, and the fourth stacked chip set is partially stacked on the third structural chip.
4. The multi-layered chip stacking and packaging structure of claim 2, wherein each of the stacked chips is connected to the first stacked chip set and the third stacked chip set respectively by a stack connection line on both sides.
5. The multi-layered chip stacked package structure of claim 1, wherein the first stacked chip group comprises a plurality of first stacked chips stacked layer by layer in a staircase manner to the left, each of the first stacked chips being electrically connected to the adjacent first stacked chip or the base chip group by a first connection line; the second stacked chip group comprises a plurality of second stacked chips stacked layer by layer rightwards in a stepped manner, each second stacked chip is electrically connected with the adjacent second stacked chip or the first stacked chip through a second connecting line, and one second stacked chip is partially stacked on the left side of the middle stacked chip group.
6. The multi-layered chip stacking package structure of claim 1 or 4, wherein the third stacked chip set comprises a plurality of third stacked chips stacked layer by layer rightward in a staircase manner, each of the third stacked chips being electrically connected to the adjacent third stacked chip or the base chip set by a third connection line; the fourth stacked chip group comprises a plurality of fourth stacked chips stacked layer by layer leftwards in a stepped manner, each fourth stacked chip is electrically connected with the adjacent fourth stacked chip or the third stacked chip through a fourth connecting line, and one fourth stacked chip is partially stacked on the right side of the middle stacked chip group.
7. The multi-layered chip stacking and packaging structure of claim 1, wherein the base chip set comprises a control chip, a first base chip, a second base chip and a third base chip, the control chip is attached to the substrate, the first base chip is stacked on the control chip, the second base chip is stacked on a left half of the first base chip, the third base chip is stacked on a right half of the first base chip, the first stacked chip set is stacked on a left half of the second base chip, the third stacked chip set is stacked on a right half of the third base chip, and the middle stacked chip set is stacked on a right half of the second base chip and a left half of the third base chip.
8. The stacked package structure of claim 1, wherein the substrate has a recess, and the base chipset is partially received in the recess, and the recess is filled with glue.
9. The stacked multi-die package structure of claim 1, further comprising a molding compound, the molding compound being encapsulated outside the base die set, the first stacked die set, the second stacked die set, the third stacked die set, the fourth stacked die set, and the middle stacked die set.
10. A multilayer chip stack packaging method is characterized by comprising the following steps:
stacking the base chip set on the substrate;
stacking the middle laminated chip set in the middle of the substrate chip set;
stacking a first stacked chip set on the left side of the base chip set in a manner of inclining towards the left in a step shape;
stacking a second stacked chip set on the first stacked chip set in a step shape and inclining to the right;
stacking a third stacked chip set on the right side of the substrate chip set in a step shape and inclining rightwards;
stacking a fourth stacked chip set on the third stacked chip set in a step shape and inclining to the left;
wherein the second stacked chipset portion is stacked on a left side of the middle stacked chipset and the fourth stacked chipset portion is stacked on a right side of the middle stacked chipset.
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| CN102629604B (en) * | 2012-04-06 | 2014-09-03 | 天水华天科技股份有限公司 | Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package |
| KR102190382B1 (en) * | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
| KR101687706B1 (en) * | 2015-04-29 | 2016-12-19 | 주식회사 에스에프에이반도체 | stacking method of thin type chip |
| KR20170099046A (en) * | 2016-02-23 | 2017-08-31 | 삼성전자주식회사 | Semiconductor package |
| US11133284B2 (en) * | 2018-12-26 | 2021-09-28 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device |
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