CN111541391A - Cross double-PV-source input-stage-connected multi-level inverter circuit - Google Patents
Cross double-PV-source input-stage-connected multi-level inverter circuit Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/49—Combination of the output voltage waveforms of a plurality of converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/56—Power conversion systems, e.g. maximum power point trackers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a cross double-PV-source input-stage-connected multi-level inverter circuit, which adopts nine switching tubes to be connected to form a cross double-PV-source input-stage-connected multi-level inverter circuit topological structure, does not need additional capacitance, can be compatible with simultaneous access of various new energy sources, can obtain high output voltage and output power through the cascade connection of a single topological structure, can obviously improve the total harmonic distortion, is suitable for the mixed use of various new energy power generation systems, and has simple structure. The cascade connection of a plurality of multi-level inverter circuits is adopted, the output level number of the multi-level inverter circuits and the requirements of high-power application occasions are expanded, the power level is improved, the total harmonic distortion is obviously reduced, the reliability of the system is improved, and the number and the size of filter elements are reduced.
Description
Technical Field
The invention belongs to the field of power electronic research, and particularly relates to a cross double-PV-source input-stage-connected multi-level inverter circuit.
Background
In recent years, multi-level inverters (MLIs) have been favored by many scholars, and have attracted much attention in the industrial field.
A series of advantages of MLIs are attributed to its own features: the reduction of Total Harmonic Distortion (THD) and the more excellent electromagnetic compatibility characteristics of the multi-level operation, which in turn, affect the whole system, thus improving the efficiency and stability of the whole system. Meanwhile, the multilevel operation of the multilevel inverter can reduce the stress on the switching devices, thereby reducing the switching loss of the switching devices and optimizing the overall efficiency characteristic. However, the multi-level inverter adopted in the new energy application fields of wind power generation, photovoltaic power generation and the like at present adopts a single-topology module structure, cannot adapt to the reliability of new energy power generation systems of wind power generation, photovoltaic power generation and the like, adopts a multi-topology structure, needs additional capacitance circuit assistance, and is complex in structure and poor in stability.
Disclosure of Invention
The invention aims to provide a cross double-PV-source input-stage cascade multilevel inverter circuit to overcome the defects of the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a cross double-PV-source input-stage-connected multi-level inverter circuit comprises a first switching tube Qa, a second switching tube Qb, a third switching tube Qc, a fourth switching tube Qd, a fifth switching tube Q1, a sixth switching tube Q2, a seventh switching tube Q3, an eighth switching tube Q4 and a ninth switching tube Q5;
the collector c of the fifth switching tube Q1, the emitter e of the sixth switching tube Q2, the collector c of the eighth switching tube Q4 and the collector c of the ninth switching tube Q5 are connected with a second direct current power supply Vdc2One connecting electrode of (1); the collector c of the seventh switching tube Q3, the emitter e of the third switching tube Qc and the emitter e of the fourth switching tube Qd are connected with a second direct current power supply Vdc2The other is connected with the electrode;
the emitter e of the fifth switching tube Q1, the collector c of the first switching tube Qa and the collector c of the second switching tube Qb are connected to a first direct current power supply Vdc1One connecting electrode of (1); the collector c of the sixth switching tube Q2 and the emitter e of the seventh switching tube Q3 are connected with a first direct current power supply Vdc1The other is connected with the electrode;
an emitter e of the first switching tube Qa, an emitter e of the eighth switching tube Q4 and a collector c of the third switching tube Qc are connected with the positive electrode of the output end; the emitter e of the second switch tube Qb, the emitter e of the ninth switch tube Q5 and the collector c of the fourth switch tube Qd are connected to the negative electrode of the output terminal.
Further, the first switch tube Qa, the second switch tube Qb, the third switch tube Qc, the fourth switch tube Qd, the fifth switch tube Q1, the sixth switch tube Q2 and the seventh switch tube Q3 are all IGBT field-effect transistors with a damping diode.
Further, the eighth switching transistor Q4 and the ninth switching transistor Q5 are N-type IGBT fets.
Furthermore, the cathode of the output end of one of the multi-level inverter circuits is connected with the anode of the output end of the other multi-level inverter circuit to form a cascade topology structure, the anode of the output end of one of the multi-level inverter circuits is the anode of the output end of the cascade topology structure, and the cathode of the output end of the other multi-level inverter circuit is the cathode of the output end of the cascade topology structure.
Furthermore, the negative electrodes of the output ends of the multi-level inverters are sequentially connected with the positive electrodes of the output ends to form a multi-stage cascade topology structure.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention relates to a cross double-PV-source input-stage-connected multi-level inverter circuit, which adopts nine switching tubes to be connected to form a cross double-PV-source input-stage-connected multi-level inverter circuit topological structure, does not need additional capacitors, can be compatible with simultaneous access of various new energy sources, can obtain high output voltage and output power by cascading a single topological structure, can obviously improve total harmonic distortion, is suitable for mixed use of various new energy power generation systems, and has a simple structure.
Furthermore, a plurality of multi-level inverter circuits are cascaded, the output level number of the multi-level inverter circuits and the requirements of high-power application occasions are expanded, the power level is improved, the total harmonic distortion is obviously reduced, the reliability of the system is improved, and the number and the size of filter elements are reduced.
Drawings
Fig. 1 is a circuit diagram of a multilevel inverter according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of different switch operation modes of the multilevel inverter circuit according to the embodiment of the invention.
FIG. 3 is a schematic diagram of sinusoidal pulse width modulation and corresponding switching tube gate drive signals used in an embodiment of the present invention.
Fig. 4 is a cascaded structure of two multilevel inverter circuit topology blocks in an embodiment of the invention.
Fig. 5 shows a control strategy under a cascade structure of two multilevel inverter circuit topology modules according to an embodiment of the present invention.
Fig. 6 is an output voltage waveform of an inverter simulated in MATLAB/SIMULINK software in an embodiment of the present invention.
Fig. 7 is a graph of simulated output voltage and current waveforms for a single inverter under resistive load in an embodiment of the present invention.
Fig. 8 is a voltage waveform simulated under the cascade structure in the embodiment of the present invention.
Fig. 9 shows simulated voltage and current waveforms of a resistor load in a cascade structure according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings:
as shown in fig. 1, a cross-coupled dual PV source input stage multilevel inverter circuit includes a first switch tube Qa, a second switch tube Qb, a third switch tube Qc, a fourth switch tube Qd, a fifth switch tube Q1, a sixth switch tube Q2, a seventh switch tube Q3, an eighth switch tube Q4, and a ninth switch tube Q5;
the collector c of the fifth switching tube Q1, the emitter e of the sixth switching tube Q2, the collector c of the eighth switching tube Q4 and the collector c of the ninth switching tube Q5 are connected with a second direct current power supply Vdc2One connecting electrode of (1); the collector c of the seventh switching tube Q3, the emitter e of the third switching tube Qc and the emitter e of the fourth switching tube Qd are connected with a second direct current power supply Vdc2The other is connected with the electrode;
the emitter e of the fifth switching tube Q1, the collector c of the first switching tube Qa and the collector c of the second switching tube Qb are connected to a first direct current power supply Vdc1One connecting electrode of (1); the collector c of the sixth switching tube Q2 and the emitter e of the seventh switching tube Q3 are connected with a first direct current power supply Vdc1The other is connected with the electrode;
an emitter e of the first switching tube Qa, an emitter e of the eighth switching tube Q4 and a collector c of the third switching tube Qc are connected with the positive electrode of the output end; the emitter e of the second switch tube Qb, the emitter e of the ninth switch tube Q5 and the collector c of the fourth switch tube Qd are connected to the negative electrode of the output terminal.
The first switch tube Qa, the second switch tube Qb, the third switch tube Qc, the fourth switch tube Qd, the fifth switch tube Q1, the sixth switch tube Q2 and the seventh switch tube Q3 are all IGBT field effect tubes with damping diodes; the eighth switch tube Q4 and the ninth switch tube Q5 are N-type IGBT field effect tubes.
Example (b): as shown in fig. 1, a first dc power supply Vdc1A second DC power supply V for outputting a level VDCdc2Is 3-level output, namely Vdc 1-Vdc, Vdc 2-3 Vdc; a first switch tube Qa, a second switch tube Qb, a third switch tube Qc, and a fourth switch tube QdThe 9-switch-9 level-cross double-PV-source input non-isolated cascade multilevel inverter circuit consists of a fifth switch tube Q1, a sixth switch tube Q2, a seventh switch tube Q3, an eighth switch tube Q4 and a ninth switch tube Q5, two different PV sources (energy sources) are connected to the circuit and can be compatible with various different types of new energy sources, and meanwhile, different output levels can be obtained by inputting different new energy sources. The two input dc power sources are connected to two different renewable energy sources, as shown in fig. 2, for different switching modes of the multilevel inverter circuit and the output levels corresponding to the switching modes are high and low.
As shown in fig. 2(a) and 2(b), the first switching tube Qa and the second switching tube Qb are turned on simultaneously or the third switching tube Qc and the fourth switching tube Qd are turned on simultaneously, and the output of the multilevel inverter circuit is 0; the output of the multi-level inverter circuit is simultaneously turned on and short-circuited by the first and second switching tubes Qa and Qb, or by the third and fourth switching tubes Qc and Qd.
As shown in fig. 2(c), the first switch tube Qa, the seventh switch tube Q3 and the fourth switch tube Qd are turned on simultaneously, and the other switch tubes are turned off simultaneously, so that the output of the multilevel inverter circuit is + Vdc;
as shown in fig. 2(d), the seventh switch Q3, the second switch Qb and the third switch Qc are turned on simultaneously, and the other switches are turned off simultaneously, so that the output of the multilevel inverter circuit is-Vdc;
as shown in fig. 2(e), the seventh switch Q3, the eighth switch Q4 and the second switch Qb are turned on simultaneously, and the other switches are turned off simultaneously, so that the output of the multi-level inverter circuit is +2 Vdc;
as shown in fig. 2(f), the seventh switch Q3, the ninth switch Q5 and the first switch Qa are turned on simultaneously, and the other switches are turned off simultaneously, so that the output of the multilevel inverter circuit is-2 Vdc;
as shown in fig. 2(g), the first switch tube Qa, the fifth switch tube Q1 and the fourth switch tube Qd are turned on simultaneously, and the other switch tubes are turned off simultaneously, at this time, the output of the multi-level inverter circuit is +3 Vdc;
as shown in fig. 2(h), the fifth switch tube Q1, the second switch tube Qb and the third switch tube Qc are turned on simultaneously, and the other switch tubes are turned off simultaneously, at this time, the output of the multilevel inverter circuit is-3 Vdc;
as shown in fig. 2(i), the sixth switching tube Q2, the first switching tube Qa and the fourth switching tube Qd are turned on simultaneously, and the other switching tubes are turned off simultaneously, so that the output of the multilevel inverter circuit is +4 Vdc;
as shown in fig. 2(j), the sixth switching tube Q2, the third switching tube Qc and the second switching tube Qb are turned on simultaneously, and the other switching tubes are turned off simultaneously, so that the output of the multilevel inverter circuit is-4 Vdc.
With such a switching strategy nine different levels, namely +4Vdc, ± 3Vdc, ± 2Vdc, ± Vdc and 0 levels, can be output.
The present application employs a Sinusoidal Pulse Width Modulation (SPWM) control technique for a multilevel inverter circuit to generate switching control pulses. SPWM requires 4 carrier reference signals Vcr 1-Vcr 4, as shown in FIG. 3. The intersections between the carrier signal and the reference signal generate the main switching functions (FA-FD) for synthesizing the corresponding output voltages according to the control scheme. A series of cross points produce 14 different operating cycles (p 1-p 14) representing different level traces of the output power; through simple logic operation, the switching pulse and the working period thereof are obtained. The specific control logic is as follows:
1)
S2＝(P4|P11)&F4
2)
7)
Sc＝(P10|P11|P12)|(P8|P14)&F1
8)
the associated reference signal, carrier signal waveform, primary switching function and one full cycle of switching pulses are shown in fig. 3.
The cascade use of a plurality of multi-level inverter circuits can improve the output voltage level and power level. The following section will illustrate the use of a cascade structure and its advantages, as exemplified by a two-stage cascade, the connection structure being shown in fig. 4, V11And V12A first direct current power supply and a second direct current power supply of the first multilevel inverter circuit Uint1, respectively; v21And V22A first direct current power supply and a second direct current power supply of a second multilevel inverter circuit Uint2, respectively; the negative electrode of the output end of the first multi-level inverter circuit Uint1 is connected with the positive electrode of the output end of the second multi-level inverter circuit Uint2, and a load RL is connected between the positive electrode of the output end of the first multi-level inverter circuit Uint1 and the negative electrode of the output end of the second multi-level inverter circuit Uint 2. In the structure shown in fig. 4, the lower cell (the second multi-level inverter circuit Uint2) uses fundamental frequency for output, so the output voltage generated by the lower cell (the second multi-level inverter circuit Uint2) will be nine levels of step-like voltage, and at the same time, the upper cell (the first multi-level inverter circuit Uint1) adopts higher switching frequency, and the control strategy is as shown in fig. 5, and in each level output period of the lower cell Unit2, the upper cell Unit1 will change eight different output levels and add to the output voltage of the lower cell Unit2, so that the output voltage is closer to an ideal sine. When asymmetric input sources are used as the inputs of the cascade devices (e.g., V21-7V 11, V22-7V 12), the total output voltage level is 73, when three stages are usedIn the case of the combined device, the output voltage level can be significantly increased to 649 level.
In order to prove the effectiveness of the topology structure of the 9 switch-9 level-crossing double-PV-source-input non-isolated cascade multi-level inverter, MATLAB/SIMULINK software is used for carrying out simulation analysis on the 9 switch-9 level-crossing double-PV-source-input non-isolated cascade multi-level inverter. Firstly, a single topological structure is verified, an R-L load is adopted in simulation, voltage waveforms and voltage-current time-domain waveforms of the single topological structure are respectively shown in FIGS. 6 and 7, and the output characteristics of the single topological structure are in accordance with expectations. And performing simulation of a two-stage cascade structure on the basis of a single-stage topological structure. Fig. 8 shows the voltage output waveforms and amplitudes of the upper and lower units in the two-stage cascade structure and the superimposed result, and fig. 9 shows the output voltage and output current waveforms of the load side, it can be observed that the smoothness of the output voltage is significantly improved, the simulation result meets the expected target, and the validity of the inventive 9-switch-9-level-cross double-PV-source input non-isolated cascade multilevel inverter topology structure is verified.
Claims (5)
1. A cross double-PV-source input-stage multi-level inverter circuit is characterized by comprising a first switch tube Qa, a second switch tube Qb, a third switch tube Qc, a fourth switch tube Qd, a fifth switch tube Q1, a sixth switch tube Q2, a seventh switch tube Q3, an eighth switch tube Q4 and a ninth switch tube Q5;
the collector c of the fifth switching tube Q1, the emitter e of the sixth switching tube Q2, the collector c of the eighth switching tube Q4 and the collector c of the ninth switching tube Q5 are connected with a second direct current power supply Vdc2One connecting electrode of (1); the collector c of the seventh switching tube Q3, the emitter e of the third switching tube Qc and the emitter e of the fourth switching tube Qd are connected with a second direct current power supply Vdc2The other is connected with the electrode;
the emitter e of the fifth switching tube Q1, the collector c of the first switching tube Qa and the collector c of the second switching tube Qb are connected to a first direct current power supply Vdc1One connecting electrode of (1); the collector c of the sixth switching tube Q2 and the emitter e of the seventh switching tube Q3 are connected with a first direct current power supply Vdc1The other is connected with the electrode;
an emitter e of the first switching tube Qa, an emitter e of the eighth switching tube Q4 and a collector c of the third switching tube Qc are connected with the positive electrode of the output end; the emitter e of the second switch tube Qb, the emitter e of the ninth switch tube Q5 and the collector c of the fourth switch tube Qd are connected to the negative electrode of the output terminal.
2. The cross-coupled dual-PV-source input-stage multilevel inverter circuit of claim 1, wherein the first switch tube Qa, the second switch tube Qb, the third switch tube Qc, the fourth switch tube Qd, the fifth switch tube Q1, the sixth switch tube Q2 and the seventh switch tube Q3 are all IGBT field effect tubes with damping diodes.
3. The cross-coupled double-PV-source input-stage multi-level inverter circuit as claimed in claim 1, wherein the eighth switching transistor Q4 and the ninth switching transistor Q5 are N-type IGBT fets.
4. The cross-coupled dual PV source input stage multi-level inverter circuit of claim 1, wherein the negative output terminals of one of the multi-level inverter circuits are connected to the positive output terminals of the other multi-level inverter circuit to form a cascade topology, wherein the positive output terminals of one of the multi-level inverter circuits are positive output terminals of the cascade topology, and the negative output terminals of the other multi-level inverter circuit are negative output terminals of the cascade topology.
5. The cross-coupled double-PV-source input-stage-coupled multilevel inverter circuit according to claim 1, wherein the negative poles of the output terminals of the multiple multilevel inverters are connected with the positive poles of the output terminals in sequence to form a multilevel cascade topology.
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