CN111525926A - Chopping frequency signal generating circuit - Google Patents
Chopping frequency signal generating circuit Download PDFInfo
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- CN111525926A CN111525926A CN202010324895.XA CN202010324895A CN111525926A CN 111525926 A CN111525926 A CN 111525926A CN 202010324895 A CN202010324895 A CN 202010324895A CN 111525926 A CN111525926 A CN 111525926A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
Abstract
The invention discloses a chopping frequency signal generating circuit which comprises a random chopping frequency generating circuit, a first addition operation circuit, a second addition operation circuit, a comparator, a frequency doubling circuit unit and a time delay circuit unit. The chopping frequency signal generating circuit can convert the square wave chopping frequency with fixed frequency into random chopping frequency, so that the chopping frequency is not fixed frequency energy and can be dispersed to each frequency point, and the noise of superposition in an ADC baseband is greatly reduced, so that the signal-to-noise ratio performance of a chopping stabilizing circuit under the sampling of a switched capacitor circuit can be effectively improved, and the signal-to-noise ratio performance of the whole analog front end until the output of the ADC can not be reduced.
Description
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to a method for processing a chopping frequency signal and a circuit for generating a chopping frequency signal, which are used in a chopping stabilization technology.
Background
The chopper stabilization technology modulates 1/f noise and circuit offset voltage in a circuit to high frequency through a signal modulation technology, and then filters the noise and the offset voltage through a subsequent low-pass filter, so that the low-noise electrical performance is obtained. The principle of the chopping stabilization technology is that an input signal is firstly modulated to a chopping frequency and then modulated back to a baseband frequency, offset voltage and 1/f noise are modulated to the position of the chopping frequency and the position of odd harmonic of the chopping frequency, and the odd components are filtered by a low-pass filter circuit of a subsequent circuit, so that the aim of low noise is fulfilled. As shown in fig. 1, explaining this principle from the time domain, the input signal is periodically inverted by a first pair of switches Φ 1, after passing through the amplifier, the inverted and amplified signal is re-inverted by a second pair of switches Φ 2, thus leaving only a dc signal, and the offset voltage is periodically modulated onto the square wave frequency and finally filtered out by the filter.
The common chopping frequency is a fixed frequency, and the frequency is far greater than the-3 dB frequency of the filter, and is generally 5-10 times. But the chopped residual signal of fixed frequency can be overlapped and mixed into the band by the subsequent ADC switch sampling circuit, and the signal-to-noise ratio is reduced. Therefore, it is necessary to design a chopper frequency signal generating circuit capable of improving the signal-to-noise ratio performance of a chopper stabilization circuit under the sampling of a switched capacitor circuit, so that the signal-to-noise ratio performance of the whole analog front end up to the output of an ADC is not reduced.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a chopping frequency signal generating circuit which can improve the signal-to-noise ratio performance of a chopping stabilizing circuit under the sampling of a switched capacitor circuit, so that the signal-to-noise ratio performance of the whole analog front end to the ADC output cannot be reduced.
In order to achieve the above objects and other related objects, the present invention provides the following technical solutions: a chopping frequency signal generating circuit comprises a random chopping frequency generating circuit, a first addition operation circuit, a second addition operation circuit, a comparator, a frequency doubling circuit unit and a time delay circuit unit; the random chopping frequency generating circuit is used for converting a square wave signal with fixed frequency into a random chopping frequency signal, the output end of the random chopping frequency generating circuit is connected with the first input end of the first addition operation circuit, the output end of the first addition operation circuit is connected with the first input end of the comparator, the second input end of the comparator is connected with the reference voltage, the comparator is used for comparing the input random chopping frequency signal with the reference voltage to obtain a random chopping frequency signal with increased or decreased frequency, the output end of the comparator is connected with the frequency doubling circuit unit, the frequency doubling circuit unit is used for performing frequency doubling processing on the random chopping frequency signal, the frequency doubling circuit unit is connected with the first input end of the second addition operation circuit, and the output end of the second addition operation circuit is connected with the time delay circuit unit, the delay circuit unit is used for carrying out delay processing on the random chopping frequency signal, and the output end of the delay circuit unit is connected with the second input end of the first addition operation circuit and the second input end of the second addition operation circuit.
Preferably, the delay circuit unit includes a first delay and a second delay, the first delay and the second delay are connected in series, an input end of the first delay is connected to the frequency multiplier circuit unit, and an output end of the second delay is connected to the first addition operation circuit and the second addition operation circuit.
Preferably, the digital signal processing circuit further comprises a mode selection circuit unit, the mode selection circuit unit comprises a chopping frequency signal input end, a clock signal input end and a mode signal selection end, the chopping frequency signal input end is connected with the output end of the comparator, the clock signal input end is connected with a clock input signal, the mode signal selection end is connected with the mode signal input circuit, and the mode selection circuit unit is used for setting a random variation range of a random chopping frequency signal.
The technical scheme has the following beneficial effects: the chopping frequency signal generating circuit can convert the square wave chopping frequency with fixed frequency into random chopping frequency, so that the chopping frequency is not fixed frequency energy and can be dispersed to each frequency point, and the noise of superposition in an ADC baseband is greatly reduced, so that the signal-to-noise ratio performance of a chopping stabilizing circuit under the sampling of a switched capacitor circuit can be effectively improved, and the signal-to-noise ratio performance of the whole analog front end until the output of the ADC can not be reduced.
Drawings
FIG. 1 is a schematic diagram of a chopper-stabilized circuit
FIG. 2 is a circuit diagram according to an embodiment of the present invention.
FIG. 3 is a circuit diagram of a mode selection circuit according to an embodiment of the present invention.
FIG. 4 is a waveform diagram of input and output according to an embodiment of the present invention.
Fig. 5 is an FFT diagram of a chopper-stabilized circuit that chops signals using an embodiment of the present invention.
Element number description: 1. a random chopping frequency generating circuit; 2. a first addition operation circuit; 3. a comparator; 4. a frequency multiplier circuit unit; 5. a second addition operation circuit; 6. a first delayer; 7. a second delay.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will become apparent to those skilled in the art from the present disclosure.
Please refer to fig. 1 to 5. It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for matching with the disclosure of the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modification, ratio relationship change, or size adjustment should still fall within the scope of the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "left", "right", "middle" and "one" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a scope of the present invention.
As shown in fig. 2, the present patent discloses a chopping frequency signal generating circuit, which includes a random chopping frequency generating circuit 1, a first adding operation circuit 2, a comparator 3, a frequency doubling circuit unit 4, a second adding operation circuit 5, and a delay circuit unit composed of a first delay 6 and a second delay 7. The output end of the random chopping frequency generating circuit 1 is connected with the first input end of the first addition operation circuit 2, the output end of the first addition operation circuit 2 is connected with the first input end of the comparator 3, the second input end of the comparator is connected with the reference voltage, the output end of the comparator 3 is connected with the frequency multiplication circuit unit 4, the frequency multiplication circuit unit 4 is connected with the first input end of the second addition operation circuit 5, the output end of the second addition operation circuit 5 is connected with the first delayer 6 of the delay circuit unit, the first delayer 6 is connected with the second delayer 7 in series, and the output end of the second delayer 7 is connected with the input ends of the first addition operation circuit 2 and the second addition operation circuit 5.
The working principle of the circuit is as follows: the random chopping frequency generating circuit 1 converts a square wave signal with fixed frequency into a random chopping frequency signal a, the random chopping frequency signal a is added by a first adding operation circuit 2 and a feedback signal c sent by a second delayer 7 to form a random chopping frequency signal b, the random chopping frequency signal b is compared with a reference value voltage of a comparator 3 to obtain a random chopping frequency signal with increased or decreased frequency, the random chopping frequency signal output by the comparator 3 is subjected to frequency doubling treatment by a frequency doubling circuit unit 4, then the second addition circuit 5 adds the frequency-doubled random chopping frequency signal and the feedback signal c sent by the second delayer 7, and the signals are transmitted to a first delayer 6 and a second delayer 7 for delay processing, and are fed back to the first addition operation circuit 2 and the second addition operation circuit 5.
As shown IN fig. 3, the random chopping frequency signal CHOPPER _ CLK _ IN outputted from the comparator 3 through the above circuit is further connected to a MODE selection circuit unit, the MODE selection circuit unit includes a chopping frequency signal input terminal, a clock signal input terminal and a MODE signal selection terminal, the chopping frequency signal input terminal is connected to the output terminal CHOPPER _ CLK _ IN of the comparator, the clock signal input terminal is connected to the clock input signal DCLK, the MODE signal selection terminal is connected to the MODE signal input circuit MODE _ SEL, and the MODE selection circuit unit MODE is set through MODE _ SEL to control the random variation range of the random chopping frequency signal.
As shown in fig. 4, it can be seen that the chopping frequency of the original fixed frequency is modulated to a random frequency by the chopper circuit, which is a waveform diagram of the input and output of the circuit of this patent. The FFT result (shown in figure 5) obtained after the random chopping frequency signal modulated by the chopper circuit can be accessed to the chopper stabilization circuit can realize the signal-to-noise ratio of 161.5dB, so that the chopper stabilization circuit is not the bottleneck of low noise performance, and the performance of the whole low noise circuit is greatly improved.
The chopping frequency signal generating circuit can convert the square wave chopping frequency with fixed frequency into random chopping frequency, so that the chopping frequency is not fixed frequency energy and can be dispersed to each frequency point, and the noise of superposition in an ADC baseband is greatly reduced, so that the signal-to-noise ratio performance of a chopping stabilizing circuit under the sampling of a switched capacitor circuit can be effectively improved, and the signal-to-noise ratio performance of the whole analog front end until the output of the ADC can not be reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (3)
1. A chopping frequency signal generating circuit is characterized by comprising a random chopping frequency generating circuit, a first addition operation circuit, a second addition operation circuit, a comparator, a frequency doubling circuit unit and a time delay circuit unit;
the random chopping frequency generating circuit is used for converting a square wave signal with fixed frequency into a random chopping frequency signal, the output end of the random chopping frequency generating circuit is connected with the first input end of the first addition operation circuit, the output end of the first addition operation circuit is connected with the first input end of the comparator, the second input end of the comparator is connected with the reference voltage, the comparator is used for comparing the input random chopping frequency signal with the reference voltage to obtain a random chopping frequency signal with increased or decreased frequency, the output end of the comparator is connected with the frequency doubling circuit unit, the frequency doubling circuit unit is used for performing frequency doubling processing on the random chopping frequency signal, the frequency doubling circuit unit is connected with the first input end of the second addition operation circuit, and the output end of the second addition operation circuit is connected with the time delay circuit unit, the delay circuit unit is used for carrying out delay processing on the random chopping frequency signal, and the output end of the delay circuit unit is connected with the second input end of the first addition operation circuit and the second input end of the second addition operation circuit.
2. The chopping frequency signal generating circuit according to claim 1, wherein the delay circuit unit includes a first delay and a second delay, the first delay and the second delay are connected in series, an input terminal of the first delay is connected to the frequency multiplier circuit unit, and an output terminal of the second delay is connected to the first addition circuit and the second addition circuit.
3. The chopping frequency signal generating circuit according to claim 1, further comprising a mode selection circuit unit including a chopping frequency signal input terminal, a clock signal input terminal, and a mode signal selection terminal, the chopping frequency signal input terminal being connected to the output terminal of the comparator, the clock signal input terminal being connected to a clock input signal, the mode signal selection terminal being connected to the mode signal input circuit, the mode selection circuit unit being configured to set a random variation range of the random chopping frequency signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010324895.XA CN111525926A (en) | 2020-04-23 | 2020-04-23 | Chopping frequency signal generating circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010324895.XA CN111525926A (en) | 2020-04-23 | 2020-04-23 | Chopping frequency signal generating circuit |
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| CN111525926A true CN111525926A (en) | 2020-08-11 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201835B1 (en) * | 1999-03-05 | 2001-03-13 | Burr-Brown Corporation | Frequency-shaped pseudo-random chopper stabilization circuit and method for delta-sigma modulator |
| CN101263657A (en) * | 2005-07-13 | 2008-09-10 | 德克萨斯仪器股份有限公司 | Oversampling analog-to-digital converter and method with reduced chopping residue noise |
| CN102780459A (en) * | 2012-07-21 | 2012-11-14 | 江苏物联网研究发展中心 | Pseudorandom modulation-demodulation chopping circuit applied to MEMS (micro-electro-mechanical system) reading circuit |
-
2020
- 2020-04-23 CN CN202010324895.XA patent/CN111525926A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201835B1 (en) * | 1999-03-05 | 2001-03-13 | Burr-Brown Corporation | Frequency-shaped pseudo-random chopper stabilization circuit and method for delta-sigma modulator |
| CN101263657A (en) * | 2005-07-13 | 2008-09-10 | 德克萨斯仪器股份有限公司 | Oversampling analog-to-digital converter and method with reduced chopping residue noise |
| CN102780459A (en) * | 2012-07-21 | 2012-11-14 | 江苏物联网研究发展中心 | Pseudorandom modulation-demodulation chopping circuit applied to MEMS (micro-electro-mechanical system) reading circuit |
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