CN111524890B - Process method for increasing erasing window of embedded memory - Google Patents
Process method for increasing erasing window of embedded memory Download PDFInfo
- Publication number
- CN111524890B CN111524890B CN202010326180.8A CN202010326180A CN111524890B CN 111524890 B CN111524890 B CN 111524890B CN 202010326180 A CN202010326180 A CN 202010326180A CN 111524890 B CN111524890 B CN 111524890B
- Authority
- CN
- China
- Prior art keywords
- region
- flash memory
- etching
- sti
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a process method for increasing an erasing window of an embedded memory, which comprises the steps of providing a silicon substrate, etching the silicon substrate to form an STI region and an active region, and covering the active region with silicon nitride; dividing the STI region and the silicon substrate region of the active region into a flash memory cell region and a logic region; forming a photoresist layer covering the STI region and the active region on the flash memory cell region; etching back the silicon nitride of the active region in the logic region; and removing the photoresist on the flash memory cell area. The process method of the invention adopts the silicon nitride back etching to the logic area after the photoresist is covered on the flash memory unit area, and the photoresist is used for protecting the flash memory unit area, so that in the subsequent wet etching process after the STI is formed, downward tips are formed on the upper sides of the two sides of the STI area of the flash memory unit area by carrying out the side edge undercutting on the STI field oxygen, thereby achieving the purposes that the width of the active area of the flash memory unit is not reduced due to the silicon nitride back etching, and simultaneously, the erasing window of the flash memory unit is also increased.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a process method for increasing an erasing window of an embedded memory.
Background
Embedded flash memory has very important applications in semiconductor technology. The difference in turn-on threshold voltages of embedded flash memories after writing and erasing, respectively, is a key for distinguishing between the "0" and "1" signals of the circuits. The greater this difference, the higher the reliability associated with flash memory in the circuit. The difference in turn-on threshold voltages of an embedded flash after writing and erasing, respectively, is referred to as the embedded memory erase window.
In the conventional STI (shallow trench isolation) process, there is a one-step isotropic silicon nitride etching back process (shown in fig. 2) after the STI silicon substrate is etched (shown in fig. 1). The purpose is to achieve that the field oxide silicon dioxide filled later protects the corners (corner) on the upper sides of the STI (as shown in fig. 3). Thus, when the MOS transistor is finally formed, the corners (corners) on the upper side of the STI are protected by silicon dioxide, so that no extra leakage is formed (as shown in figure 4).
The reason is that the upper corners (corners) of the two sides of the STI are sharp, and the electric field at the corners is strong, so that electric leakage is easy to occur. At the cost of shrinking the width of the active region: i.e., the etched portions of silicon nitride.
In the STI (shallow trench isolation) process, if a silicon nitride etch-back process is not used. The corners (corners) on the upper sides of the STI eventually form recesses, so that the electric field at the location of the polysilicon gate forms a strong electric field similar to a tip discharge. Causing additional leakage (as shown in fig. 5) in the conventional logic tube.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an objective of the present invention is to provide a process for increasing the erasing window of an embedded memory, which is used for solving the problem of the prior art that the width of an active region is reduced due to the adoption of silicon nitride back etching in the shallow trench isolation process.
To achieve the above and other related objects, the present invention provides a process for increasing an erasing window of an embedded memory, the process at least comprising the following steps:
step one, providing a silicon substrate, etching the silicon substrate to form an STI region and an active region, and covering silicon nitride on the active region; dividing the silicon substrate regions of the STI region and the active region into a flash memory cell region and a logic region;
forming a layer of photoresist covering the STI region and the active region on the flash memory unit region;
step three, back etching is carried out on the silicon nitride of the active region in the logic region;
removing the photoresist on the flash memory unit area;
step five, forming a field oxide region in the flash memory unit region and the logic region synchronously;
and step six, etching the field oxide region to enable the upper sides of the two sides of the STI region of the flash memory unit region to form downward tips through side edge undercutting of the field oxide region.
Preferably, in the first step, silicon oxide is further disposed between the silicon substrate of the active region and the silicon nitride.
Preferably, the etching back of the silicon nitride in the third step is isotropic etching.
Preferably, the etching back of the silicon nitride of the active region in the logic region in the third step is wet etching.
Preferably, the method for forming the field oxide region in the fifth step includes: 1. synchronously depositing a layer of silicon oxide in the flash memory unit region and the logic region, wherein the deposited silicon oxide fills the flash memory unit region and the STI region of the logic region; 2. and removing the silicon nitride and the silicon oxide on the active region in the flash memory unit region and the logic region, and exposing the upper surface of the silicon substrate of the active region.
Preferably, the etching performed on the field oxide region in the step six is wet etching.
Preferably, after etching the field oxide region in the step six, top corners on two sides of the STI region of the logic region are covered by the field oxide region.
As described above, the process method for increasing the erasing window of the embedded memory has the following beneficial effects: the process method of the invention adopts the silicon nitride back etching to the logic area after the photoresist is covered on the flash memory unit area, and the photoresist is used for protecting the flash memory unit area, so that in the subsequent wet etching process after the STI is formed, downward tips are formed on the upper sides of the two sides of the STI area of the flash memory unit area by carrying out the side edge undercutting on the STI field oxygen, thereby achieving the purposes that the width of the active area of the flash memory unit is not reduced due to the silicon nitride back etching, and simultaneously, the erasing window of the flash memory unit is also increased.
Drawings
FIG. 1 is a schematic diagram of a prior art structure for forming an STI region in a silicon substrate;
FIG. 2 is a schematic diagram of the structure of an active region after etching back silicon nitride in the prior art;
FIG. 3 is a schematic diagram showing a structure of the prior art for covering sharp corners on the upper side of STI after filling the STI region;
FIG. 4 is a schematic diagram showing a prior art structure for forming a polysilicon gate over an field oxide region;
FIG. 5 is a schematic diagram showing the structure of the prior art for forming a recess on the upper side of the STI region without etching back silicon nitride;
fig. 6 is a schematic diagram showing the structure of the STI region formed on a silicon substrate according to the present invention;
FIG. 7 is a schematic diagram of the structure of the present invention after photoresist is formed in the flash memory cell area;
FIG. 8 is a schematic diagram of the structure of the logic region after etching back silicon nitride according to the present invention;
FIG. 9 is a schematic diagram of the structure of the flash memory cell region after photoresist removal according to the present invention;
FIG. 10 is a schematic diagram of the structure of the present invention after forming field oxide regions in the flash memory cell region and the logic region;
FIG. 11 is a schematic diagram showing the structure of the present invention for forming tips by etching on both sides of the STI region of the flash memory cell region in an undercut manner;
FIG. 12 is a flow chart of a process for increasing the erasing window of an embedded memory according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 6 to 12. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides a process method for increasing an embedded memory erasing window, as shown in fig. 12, fig. 12 is a flow chart of the process method for increasing the embedded memory erasing window. The method at least comprises the following steps:
step one, providing a silicon substrate, etching the silicon substrate to form an STI region and an active region, and covering silicon nitride on the active region; dividing the silicon substrate regions of the STI region and the active region into a flash memory cell region and a logic region; as shown in fig. 6, fig. 6 is a schematic structural diagram of forming an STI region on a silicon substrate in the present invention, in which an STI region (shallow trench isolation region) is formed on the provided silicon substrate, the STI region is formed by performing an etching process on the silicon substrate to form regions isolated from each other, the STI region formed by etching is a trench, and a portion of the silicon substrate between the trenches of any two STI regions is an active region, as shown in fig. 6. That is, this step forms the active region at the same time as the STI region is etched; this step one of the invention is to blanket form a layer of silicon nitride as described in fig. 6 over the active region. The invention is divided into a flash memory cell region and a logic region except the flash memory cell region on a silicon substrate where an STI region and an active region are formed, wherein the left region of a vertical line is the flash memory cell region in FIG. 6, and the right region of the vertical line is the logic region.
In the first step, silicon oxide is further arranged between the silicon substrate of the active region and the silicon nitride. As shown in fig. 6, this step-before forming silicon nitride on the active region, silicon oxide is now formed on the active region, and then silicon nitride is formed on the silicon oxide, so that in this embodiment, the silicon oxide is located between the active region and the silicon nitride.
Forming a layer of photoresist covering the STI region and the active region on the flash memory unit region; FIG. 7 is a schematic diagram of the structure of the present invention after photoresist is formed in the flash memory cell region; in the second step, photoresist formed on the flash memory cell region covers the trench of the STI region of the flash memory cell region and covers the upper surface of the silicon nitride of the flash memory cell region. The method is used for protecting the flash memory cell area, so that the flash memory cell area is not etched simultaneously in the subsequent etching process, and therefore, the covered photoresist plays a role in protection.
Step three, back etching is carried out on the silicon nitride of the active region in the logic region; FIG. 8 is a schematic diagram of the structure of the logic region of the present invention after etching back silicon nitride, as shown in FIG. 8; in the process of etching back silicon nitride, the silicon nitride and silicon oxide in the flash memory unit area are not etched due to the protection of the photoresist, and the silicon nitride and silicon oxide on the active area in the logic area are exposed due to the fact that the photoresist is not covered, so that in the process of etching back silicon nitride, the silicon nitride in the logic area is etched. In the invention, the back etching of the silicon nitride in the step three is isotropic etching. As shown in fig. 8, the etching method adopted in the step of etching the silicon nitride of the logic region is an isotropic etching method, and in this embodiment, the silicon nitride on the silicon oxide is exposed above and on both sides, so that in the process of adopting isotropic etching, the upper surface and both sides of the silicon nitride are etched to the same extent.
In the third step, the etching back of the silicon nitride of the active region in the logic region is wet etching.
And step four, removing the photoresist on the flash memory unit area. FIG. 9 is a schematic diagram of the structure of the flash memory cell region according to the present invention after photoresist is removed, as shown in FIG. 9; and step four, after isotropic etching back is carried out on the silicon nitride in the logic region, photoresist covering the silicon nitride and the STI region in the flash memory unit region is completely removed, and the silicon nitride and the trench of the STI region in the flash memory unit region are completely exposed.
Step five, forming field oxide regions in the flash memory cell region and the logic region synchronously, as shown in fig. 10, fig. 10 is a schematic structural diagram of the present invention after forming field oxide regions in the flash memory cell region and the logic region. The method for forming the field oxide region in the fifth step further comprises the following steps: 1. and synchronously depositing a layer of silicon oxide in the flash memory cell area and the logic area, wherein the deposited silicon oxide fills the STI regions of the flash memory cell area and the logic area.
2. And removing the silicon nitride and the silicon oxide on the active region in the flash memory unit region and the logic region, and exposing the upper surface of the silicon substrate of the active region. Thereafter, a field oxide region as shown in fig. 10 is formed. In the flash memory cell region, since the silicon nitride on the active region and the silicon nitride isotropic etching are not performed, the width of the active region is not reduced, so that the field oxide region on the flash memory cell region does not occupy the region on the active region after the silicon nitride on the active region is removed after the field oxide region is formed, and the field oxide region covers the upper side edge of the STI region after the silicon nitride on the active region of the logic region is removed after the field oxide region is formed (as shown in fig. 10). And step six, etching the field oxide region to enable the upper sides of the two sides of the STI region of the flash memory unit region to form downward tips through side edge undercutting of the field oxide region. As shown in fig. 11, fig. 11 is a schematic diagram showing the structure of the present invention in which tips are formed by side-etching on both sides of STI regions of a flash memory cell region by etching in an oxygen region. In this step, between the field oxide regions, since the active region of the flash memory cell region is not partially covered by the field oxide regions, after the field oxide regions are etched, the field oxide regions of the flash memory cell region form a structure as shown in fig. 11, and the field oxide regions on both sides of the STI region are laterally etched to form a tip structure as shown in fig. 11, that is, STI DIVOT. Further, the etching performed on the field oxide region in the step six is wet etching, and further, after the etching is performed on the field oxide region in the step six, top angles on two sides of the STI region of the logic region are covered by the field oxide region.
For the embedded flash memory, the number of electrons/holes in the charge storage layer is influenced by allowing electrons or holes to pass through the tunneling insulating layer, so that the opening threshold voltage of the flash memory is influenced, and the purpose of distinguishing 0 and 1 is achieved. Therefore, increasing the electric field strength under the control of the polysilicon gate increases the bidirectional tunneling current of electrons or holes through the tunneling insulating layer, thereby achieving the purpose of increasing the difference of the opening threshold voltages of the embedded flash memory after writing and erasing respectively, namely the erasing window of the embedded memory. Therefore, it is not necessary for the embedded flash memory to use a silicon nitride etch back process in the STI (shallow trench isolation) process. Therefore, in the process of etching back the silicon nitride of the logic area except the flash memory unit area, the method of the invention covers the photoresist of the flash memory unit area, thereby protecting the silicon nitride of the flash memory unit from being etched. Therefore, the width of the active region in the flash memory cell region is not reduced.
On the one hand, the method of the invention increases the erasing current caused by the strong electric field formed by the corner (burner) concave on the upper sides of the two sides of the STI region. On the other hand, the width of the active region is not reduced due to the silicon nitride back etching process.
In summary, the process method of the invention adopts the silicon nitride etching to the logic area after the photoresist is covered on the flash memory cell area, and the photoresist is used to protect the flash memory cell area, so that the downward tips are formed by the side edge undercutting of the STI field oxide on the upper side of the two sides of the STI area of the flash memory cell area in the subsequent wet etching process after the STI is formed, thereby achieving the purposes that the width of the flash memory cell active area is not reduced due to the silicon nitride etching, and the erasing window of the flash memory cell is also increased. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (6)
1. A process method for increasing an erasing window of an embedded memory, which is characterized by at least comprising the following steps:
step one, providing a silicon substrate, etching the silicon substrate to form an STI region and an active region, and covering silicon nitride on the active region; dividing the silicon substrate areas of the STI region and the active region into a flash memory cell area and a logic area;
forming a layer of photoresist covering the STI region and the active region on the flash memory unit region;
step three, back etching is carried out on the silicon nitride of the active region in the logic region; the back etching of the silicon nitride is isotropic etching, and the upper surface and the two side surfaces of the silicon nitride are etched to the same extent;
removing the photoresist on the flash memory unit area;
step five, forming a field oxide region in the flash memory unit region and the logic region synchronously;
and step six, etching the field oxide region to enable the upper sides of the two sides of the STI region of the flash memory unit region to form downward tips through side edge undercutting of the field oxide region.
2. The process for increasing an erase window of an embedded memory according to claim 1, wherein: in the first step, silicon oxide is further arranged between the silicon substrate of the active region and the silicon nitride.
3. The process for increasing an erase window of an embedded memory according to claim 1, wherein: and step three, etching back the silicon nitride of the active region in the logic region by wet etching.
4. The process for increasing an erase window of an embedded memory according to claim 1, wherein: the method for forming the field oxide region in the fifth step comprises the following steps: 1. synchronously depositing a layer of silicon oxide in the flash memory unit region and the logic region, wherein the deposited silicon oxide fills the flash memory unit region and the STI region of the logic region; 2. and removing the silicon nitride and the silicon oxide on the active region in the flash memory unit region and the logic region, and exposing the upper surface of the silicon substrate of the active region.
5. The process for increasing an erase window of an embedded memory according to claim 1, wherein: and step six, etching the field oxide region is wet etching.
6. The process for increasing an erase window of an embedded memory according to claim 1, wherein: and step six, after etching the field oxide region, top angles at two sides of the STI region of the logic region are covered by the field oxide region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010326180.8A CN111524890B (en) | 2020-04-23 | 2020-04-23 | Process method for increasing erasing window of embedded memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010326180.8A CN111524890B (en) | 2020-04-23 | 2020-04-23 | Process method for increasing erasing window of embedded memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111524890A CN111524890A (en) | 2020-08-11 |
| CN111524890B true CN111524890B (en) | 2023-08-22 |
Family
ID=71903576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010326180.8A Active CN111524890B (en) | 2020-04-23 | 2020-04-23 | Process method for increasing erasing window of embedded memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111524890B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489214A (en) * | 2002-08-30 | 2004-04-14 | ��ʿͨ��ʽ���� | Semiconductor device and manufacturing method thereof |
| CN1518089A (en) * | 2003-01-16 | 2004-08-04 | ���ǵ�����ʽ���� | Semiconductor device with multi-grid insulating barrier and its manufacturing method |
| CN1956163A (en) * | 2005-10-27 | 2007-05-02 | 上海华虹Nec电子有限公司 | Process method of implementing shallow ridge separation |
| CN110648959A (en) * | 2019-10-23 | 2020-01-03 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004228358A (en) * | 2003-01-23 | 2004-08-12 | Fujitsu Ltd | Method of manufacturing semiconductor apparatus |
| US20060244095A1 (en) * | 2005-04-29 | 2006-11-02 | Barry Timothy M | Method of forming a shallow trench isolation structure with reduced leakage current in a semiconductor device |
-
2020
- 2020-04-23 CN CN202010326180.8A patent/CN111524890B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489214A (en) * | 2002-08-30 | 2004-04-14 | ��ʿͨ��ʽ���� | Semiconductor device and manufacturing method thereof |
| CN1518089A (en) * | 2003-01-16 | 2004-08-04 | ���ǵ�����ʽ���� | Semiconductor device with multi-grid insulating barrier and its manufacturing method |
| CN1956163A (en) * | 2005-10-27 | 2007-05-02 | 上海华虹Nec电子有限公司 | Process method of implementing shallow ridge separation |
| CN110648959A (en) * | 2019-10-23 | 2020-01-03 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111524890A (en) | 2020-08-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106057895B (en) | Self-aligning joint for groove power MOSFET | |
| US7508048B2 (en) | Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby | |
| KR20040011656A (en) | Flash memory devices having shallow trench isolation structures and methods of fabricating the same | |
| CN109712981B (en) | Memory and forming method thereof | |
| JP2007157927A (en) | Non-volatile semiconductor memory device and method of manufacturing same | |
| US20120252186A1 (en) | Semiconductor device and method for forming the same | |
| US6794250B2 (en) | Vertical split gate flash memory cell and method for fabricating the same | |
| US7572702B2 (en) | Split gate type non-volatile memory device | |
| KR20060030717A (en) | Manufacturing method for semiconductor device | |
| CN111415937B (en) | Memory and forming method thereof | |
| CN111524890B (en) | Process method for increasing erasing window of embedded memory | |
| CN108807391B (en) | Flash memory and forming method thereof | |
| US6849514B2 (en) | Method of manufacturing SONOS flash memory device | |
| US11600627B2 (en) | Memory and method for forming the same | |
| CN114927528A (en) | Memory structure and forming method thereof | |
| KR100939425B1 (en) | Method for manufacturing semiconductor device | |
| JP4049425B2 (en) | Method for manufacturing nonvolatile semiconductor memory device | |
| CN109712982B (en) | Flash memory and forming method thereof | |
| KR100384794B1 (en) | Flash memory cell and manufacturing method thereof | |
| CN100361303C (en) | Flash memory storage unit and its mfg. method | |
| KR20070098291A (en) | Self align type flash memory device and method of forming the same | |
| KR100220942B1 (en) | A flash memory device and its manufacturing method | |
| KR20080033614A (en) | Non volatile memory device and method for fabricating the same | |
| CN116156885A (en) | Method for manufacturing semiconductor device | |
| KR100474509B1 (en) | Method of manufacturing a flash memory cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |