CN111524540B

CN111524540B - Novel automobile audio Digital chip player

Info

Publication number: CN111524540B
Application number: CN202010638198.1A
Authority: CN
Inventors: 韦玮; 郭宁之; 杨勇; 陈亮; 曹乐千; 张勇; 崔立业; 张歆钰; 姜杨
Original assignee: Yanfeng Visteon Electronic Technology Nanjing Co Ltd
Current assignee: Yanfeng Visteon Electronic Technology Nanjing Co Ltd
Priority date: 2020-07-06
Filing date: 2020-07-06
Publication date: 2020-11-20
Anticipated expiration: 2040-07-06
Also published as: CN111524540A

Abstract

The invention relates to a novel automobile audio Digital chip player, which belongs to the technical field of automobile electronics and comprises an MCU (microprogrammed control unit), a DSP (Digital signal processor), a first Flash and a second Flash, wherein the MCU is connected with the DSP and the first Flash, and the DSP is connected with the first Flash and the second Flash; during initialization, the DSP is a host, the second Flash is a slave, a HiFi processing program of the second Flash is loaded into a HiFi kernel of the DSP, after initialization, communication between the DSP and the second Flash is cut off, the DSP mounts an SPI data channel onto the SPI data channel between the MCU and the first Flash, the MCU is the host, the first Flash is the slave, and the DSP is switched from the host to the slave, so that data transmission of double slaves is realized. The player can effectively improve the sound quality of the Chime, can freely customize diversified sound effects, and overcomes the dependence on a specific DSP chip module.

Description

Novel automobile audio Digital chip player

Technical Field

The invention relates to the technical field of automobile electronics, in particular to an automobile audio Digital chip player based on a dual-slave-machine Digital transmission strategy.

Background

With the development of automobile electronic technology, each large automobile manufacturer has more and more Chime application scenes, more and more pursuits of users for high-quality sound are obtained, and the requirements of Chime gradually develop from singleness to high-quality and diversification. Currently, the playing of the Chime on an automobile mainly depends on the existing modules provided by a DSP chip supplier to realize the prompting sound effect under various scenes, common sine wave modulation and chord tones are generally adopted, the output Chime sound is single and poor in sound quality, and meanwhile, a configuration register is complex in operation and complicated in change.

Disclosure of Invention

The invention aims to provide a car audio Digital chip player of low-delay stereo based on a dual-slave-machine Digital transmission strategy, which is suitable for a DSP chip supporting a HiFi kernel and provided with an independent data transmission channel, overcomes the dependence on a DSP chip module, improves the sound quality of the chip, and can freely customize diversified sound effects.

In order to achieve the purpose, the invention adopts the technical scheme that a novel automobile audio Digital chip player supports playing high-resolution lossless audio files, generally in a Wav file format, also called Wav chip, and comprises a main control MCU, a data processor DSP, a first Flash memory (namely Wav chip Flash) and a second Flash memory (namely HiFi Core Flash), wherein the main control MCU is connected with the data processor DSP through an SPI/IIC data bus, the main control MCU is connected with the first Flash memory through an SPI data bus, and the data processor DSP is respectively connected with the first Flash memory and the second Flash memory through the SPI data bus; a HiFi kernel is arranged in the data processor DSP, the data processor DSP is used as a host and the second Flash memory is used as a slave in an initialization stage, a HiFi processing program in the second Flash memory is loaded into the HiFi kernel (i.e. HiFi kernel) of the data processor DSP through an SPI data bus, after the initialization is finished, the communication between the data processor DSP and the second Flash memory is cut off, meanwhile, the SPI data channel is directly mounted on the SPI data channel between the master control MCU and the first Flash memory by the data processor DSP, at the moment, the master control MCU is used as the host, the first Flash memory is used as the slave, the data processor DSP is switched from the host to the slave, and the data transmission between the two slaves is realized by adopting a double-slave data transmission control strategy; when the Digital chip needs to be played, the audio data of the Digital chip is read from the first Flash memory and transmitted to a HiFi kernel of the data processor DSP, and the HiFi kernel performs aliasing on the main media sound source and the Digital chip sound and outputs the aliasing to the data processor DSP for subsequent processing and playing.

The Digital chip audio data is stored in an external Flash memory and comprises header information and PCM source data, wherein the header information starts from a storage address of 0x0 to 0xFFF and can support 4KB to the maximum extent, the header information is used for storing the version number, the audio format, the channel number, the sampling rate, the bit sampling, the number of supportable chips, the data parameter of each chip and the like, the data parameter of each chip comprises a chip _ ID, a start address, a data length, a Checksum and the like, and the information records the start address of the PCM source data of the chip corresponding to the ID in Wav chip Flash, the PCM source data length of the chip and a data Checksum. The PCM source data stores all supportable audio stream data of the stereo chip starting from the storage address 0x1000, and the audio stream data is based on PCM coding and can obtain good sound quality effect without any compression processing. The data transmission of the Digital chip player is between a main control MCU, a data processor DSP, a first Flash memory and a second Flash memory, the control of the two Flash memories is realized by multiplexing of a single data channel of the data processor DSP, the Digital chip player is divided into a program initialization stage and a normal working stage, in the program initialization stage, an SPI channel HIFI _ SPI between the data processor DSP and the second Flash memory and an SPI channel WAV _ SPI between the main control MCU and the first Flash memory work, on the HIFI _ SPI channel, the data processor DSP is used as a host to control a second Flash memory (HiFi Core Flash) of a slave, HiFi processing program data in the second Flash memory (HiFi Core Flash) is transmitted into a HiFi kernel of the data processor DSP, on the WAV _ SPI channel, the main control MCU is used as the host to control the first Flash memory (Wav Core Flash) of the slave, reading 4KB header information in a first Flash memory (Wav Chime Flash); after the program initialization is completed, a normal working stage is entered, the DSP and a second Flash memory (HiFi Core Flash) are disconnected, a HIFI _ SPI passage does not work, an independent data transmission passage DSP _ SPI and a WAV _ SPI passage of the DSP work, at the moment, the main control MCU serves as a host, and the DSP and a first Flash memory (Wav chip Flash) serve as slaves.

As an improvement of the present invention, the dual-slave data transmission control strategy is to mount a DSP _ SPI channel on a Wav _ SPI channel between a master control MCU and a first FLash memory (Wav chip FLash), share a data line and a clock line of the DSP _ SPI channel and the Wav _ SPI channel, separately control CS lines of two slaves by the master control MCU, and perform policy control on timing sequences of two CS pins, thereby achieving DSP data sharing of the master control MCU and the data processor.

As an improvement of the present invention, the dual slave data transmission management and control policy specifically includes the following three steps:

the first step is as follows: when the Digital Chime player needs to play a Digital Chime with a certain ID, the main control MCU firstly sends an instruction through an SPI/IIC communication interface between the Digital Chime player and the data processor DSP to inform the data processor DSP of the address and the size of data to be written (the address is in the RAM of HiFi Core of the DSP, and the HiFi independently opens up 8KB size to store PCM source data);

the second step is that: indexing the initial address and the data length of PCM source data of the Digital chip in a first FLash memory (Wav chip FLash) by header information in Digital chip audio data, and initiating a data reading instruction request to the first FLash memory (Wav chip FLash) by a main control MCU (microprogrammed control Unit) through pulling down a WAV _ CS pin;

the third step: when the main control MCU receives a data transmission interruption request returned by a first FLash memory (Wav chip FLash), a WAV _ MOSI pin of the main control MCU is changed into an input mode from an output mode, at the moment, a DSP _ CS pin is pulled down, data in the first FLash memory (Wav chip FLash) start to be transmitted to the main control MCU through a WAV _ SPI _ MISO line, and meanwhile, the WAV _ SPI _ MISO line and the DSP _ SPI _ MOSI line are connected, so that the data on the WAV _ SPI _ MISO line are transmitted to the WAV _ SPI _ MOSI line and the DSP _ SPI _ MOSI line, and at the moment, the data are transmitted into a data processor DSP through the DSP _ SPI _ MOSI line.

As an improvement of the invention, two buffer areas BUF _0 and BUF _1 are arranged in a HiFi kernel of the data processor DSP to store PCM source data, instruction interaction is carried out with a main control MCU in a memory sharing mode, data of the two buffer areas are played in a time-sharing mode and loaded in a time-sharing mode through real-time control of a playing flow task, namely, only audio data of a single buffer area is played at the same time, and playing is started after the audio data of the current buffer area is played after the other buffer area is loaded with the data, so that a Digital chip can be played continuously.

As an improvement of the invention, a processing program of the HiFi kernel is stored in a second Flash memory (HiFi Core Flash), an independent sound mixing module is arranged in the HiFi kernel, Digital Core sound obtained from a buffer zone is mixed into a main sound source data path, and then a superposed signal is transmitted to a data processor DSP and is output to an external power amplifier by the data processor DSP; the main control MCU is provided with two shared memory areas DATA _ FROM _ HOST and DATA _ TO _ HOST which are used for instructing interaction and controlling a playing process, the HiFi kernel plays audio DATA of a buffer area according TO a control instruction of the shared memory area DATA _ FROM _ HOST and updates necessary parameter information in playing in the shared memory area DATA _ TO _ HOST, the main control MCU acquires the current playing state of the HiFi kernel, and the main control MCU updates a control instruction in the shared memory area DATA _ FROM _ HOST according TO the playing state information, so that time-sharing and continuous playing of BUF _0 and BUF _1 is managed, Digital Chiaudio DATA is superposed into a main audio source DATA passage and then is output TO the DATA processor DSP by the sound mixing module.

As an improvement of the invention, the main control MCU adopts a double buffer mode to manage the playing flow of the Digital chip, the playing is divided into an initialization loading stage and a circular playing stage, the initialization loading stage is prepared before playing, some necessary initialization information is written in, and BUF _0 audio data is loaded, and the circular playing stage is to control double buffers to carry out staggered loading data to realize the alternate circular playing of BUF _0 and BUF _1, thereby completing the playing of the whole chip.

In the initial loading stage, all write-in instructions are realized by depending on a shared memory area DATA _ FROM _ HOST, read-out instructions are realized by depending on the shared memory area DATA _ TO _ HOST, and after a Digital chip player task is started, an emptying instruction is written in, the playing state is set TO be idle, and some state variables are cleared; then, the volume parameter of the sound mixing module in the HiFi kernel needs to be set, and the PCM source data checksum of the Chime is written in; then pointing the buffer to be loaded to the initial address of BUF _0, indexing the initial address and the data length of the audio data of the chip in a first Flash memory (Wav chip Flash) by a chip _ ID, performing packet division processing on the audio data, taking 4KB data as a packet, calculating the total packet number, and loading the first packet data into BUF _0 from the first Flash memory (Wav chip Flash); the control instruction of the shared memory area DATA _ FROM _ HOST comprises parameters such as total packet number, current packet number, play mode and the like, the control instruction is written into a play control instruction, the audio DATA in the BUF _0 is played, and at the moment, the chip starts to play;

in the stage of circular playing, after the Chime starts playing, the buffer area starts to be loaded, the address of the buffer area to be loaded points to BUF _0, the BUF _0 and the BUF _1 need to be exchanged, the pointer of the buffer area to be loaded points to BUF _1, and the next packet of 4KB data is loaded to BUF _ 1; reading the playing state of HiFi through a shared memory area DATA _ TO _ HOST, acquiring the playing progress, the playing state and the like of the current packet of DATA, judging whether abnormal conditions such as Underrun or Overrun occur, if so, ending the Digital chip player, reporting a playing error code, if the playing is normal, calculating the remaining playing time of the buffer area through the playing progress, and starting a timer; and after the playing of the single buffer area is finished, updating a playing instruction, judging whether the data is the last packet of data, if not, continuing to exchange BUF _0 and BUF _1, loading the data in the buffer area, and if so, ending the Digital chip player and finishing the playing of the whole chip.

As an improvement of the invention, the main control MCU adopts an RH850 microcontroller of Ryssa electronics, the data processor DSP adopts an automobile audio chip Dirana3 (D3 for short) of Enzhipu, the first Flash memory adopts a Flash chip with the model number of N25Q128A, and the second Flash memory adopts a plug-in Flash chip.

Compared with the prior art, the Digital Chime player has the advantages of ingenious overall structure design, reasonable and stable structure and high data transmission speed, utilizes the master control MCU as a main controller to control the DSP and the Wav Chime Flash which support the HiFi kernel and are provided with independent data transmission channels, effectively overcomes the dependence on the inherent module of the DSP chip, reduces the design cost, the internal data transmission of the Digital chip player realizes the data transmission operation of two flashes through the multiplexing of an independent data channel of a data processor DSP, adopts a data transmission control strategy of double slave machines, realizes the data transmission of two slave machines by one-way host control, avoids the data transfer, realizes the direct data transmission of the Wav chip Flash into the data processor DSP only through the time sequence control of a CS pin, greatly shortens the data transmission time, and does not occupy the master control MCU resource; in addition, the playing process management of the Digital chip player realizes double-buffer mode playing by the main control MCU, two buffer areas are adopted in the HiFi Core to store PCM source data, instruction interaction is carried out with the main control MCU in a memory sharing mode, the data of the two buffer areas are played in a time-sharing mode and loaded in a time-sharing mode through real-time control of playing process tasks, continuous playing of audio data is realized, the sound quality of the chip is improved, and diversified sound effects can be freely customized.

Drawings

FIG. 1 is an architecture diagram of a Digital chip player according to the present invention;

FIG. 2 is a schematic diagram of a data transmission structure of a Digital chip player according to the present invention;

FIG. 3 is a schematic structural diagram of a mixing module of a Digital chip player according to the present invention;

FIG. 4 is a flow chart of the dual buffer mode playback management of a Digital chip player according to the present invention;

FIG. 5 is a diagram illustrating a data transmission structure of a Digital chip player in accordance with a preferred embodiment of the present invention;

FIG. 6 is a timing diagram illustrating the dual buffer mode playback management in a Digital chip player according to a preferred embodiment of the present invention.

Detailed Description

For a better understanding and appreciation of the invention, it is further described and illustrated below in connection with the accompanying drawings.

As shown in fig. 1, a novel car audio Digital chip player is designed mainly based on a HiFi Core architecture, supports playing high-resolution lossless audio files, and can meet the requirements of low delay and fast sound production and play high-quality sound. The Digital chip player comprises a main control MCU, a data processor DSP, a Wav chip Flash and a HiFi Core Flash, wherein data transmission mainly exists among the main control MCU, the data processor DSP and the Flash, because SPI transmission is stable and transmission speed is relatively high, an SPI channel of the data processor DSP is preferably adopted as an independent data transmission channel, communication between the main control MCU and the data processor DSP only has instruction interaction, a large amount of data is not transmitted, and SPI or IIC can be adopted. Therefore, the main control MCU is connected with the data processor DSP through the SPI/IIC data bus, the main control MCU is connected with the Wav Chime Flash through the SPI data bus, and the data processor DSP is respectively connected with the Wav Chime Flash and the HiFi Core Flash through the SPI data bus. The master control MCU is used for controlling the data processor DSP and the Wav chip Flash, the data transmission between the master control MCU and the Wav chip Flash adopts SPI _ X, and the data processor DSP needs an independent data channel SPI _ Y. The method comprises the steps that a HiFi kernel is arranged in a data processor DSP, the data processor DSP is used as a host and a HiFi Core Flash is used as a slave in an initialization stage, a HiFi processing program in the HiFi Core Flash is loaded into the HiFi kernel (namely the HiFi Core) of the data processor DSP through SPI _ Y, after initialization is finished, communication between the data processor DSP and the HiFi Core Flash is cut off, meanwhile, an SPI _ Y data channel is directly mounted on an SPI _ X data channel between a master control MCU and a Wav Core Flash by the data processor DSP, the master control MCU is used as the host, the Wav Core Flash is used as a slave, the data processor DSP is switched from the host to the slave, and accordingly, a dual-slave data transmission control strategy is adopted to achieve data transmission between the two slaves. When the Digital chip needs to be played, reading PCM source data of the Digital chip from the Wav chip Flash, transmitting the PCM source data to a HiFi kernel of a data processor DSP, and performing aliasing on a main media sound source and Digital chip sound by the HiFi kernel and outputting the aliasing to the data processor DSP for subsequent processing and playing.

The Digital chip audio data is stored in an external Flash memory, the data is aligned at 4KB to support sector erasure, and the defined data is stored in big-endian format. The method comprises header information and PCM source data, wherein the header information starts from 0x0 address and is used for storing the version number, audio format, channel number, sampling rate, bit sampling, the number of supportable Chimes, the data parameter of each Chime and the like, the data parameter of each Chime comprises a Chime _ ID, a start address, data length, Checksum and the like, and the information records the start address of the PCM source data of the Chime corresponding to the ID in Wav Chime Flash, the PCM source data length of the Chime and data Checksum. The PCM source data stores all audio stream data of the supportable stereo Chime starting from 0x1000 address.

When the initialization of the system is finished, the head information of the front 4KB in the Wav chip Flash can be directly read, so that the information of each chip is analyzed and stored, when a Digital chip player receives an instruction to play a certain Digital chip, the information can be provided for a main control MCU by inquiring the initial address and the data size of PCM source data of the chip indexed by the chip _ ID, and the main control MCU can read the corresponding data length from the corresponding address of the Wav chip Flash.

The data transmission of the Digital chip player is between a main control MCU, a data processor DSP, a Wav chip Flash and a Wav chip Flash, the data transmission operation of the two Flash processors is realized through multiplexing of a single data channel of the data processor DSP, as shown in figure 2, the data transmission operation is divided into a program initialization stage and a normal working stage, in the program initialization stage, an SPI channel HIFI _ SPI between the data processor DSP and the HiFi chip Flash and an SPI channel WAV _ SPI between the main control MCU and the Wav chip Flash work, on the HIFI _ SPI channel, the data processor DSP is used as a host to control the slave HiFi chip Flash, HiFi processing program data in the HiFi chip Flash is transmitted into a HiFi inner Core of the data processor DSP, on the WAV _ SPI channel, the main control MCU is used as the host to control the slave Wav chip Flash, and head information of 4KB in the Wav chip Flash is read. After the program initialization is completed, a normal working stage is entered, the DSP and the HiFi Core Flash are disconnected, the HIFI _ SPI channel does not work, the DSP independent data transmission channel DSP _ SPI and the WAV _ SPI channel work, the main control MCU is used as a host, and the DSP and the WAV Core Flash are used as slaves.

The dual-slave data transmission control strategy is characterized in that a DSP _ SPI channel is mounted on a WAV _ SPI channel between a master control MCU and a Wav chip Flash, the data lines and clock lines of the DSP _ SPI channel and the WAV _ SPI channel are shared, the master control MCU controls CS lines of two slaves independently, and strategy control on time sequence is carried out on two CS pins, so that DSP data sharing of the master control MCU and a data processor is realized.

The main reason for designing like this is because if regard as the transfer through master control MCU, master control MCU reads data from Wav chip Flash earlier, and rethread master control MCU transmits for data processor DSP, and operation can waste the transmission time of PCM data on the one hand like this, and on the other hand can increase master control MCU's work load, wastes a lot of unnecessary resources, influences other tasks and carries out. According to the double-slave data transmission control strategy, one path of host control is adopted, two paths of slave data transmission are realized, data transfer is avoided, and Wav Chime Flash is directly transmitted into a data processor DSP only through time sequence control of a CS pin, so that the data transmission time is greatly shortened, and meanwhile, the master MCU resource is not occupied.

The dual-slave data transmission management and control strategy specifically comprises the following three steps:

the first step is as follows: when a Digital chip player needs to play a Digital chip, the main control MCU firstly sends an instruction through an SPI/IIC communication interface between the Digital chip player and the data processor DSP to inform the data processor DSP of the address and the size of data to be written (the address is in a RAM of a HiFi Core of the data processor DSP, and the HiFi Core can independently store PCM data in 8KB size).

The second step is that: and indexing the initial address and the data length of PCM source data of the Digital chip in the Wav chip Flash by header information in the audio data of the Digital chip, and initiating a data reading instruction request to the Wav chip Flash by the main control MCU through pulling down a WAV _ CS pin.

The third step: when the master control MCU receives a data transmission interruption request returned by the Wav chip Flash, the WAV _ MOSI pin of the master control MCU is changed from an output mode to an input mode, the DSP _ CS pin is pulled down at the moment, and data in the Wav chip Flash starts to be transmitted to the master control MCU through the WAV _ SPI _ MISO line. Because of the logic design of the hardware circuit, when the DSP _ CS pin is pulled down, the WAV _ SPI _ MISO line and the DSP _ SPI _ MISO line are cut off, and the WAV _ SPI _ MISO line and the WAV _ SPI _ MOSI line are connected, namely the WAV _ SPI _ MISO line and the DSP _ SPI _ MOSI line are connected, so that the data on the WAV _ SPI _ MISO line is transmitted to the WAV _ SPI _ MOSI line and the DSP _ SPI _ MOSI line, and the data is transmitted to the DSP of the data processor from the DSP _ SPI _ MOSI line.

Under the condition, the master MCU can receive data output by the slave Wav chip Flash and the slave DSP can also receive data output by the slave Wav chip Flash, so that data transmission between the two slaves is realized, and the master MCU can not process the received data, so that resources are not occupied in the data transmission process, the data transfer of the master MCU is not carried out, and the data transmission speed is also improved.

Two buffer areas BUF _0 and BUF _1 are arranged in a HiFi kernel of the data processor DSP to store PCM source data, instruction interaction is carried out with a main control MCU in a memory sharing mode, data of the two buffer areas are played in a time-sharing mode and loaded in a time-sharing mode through real-time control of a playing flow task, namely, only audio data of a single buffer area is played at the same time, and then the playing of the audio data of the current buffer area is started after the audio data of the current buffer area is played after the other buffer area is loaded with the data, so that the continuous playing of the Digital chip is realized.

The purpose of adopting the double-buffer mode play management mode is that the size of the audio data of a common Chime is more than 500KB, the RAM in the HiFi Core is limited, the audio data can only be subjected to sub-packet processing, buffer areas are loaded in a time-sharing mode, the two buffer areas are managed to play in turn through accurate control of time points, and therefore continuous playing of the Chime audio data is achieved. For the player, only the audio data of a single buffer zone is played at the same time, at the moment, the other buffer zone needs to load data and waits for the end of the playing of the audio data of the current buffer zone, so that the size of the audio data does not need to be considered, and meanwhile, the playing can be started as long as the loading of the first buffer zone is completed, so that the response speed of the Digital chip is greatly improved, and the application scene of quick sound production on an automobile is met.

The processing program of the HiFi kernel is stored in the HiFi Core Flash, and can be loaded into the HiFi kernel in the program initialization stage, and the main function of the processing program is to take out the audio data of the buffer area according to the left and right sound channels and mix the audio data into the main sound source channel for output. An independent sound mixing module is arranged in the HiFi kernel, Digital chip sound obtained from the buffer area is mixed into a main sound source data path, as shown in fig. 3, and then the superposed signal is transmitted to a data processor DSP and is output to an external power amplifier by the data processor DSP. The HiFi Core can independently open up 8KB for storing audio DATA on RAM allocation, the 8KB is defined as two buffer areas BUF _0 and BUF _1 of 4KB, the MCU adopts a double-buffer mode for play management, and meanwhile, two shared memory areas DATA _ FROM _ HOST and DATA _ TO _ HOST of 1KB are defined and used as instruction interaction TO control a play flow. The memory area DATA _ FROM _ HOST is used for realizing the control writing of the main control MCU TO the HiFi, and the memory area DATA _ TO _ HOST is used for realizing the reading of the play state of the HiFi by the main control MCU. The HiFi can play the audio DATA of the buffer area according TO the control instruction of the shared memory area DATA _ FROM _ HOST, necessary parameter information in playing is updated in the shared memory area DATA _ TO _ HOST, the main control MCU obtains the current playing state of the HiFi, the main control MCU can update the control instruction in the shared memory area DATA _ FROM _ HOST according TO the playing state information, so that time-sharing and continuous playing of BUF _0 and BUF _1 is managed, Digital Chime audio DATA are overlapped into a main audio source DATA path, and then the Digital Chime audio DATA are output TO the DATA processor DSP by the sound mixing module. The control of the whole playing process mainly depends on the control of a master control MCU, the master control MCU realizes double-buffer mode playing, and playing data and loading data are managed in real time.

The main control MCU is used as a control unit for Digital chip playing management, has high requirements on task scheduling and real-time performance of a system, needs to manage each time point in the playing process through a precise timer, optimizes a system scheduling and task management mechanism, ensures that a buffer area is filled in time, and plays without abnormal interruption. The main control MCU adopts a double buffer mode to manage the playing process of Digital chip audio data, as shown in FIG. 4, when an automobile entertainment system program is started and initialization operation is carried out, a Digital chip player can read header information in Wav chip Flash, store PCM source data parameters (chip _ ID, initial address, data length, checksum) of all chips and enter a waiting state; after receiving a Digital chip sounding request on the CAN network, adding a task for starting a Digital chip player into a task list of the system, waiting for system scheduling, and executing the task; when the task scheduling time is up, the Digital Chime player is started. The playing is divided into an initialization loading stage and a circular playing stage, the preparation before playing is carried out in the initialization loading stage, some necessary initialization information is written, BUF _0 audio data is loaded, and the circular playing stage is to control double buffers to carry out staggered loading on data to realize the alternate circular playing of BUF _0 and BUF _1, so that the playing of the whole Chime is completed.

In the initial loading stage, all writing instructions are realized by depending on a shared memory area DATA _ FROM _ HOST, reading instructions are realized by depending on a shared memory area DATA _ TO _ HOST, after a Digital chip player task is started, an emptying instruction is written, the playing state is set TO be idle, and some state variables are cleared; then, the volume parameter of the Superposition of the sound mixing module in the HiFi kernel needs to be set, and the checksum of the PCM source data of the chip is written in; then pointing the buffer to be loaded to the initial address of BUF _0, indexing the initial address and the data length of the audio data of the Chime in the Wav Chime Flash by the Chime _ ID, performing packet processing on the audio data, taking 4KB data as one packet, calculating the total packet number, and loading the first packet of data into BUF _0 from the Wav Chime Flash; the control instruction of the shared memory area DATA _ FROM _ HOST comprises parameters such as total packet number, current packet number, playing mode and the like, the playing control instruction is written in, the audio DATA in BUF _0 is played, and at the moment, the Chime starts playing.

Through the architecture design and the play flow management strategy of the Digital chip player, a Flash-based dual-slave data transmission control strategy can be realized, and a low-delay and high-quality Digital chip player function of playing in a dual-buffer mode is adopted. The method has the advantages that dependence on inherent modules of chip suppliers is eliminated, the HiFi kernel-based universal design is realized, the use of the Chime is greatly simplified, the operation is simple and convenient when the Chime is changed, complicated configuration is not needed, only the Wav Chime Flash data needs to be updated, meanwhile, the sound quality is improved, and rich and diversified sound effects can be freely customized.

As shown in fig. 5, in the implementation structure of the DigitalChime player according to the preferred embodiment, the main control MCU is an RH850 microcontroller of rassa electronics, the data processor DSP is an automobile audio chip Dirana3 (D3 for short) of enginepu, the Wav chip Flash is a 16MB Flash chip with model number N25Q128A, and the HiFi Core Flash is a 2MB plug-in Flash chip. The D3 and the RH850 adopt SPI1 (namely DIRANA3_ SPI1) to carry out command communication, adopt SPI0 as a single data channel, and carry out time division multiplexing and data transmission by HiFi Core Flash and Wav chip Flash (namely, the time division multiplexing is HIFI _ SPI and DSP _ SPI). Digital chip audio data stored by WAV chip Flash adopts PCM format, supports left and right sound channels, has sampling rate of 48KHz, samples by 16 bits, and supports 12 chips in total. The audio data is divided into packets by 4KB, defining a frame of data as 16bit left channel PCM samples and 16bit right channel PCM samples, which are 4 bytes, and 16 frames as a Packet, so that a Packet of data contains 64 packets.

When the RH850 program is started, initialization operation is firstly carried out, header information in the Wav Chime Flash is read through the WAV _ SPI and verified, 12 Chime parameter information is stored if verification is passed, otherwise, initialization is failed, error information is reported, and meanwhile, the D3 loads a HiFi processing program from the HiFi Core Flash through the HIFI _ SPI and enters a HiFi kernel of the D3. After the RH850 is initialized successfully, the HIFI _ SPI channel is cut off, the DSP _ SPI is mounted on the WAV _ SPI, and the Digital chip player enters a waiting state to wait for a chip sounding request signal on the CAN network.

When data needs to be loaded into the buffer area, the RH850 is used as a host to control two slave machines Wav Chime Flash and D3, and a double-slave-machine data transmission control strategy is adopted to realize data loading. Since the size of a single buffer is 4KB, the audio data can be packetized into 4KB packets, when loading data, RH850 first pulls down the D3_ SPI _ CS pin, sends a write command to D3 through DIRANA3_ SPI1, informs D3 that it is ready to write the buffer's head address, data size, and is transmitted using SPI 0; secondly, the RH850 pulls down a WAV _ SPI _ CS pin, sends a reading instruction to the Wav chip Flash through the WAV _ SPI, and informs the Wav chip Flash to prepare to read data; then, when the RH850 receives a data transmission interruption request of the Wav chip Flash, the Wav _ SPI _ MOSI pin of the RH850 is changed from an output mode to an input mode, and then the Wav _ D3_ CS pin is pulled down (at this time, the Wav _ SPI _ CS pin is low), at this time, the DSP _ SPI _ MISO line and the Wav _ SPI _ MISO line are cut off, the Wav _ SPI _ MISO line and the Wav _ SPI _ MOSI line are connected, that is, the DSP _ SPI _ MOSI line and the Wav _ SPI _ MISO line are connected, at this time, audio data exist in the DSP _ SPI _ MOSI line, the Wav _ SPI _ MISO line and the Wav _ SPI _ MOSI line, and data in the Wav _ SPI _ MOSI line are transmitted to the RH850 si, and the RH850 does not need to process the data, and the data in the DSP _ SPI _ MOSI line is transmitted to the D3, and the audio data in the designated buffer 3 can be loaded into the designated buffer area 3; finally, when the data transmission is completed and the pins WAV _ D3_ CS and WAV _ SPI _ CS are pulled up at the same time, the data transmission is finished.

When a sound request signal of the Chime _ X on the CAN network is received, the RH850 indexes parameter information (namely the initial address, the data length and the checksum of PCM source data) corresponding to the Chime _ X according to the ID of the Chime _ X, starts a Digital Chime player task and adds the Digital Chime player task into a system task list, and starts to execute the Digital Chime player task when the task scheduling cycle time is up. Since 4KB audio DATA is used as a packet, the sampling rate is 48KHz, 16-bit sampling is carried out by double channels, the playable time of a single buffer zone can be calculated to be 21.3ms, in a double-slave DATA transmission mechanism, when the SPI0 (namely the DSP _ SPI) of D3 is set at the clock frequency of 7.4MHz, the time required for loading 4KB DATA into the buffer zone is 6.3ms, the filling time of the single buffer zone is controlled to be one third of the playing time of the single buffer zone, the playing continuity can be ensured, the risk of interruption by other tasks is reduced, the specific playing time sequence is shown in figure 6, after a Digital Chime player is started, a clearing instruction is written into a shared memory zone DATA _ OM _ HOST, then a volume parameter of the Superposition and a Checksum of PCM source DATA of the Chime _ X are written in sequence, and finally a playing instruction is written into the Chime _ X to start playing.

After playing of a chip _ X is started, 4KB DATA is started TO be loaded into BUF _1, after DATA loading is finished, the current playing state of HiFi is read through a shared memory area DATA _ TO _ HOST, the current playing state and the total number of packets needing playing can be read as 1 Packet of DATA comprises 64 packets, then whether abnormal conditions such as Underrun and Overrun occur in the playing state or not is judged, if yes, the player is finished, otherwise, according TO the current playing Packet, the BUF _0 residual playing time is calculated, and a timer is started TO wait for the completion of playing of the buffer area. When BUF _0 is played, updating a playing instruction through a shared memory area DATA _ FROM _ HOST, judging whether the DATA is the last packet of DATA, if not, continuing to exchange buffer areas BUF _0 and BUF _1, loading the DATA of the buffer areas, then performing operations such as reading states and the like, realizing continuous and alternate playing of the buffer areas BUF _0 and BUF _1, and if the DATA is the last packet of DATA, ending the Digital chip player, thereby finishing the playing of the whole chip _ X. Therefore, the Digital chip player with low time delay, stereo and high quality can be realized.

The technical means disclosed in the invention scheme are not limited to the technical means disclosed in the above embodiments, but also include the technical scheme formed by any combination of the above technical features. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and such improvements and modifications are also considered to be within the scope of the present invention.

Claims

1. The utility model provides a novel car audio Digital chip player which characterized in that: the high-resolution lossless audio file player is supported to play and is also called a Wav chip, and comprises a main control MCU, a data processor DSP, a first Flash memory and a second Flash memory, wherein the main control MCU is connected with the data processor DSP through an SPI/IIC data bus, the main control MCU is connected with the first Flash memory through an SPI data bus, and the data processor DSP is respectively connected with the first Flash memory and the second Flash memory through an SPI data bus; a HiFi kernel is arranged in the data processor DSP, the data processor DSP is used as a host and the second Flash memory is used as a slave in an initialization stage, a HiFi processing program in the second Flash memory is loaded into the HiFi kernel of the data processor DSP through an SPI data bus, after initialization is finished, communication between the data processor DSP and the second Flash memory is cut off, the SPI data channel is directly mounted on the SPI data channel between the main control MCU and the first Flash memory by the data processor DSP, the main control MCU is used as the host, the first Flash memory is used as the slave, the data processor DSP is switched from the host to the slave, and therefore data transmission between the two slaves is realized by adopting a dual-slave data transmission control strategy; when a Digital chip needs to be played, reading Digital chip audio data from a first Flash memory and transmitting the Digital chip audio data to a HiFi kernel of a data processor DSP, and performing aliasing on a main media sound source and Digital chip sound by the HiFi kernel and outputting the main media sound source and the Digital chip sound to the data processor DSP for subsequent processing and playing; the Digital chip audio data is stored in an external Flash memory and comprises header information and PCM source data, wherein the header information starts from 0x0 address and is used for storing the version number, audio format, channel number, sampling rate, bit sampling, the number of chips capable of supporting and the data parameter of each chip, the data parameter of each chip comprises a chip _ ID, a start address, data length and Checksum, and the PCM source data starts from 0x1000 address and stores all audio data of the stereo chips capable of supporting; the data transmission of the Digital chip player is between a main control MCU, a data processor DSP, a first Flash memory and a second Flash memory, the data transmission operation of the two Flash processors is realized by multiplexing of a single data channel of the data processor DSP, the Digital chip player comprises a program initialization stage and a normal working stage, in the program initialization stage, an SPI (Serial peripheral interface) channel between the data processor DSP and the second Flash memory and an SPI channel WAV-SPI between the main control MCU and the first Flash memory work, on the HIFI-SPI channel, the data processor DSP is used as a host computer, the second Flash memory of the slave computer is controlled, HiFi processing program data in the second Flash memory are transmitted into a HiFi kernel of the data processor DSP, on the WAV-SPI channel, the MCU is used as the host computer, the first Flash memory of the slave computer is controlled, and head information in the first Flash memory is read; and when the program initialization is completed, entering a normal working stage, disconnecting the DSP from the second Flash memory, enabling the HIFI _ SPI channel to not work, enabling the DSP independent data transmission channel DSP _ SPI and the WAV _ SPI channel to work, enabling the main control MCU to serve as a host and the DSP and the first Flash memory to serve as a slave.

2. The novel car audio Digital chip player according to claim 1, wherein the dual slave computer data transmission control strategy is to mount a DSP _ SPI channel on a WAV _ SPI channel between the master MCU and the first FLash memory, share a data line and a clock line of the DSP _ SPI channel and the WAV _ SPI channel, the master MCU controls CS lines of the two slave computers separately, and perform strategy control on timing of the two CS pins to realize data sharing of the master MCU and the data processor DSP.

3. The novel car audio Digital chip player according to claim 2, wherein said dual slave computer data transmission management and control strategy specifically includes the following three steps:

the first step is as follows: when a Digital chip player needs to play a certain Digital chip, the main control MCU firstly sends an instruction through an SPI/IIC communication interface between the main control MCU and the data processor DSP to inform the data processor DSP of the address and the size of data to be written;

the second step is that: the method comprises the steps that header information in Digital chip audio data indexes the initial address and the data length of PCM source data of the Digital chip in a first FLash memory, and a main control MCU initiates a data reading instruction request to the first FLash memory through pulling down a WAV _ CS pin;

the third step: when the main control MCU receives a data transmission interruption request returned by the first FLash memory, the WAV _ MOSI pin of the main control MCU is changed into an input mode from an output mode, the DSP _ CS pin is pulled down at the moment, data in the first FLash memory begin to be transmitted to the main control MCU through the WAV _ SPI _ MISO line, and meanwhile, the WAV _ SPI _ MISO line and the DSP _ SPI _ MOSI line are connected, so that data on the WAV _ SPI _ MISO line are transmitted to the WAV _ SPI _ MOSI line and the DSP _ SPI _ MOSI line, and at the moment, the data are transmitted into the DSP by the DSP _ SPI _ MOSI line.

4. The novel automobile audio Digital chip player according to claim 3, wherein two buffer areas BUF _0 and BUF _1 are provided in a HiFi kernel of the data processor DSP for storing PCM source data, command interaction is performed with the main control MCU in a memory sharing mode, data of the two buffer areas are played in a time-sharing mode and loaded in a time-sharing mode through real-time management and control of a play flow task, namely, only audio data of a single buffer area is played at the same time, and then the audio data of the current buffer area is played after the audio data of the current buffer area is played, so that continuous playing of Digital chip audio data is realized.

5. The novel automobile audio Digital chip player according to claim 4, wherein the processing program of the HiFi kernel is stored in the second Flash memory, an independent sound mixing module is arranged in the HiFi kernel, Digital chip sound obtained from the buffer area is mixed into a main sound source data path, and then the superposed signal is transmitted to the data processor DSP and is output to an external power amplifier by the data processor DSP; the main control MCU is provided with two shared memory areas DATA _ FROM _ HOST and DATA _ TO _ HOST which are used for instructing interaction and controlling a playing process, the HiFi kernel plays audio DATA of a buffer area according TO a control instruction of the shared memory area DATA _ FROM _ HOST and updates necessary parameter information in playing in the shared memory area DATA _ TO _ HOST, the main control MCU acquires the current playing state of the HiFi kernel, and the main control MCU updates a control instruction in the shared memory area DATA _ FROM _ HOST according TO the playing state information, so that time-sharing and continuous playing of BUF _0 and BUF _1 is managed, Digital Chiaudio DATA is superposed into a main audio source DATA passage and then is output TO the DATA processor DSP by the sound mixing module.