CN111509971A

CN111509971A - Integrated circuit, packaging structure and manufacturing method

Info

Publication number: CN111509971A
Application number: CN201910683017.4A
Authority: CN
Inventors: 杨长暻; 王良丞
Original assignee: Delta Electronics Inc
Current assignee: Anchorage Semiconductor Co ltd
Priority date: 2019-01-30
Filing date: 2019-07-26
Publication date: 2020-08-07
Anticipated expiration: 2039-07-26
Also published as: TW202029628A; TWI709294B; CN111509971B; TWI778333B; TW202029441A

Abstract

The invention provides an integrated circuit, a packaging structure and a manufacturing method, wherein the integrated circuit comprises a first power transistor, a second power transistor and an isolator. The first power transistor is integrated with the first driving circuit. The second power transistor is integrated with the second driving circuit. The isolator provides a first control signal to the first power transistor and a second control signal to the second power transistor according to the input signal.

Description

Integrated circuit, packaging structure and manufacturing method

Technical Field

The present invention relates to a driving circuit integrated with a gallium nitride (GaN) power transistor, and more particularly, to a package structure including a driving circuit, an isolator and a GaN power transistor.

Background

FIG. 1 shows a typical power circuit 100 as shown in FIG. 1, an upper bridge driving circuit DRV1 is used to drive a first power transistor 110A, a lower bridge driving circuit DRV2 is used to drive a second power transistor 110B, and a boost capacitor CB and a boost diode DB are used to boost a supply voltage VDD to a boost voltage VB, so that the first power transistor 110A can be fully turned on, therefore, the first power transistor 110A is supplied by an input voltage VIN, and the second power transistor 110B can drive a load device R L through an inductor L and a capacitor C.

Since the inductor L can generate significant parasitic effects on the switching node SW, such as negative voltage spikes generated by the conducting internal diode (body diode) of the second power transistor 110B, these parasitic effects can interfere with the boost voltage VB. when the boost capacitor CB is charged through the power transistor, and thus, the parasitic effects of the driving circuit need to be reduced.

Disclosure of Invention

In view of the above, the present invention provides an integrated circuit including a first power transistor, a second power transistor and an isolator. The first power transistor is integrated with a first driving circuit. The second power transistor is integrated with a second driving circuit. The isolator can provide a first control signal to a first power transistor and a second control signal to a second power transistor according to an input signal.

According to an embodiment of the present invention, the integrated circuit further includes a first power circuit and a second power circuit. The first power circuit includes the first driving circuit and the first power transistor, and the second power circuit includes the second driving circuit and the second power transistor.

According to an embodiment of the present invention, the integrated circuit further includes a bootstrap diode and a bootstrap capacitor. The bootstrap diode includes a bootstrap anode and a bootstrap cathode, wherein the bootstrap anode is coupled to a first supply voltage, and the bootstrap cathode is coupled to a second supply voltage. The bootstrap capacitor is coupled to the second supply voltage and a switching voltage of a switching node.

According to an embodiment of the present invention, the first driving circuit is powered by the second supply voltage and the switching voltage, and generates a first driving voltage at a first driving node according to the first control signal, wherein the first power transistor supplies a high voltage to the switching node according to the driving voltage.

According to an embodiment of the present invention, the second driving circuit is powered by the first supply voltage and a second ground, and generates a second driving voltage at a second driving node according to the second control signal, wherein the second power transistor pulls down the switching voltage to the first ground according to the second driving voltage.

According to an embodiment of the present invention, each of the first power transistor and the second power transistor is a gan transistor.

According to an embodiment of the present invention, the high voltage exceeds the first supply voltage and the second supply voltage.

According to an embodiment of the present invention, the isolator includes a first sub-isolator and a second sub-isolator. The first sub-isolator includes a first transmitter, a first receiver, and a first isolation barrier. The first transmitter is powered by a third supply voltage and a second ground and is capable of transmitting a first RF signal according to the input signal. The first receiver is powered by a second supply voltage and the switching voltage, and generates the first control signal according to the first RF signal. The first isolation barrier is configured to electrically isolate the first transmitter from the first receiver. The second sub-isolator includes a second transmitter, a second receiver, and a second isolation barrier. The second transmitter is powered by a third supply voltage and a second ground and can transmit a second radio frequency signal according to the input signal. The second receiver is powered by the first supply voltage and the first ground, and generates the second control signal according to the second rf signal. The second isolation barrier is configured to electrically isolate the second transmitter from the second receiver.

According to an embodiment of the present invention, the isolator includes a transmitter, a first receiver, a first isolation barrier, a second receiver, and a second isolation barrier. The transmitter is powered by a third supply voltage and a second ground, and can transmit a first radio frequency signal and a second radio frequency signal according to the input signal. The first receiver is powered by the second supply voltage and the switching voltage, and generates the first control signal according to the first rf signal. The first isolation barrier is configured to electrically isolate the transmitter from the first receiver. The second receiver is powered by the first supply voltage and the first ground, and generates the second control signal according to the first rf signal. The second isolation barrier is configured to electrically isolate the transmitter from the second receiver.

According to an embodiment of the present invention, the integrated circuit further includes a decoupling capacitor. The decoupling capacitor is coupled between the high voltage and the first ground, wherein the first sub-isolator, the second sub-isolator, the first power circuit, the second power circuit and the decoupling capacitor are packaged together.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes a pre-driver circuit. The pre-driver circuit generates the first internal signal according to a control signal, wherein the pre-driver circuit is used for improving the driving capability of the control signal, and a driver circuit generates a driving voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit further includes an upper bridge transistor, a lower bridge transistor and a charge pump. The upper bridge transistor provides a supply voltage to a driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to a ground terminal according to the first internal signal. The charge pump is coupled to the upper bridge node and the driving node, wherein the charge pump is configured to generate the upper bridge voltage exceeding the supply voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit further includes a hysteresis circuit. The hysteresis circuit is coupled between the control signal and the pre-driver circuit, and is configured to receive the control signal and generate a second internal signal, such that the pre-driver circuit generates the first internal signal according to the second internal signal, wherein the hysteresis circuit is configured to provide a hysteresis function to the control signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit further includes an upper-bridge normally-on transistor. The top bridge normally-on transistor includes a source terminal coupled to the driving node, a gate terminal coupled to the driving node, and a drain terminal powered by the supply voltage, wherein the top bridge normally-on transistor is configured to enhance a driving capability of the top bridge transistor.

The present invention further provides a package structure, including: a substrate, a decoupling capacitor, an integrated circuit and a conductive layer. The decoupling capacitor is located on the substrate. The integrated circuit and the decoupling capacitor are fixed in a first dielectric layer. The conductive layer is used for electrically coupling the decoupling capacitor to the integrated circuit, wherein the conductive layer is located on the first dielectric layer and penetrates through a second dielectric layer.

According to an embodiment of the present invention, the decoupling capacitor includes a first conductive unit, a first dielectric unit and a second conductive unit. The first conductive unit is formed in the first dielectric layer. The first dielectric element is formed on the first conductive element. The second conductive element is formed on the first dielectric element.

According to an embodiment of the present invention, the package structure further includes a bootstrap capacitor. The bootstrap capacitor is located on the substrate, wherein the integrated circuit and the bootstrap capacitor are fixed in the first dielectric layer or the second dielectric layer.

According to an embodiment of the present invention, the bootstrap capacitor includes a third conductive unit, a second dielectric unit and a fourth conductive unit. The third conductive unit is formed in the first dielectric layer. The second dielectric element is formed on the first conductive element. The fourth conductive element is formed on the second dielectric element.

According to an embodiment of the present invention, the material of the first dielectric unit and the second dielectric unit is different from the material of the first dielectric layer and the second dielectric layer.

According to an embodiment of the present invention, the integrated circuit includes an isolator, a first power circuit and a second power circuit. The isolator can provide a first control signal and a second control signal according to an input signal. The first power circuit includes a first driving circuit and a first power transistor. The first driving circuit is powered by a second supply voltage and a switching voltage, and generates a first driving voltage at a first driving node according to the first control signal, wherein a bootstrap diode and the bootstrap capacitor are used for boosting a first supply voltage to the second supply voltage, wherein the bootstrap diode includes a bootstrap anode coupled to the first supply voltage and a bootstrap cathode coupled to the second supply voltage, and the bootstrap capacitor is coupled between the second supply voltage and the switching voltage at a switching node. The first power transistor may supply a high voltage to the switching node according to the first driving voltage. The second power circuit includes a second driving circuit and a second power transistor. The second driving circuit is powered by the first supply voltage and a first ground terminal, and generates a second driving voltage at a second driving node according to the second control signal. The second power transistor may pull down the switching voltage to the first ground according to the second driving voltage.

According to an embodiment of the present invention, the decoupling capacitor is coupled between the high voltage and the first ground terminal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes a pre-driver circuit. The pre-driver circuit generates the first internal signal according to a control signal, wherein the pre-driver circuit is used for enhancing the driving capability of the control signal, and a driver circuit generates a driving voltage according to the first internal signal.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes an upper bridge transistor, a lower bridge transistor and a charge pump. The upper bridge transistor provides a supply voltage to a driving node according to an upper bridge voltage of an upper bridge node. The lower bridge transistor couples the driving node to a ground terminal according to the first internal signal. The charge pump is coupled to the upper bridge node and the driving node, wherein the charge pump is configured to generate the upper bridge voltage exceeding the supply voltage according to the first internal signal.

According to an embodiment of the present invention, the upper bridge transistor and the lower bridge transistor are both normally-off transistors.

The present invention further provides a manufacturing method for manufacturing a package structure, comprising: providing a decoupling capacitor on a substrate; providing an integrated circuit on the substrate;

fixing the decoupling capacitor and the integrated circuit through a first dielectric and forming a first dielectric layer; forming a conductive line layer on the first dielectric layer to electrically couple the decoupling capacitor to the integrated circuit through the conductive line layer; and fixing the conductive layer and the first dielectric layer by a second dielectric substance, and forming a second dielectric layer on the first dielectric layer.

According to an embodiment of the present invention, the step of providing the decoupling capacitor on the substrate further includes: forming a first conductive unit in the first dielectric layer; forming a first dielectric unit on the first conductive unit; and forming a second conductive element on the first dielectric element.

According to an embodiment of the invention, the manufacturing method further comprises: providing a bootstrap capacitor on the substrate; and fixing the bootstrap capacitor, the decoupling capacitor and the integrated circuit through the first dielectric substance, and forming the first dielectric layer.

According to an embodiment of the present invention, the step of providing the bootstrap capacitor to be disposed on the substrate further includes: forming a third conductive unit in the first dielectric layer; forming a second dielectric unit on the third conductive unit; and forming a fourth conductive unit on the second dielectric unit.

According to an embodiment of the present invention, the integrated circuit includes an isolator, a first power circuit and a second power circuit. The isolator includes a first supply node, a second supply node, a third supply node, a fourth supply node, a first reference node, a second reference node, a third reference node, a fourth reference node, a first input node, a second input node, a first output node, and a second output node. The first power circuit includes a fifth supply node coupled to the second supply node, a sixth supply node, a fifth reference node coupled to the second reference node, and a first PWM node coupled to the first output node. The second power circuit includes a seventh supply node coupled to the fourth supply node, an eighth reference node coupled to the fifth reference node, a sixth reference node, and a second PWM node coupled to the second output node.

According to an embodiment of the invention, the manufacturing method further comprises: forming a first conductive layer on the substrate, wherein the first power circuit and the bootstrap capacitor are disposed on the first conductive layer. The first conductive layer is coupled to a first end of the bootstrap capacitor and the fifth reference node, a second end of the bootstrap capacitor is coupled to the fifth supply node through the conductive line layer, and the sixth supply node is coupled to a third end of the decoupling capacitor through the conductive line layer.

According to an embodiment of the invention, the manufacturing method further comprises: forming a second conductive layer on the substrate. The second power circuit and the decoupling capacitor are disposed on the second conductive layer, wherein the second conductive layer is coupled to a fourth terminal of the decoupling capacitor and a sixth reference node.

According to an embodiment of the invention, the manufacturing method further comprises: forming a third conductive layer on the substrate, wherein the isolator is located on the third conductive layer.

According to an embodiment of the present invention, the first supply node and the third supply node are powered by a third supply voltage, the second supply node and the fifth supply node are powered by a second supply voltage, the first input node receives an input signal, the second input node receives an inverted input signal, the first output node generates a first control signal, the second output node generates a second control signal, the fourth supply node and the seventh supply node are powered by a first supply voltage, the sixth supply node is powered by a high voltage, the first reference node and the third reference node are coupled to a second ground, the fourth reference node and the sixth reference node are coupled to a first ground, wherein the input signal and the inverted input signal are inverted.

According to an embodiment of the present invention, the first power circuit includes a first driving circuit and a first power transistor. The first driving circuit is powered by the second supply voltage and a switching voltage, and generates a first driving voltage at a first driving node according to the first control signal. The first power transistor couples the sixth supply node to the fifth reference node according to the first driving voltage.

According to an embodiment of the present invention, the second power circuit includes a second driving circuit and a second power transistor. The second driving circuit is powered by the first supply voltage and a first ground terminal, and generates a second driving voltage at a second driving node according to the second control signal. The second power transistor couples an eighth supply node to the first ground terminal according to the second driving voltage.

According to an embodiment of the present invention, any one of the first power transistor and the second power transistor is a gan transistor.

According to an embodiment of the present invention, the integrated circuit further includes a bootstrap diode. The bootstrap diode includes a bootstrap anode terminal and a bootstrap cathode terminal, wherein the bootstrap anode terminal is coupled to a first supply voltage, and the bootstrap cathode terminal is coupled to a second supply voltage.

According to an embodiment of the present invention, the isolator includes a first sub-isolator and a second sub-isolator. The first sub-isolator includes: a first transmitter, a first receiver, and a first isolation barrier. The first transmitter is powered by a third supply voltage and a second ground, and transmits a first RF signal according to the input signal. The first receiver is powered by a second supply voltage and the switching voltage, and generates the first control signal according to the first RF signal. The first isolation barrier is configured to electrically isolate the first transmitter from the first receiver. The second sub-isolator includes a second transmitter, a second receiver, and a second isolation barrier. The second transmitter is powered by a third supply voltage and a second ground, and transmits a second RF signal according to the input signal. The second receiver is powered by the first supply voltage and the first ground, and generates the second control signal according to the second rf signal. The second isolation barrier is configured to electrically isolate the second transmitter from the second receiver.

According to an embodiment of the present invention, each of the first power circuit and the second power circuit includes a hysteresis circuit. The hysteresis circuit is coupled between the control signal and the pre-driver circuit, wherein the hysteresis circuit receives the control signal to generate a second internal signal, so that the pre-driver circuit generates the first internal signal according to the second internal signal, and the hysteresis circuit is used for providing a hysteresis function for the control signal.

Drawings

FIG. 1 shows a generic power circuit;

FIG. 2 shows a block diagram of a power circuit according to an embodiment of the invention;

FIG. 3 is a circuit diagram of a charge pump of the power circuit 200 of FIG. 2 according to an embodiment of the invention;

FIG. 4 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 5 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 6 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 7 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 8 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 9 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 10 shows a block diagram of a power circuit according to another embodiment of the invention;

FIG. 11 shows a block diagram of an integrated circuit according to another embodiment of the invention;

FIG. 12 shows a block diagram of an integrated circuit according to another embodiment of the invention;

FIG. 13 shows a block diagram of an integrated circuit according to another embodiment of the invention;

FIG. 14 is a top view of a package structure according to an embodiment of the invention;

FIG. 15 is a cross-sectional view of a package structure according to an embodiment of the invention;

FIGS. 16A-16B illustrate top and cross-sectional views of a first power circuit according to an embodiment of the invention; and

fig. 17A-17F illustrate a manufacturing flow diagram of the package structure 1400 of fig. 14 and the package structure 1500 of fig. 15 according to an embodiment of the invention.

Description of reference numerals:

100. 200, 400, 500, 600, 700, 800, 900, 1000 power circuit

110A first power transistor

110B second power transistor

210. 410, 510, 610, 710, 810, 910 power transistor

220. 420, 520, 620, 720, 820, 920, 1020 drive circuit

221 upper bridge transistor

222 lower bridge transistor

230 charge pump

310 first unidirectional conducting device

320 second unidirectional conducting device

330 third unidirectional conducting device

340 switch

421 upper bridge transistor

423 normally-on transistor

530 first pre-driver circuit

531 first normally-on transistor

532 first normally-off transistor

630. 730 first pre-drive circuit

640. 740 second pre-driver circuit

641 second normally-on transistor

642 second normally-off transistor

750. 850, 950, 1050 first hysteresis circuit

751 third normally-off transistor

752 fourth normally-off transistor

753 fifth normally-off transistor

830. 930, 1030 predrive circuit

931. 1031 first sub pre-driver circuit

932. 1032 second sub-pre-driver circuit

1033 third sub pre-driver circuit

1034 fourth sub-pre-driver circuit

1100. 1200, 1300 integrated circuit

1110 isolator

1120 first Power Circuit

1121 first driving circuit

1122 first power transistor

1130 second power circuit

1131 second driving circuit

1132 second power transistor

1400. 1500 packaging structure

1401 first conductive layer

1402 second conductive layer

1403 third conductive layer

1411 first conductor

1412 second conductor

1510 first dielectric layer

1520 second dielectric layer

1520a first fixed layer

1520b second fixed layer

1521 conductor layer

1521a first metal unit

1521b Metal Unit

1522 first conductive unit

1523 first dielectric unit

1524 second conductive unit

1525 third conductive unit

1526 second dielectric unit

1527 fourth conductive unit

14 base plate

141 first carrier

142 second carrier

143 third carrier

DB bootstrap diode

CB bootstrap capacitor

NBA bootstrap anode

NBC bootstrap cathode

NSW switching node

SIN input signal

SC1 first control signal

SC2 second control signal

SIN input signal

SINB inverting input signal

VDD1 first supply voltage

VDD2 second supply voltage

VDD3 third supply voltage

VSW switching voltage

VD1 first drive Voltage

VD2 second drive Voltage

VHV high voltage

GND1 first ground

GND2 second ground

TX transmitter

T1 first emitter

T2 second emitter

R1 first receiver

R2 second receiver

IB1 first isolation barrier

IB2 second isolation barrier

RF1 first radio frequency signal

RF2 second radio frequency signal

CD decoupling capacitor

NR5 fifth reference node

NR6 sixth reference node

S1, S2 Source terminal

G1 gate terminal

D1 drain terminal

H hole

C capacitor

CB boost capacitor

DRV1 upper bridge driving circuit

DRV2 lower bridge driving circuit

DB boost diode

E1 first sub normally-off transistor

E2 second sub normally-off transistor

E3 third sub normally-off transistor

E4 fourth sub normally-off transistor

E5 fifth sub normally-off transistor

E6 sixth sub-normally-off transistor

E7 seventh sub normally-off transistor

E8 eighth sub normally-off transistor

D1 first sub normally-on transistor

D2 second sub normally-on transistor

D3 third sub normally-on transistor

D4 fourth sub normally-on transistor

L inductance

IP power current

R1 first resistor

R2 second resistor

R L load device

RD discharge resistance

SW switching node

VB boost voltage

VDD supply voltage

VD drive voltage

Upper bridge voltage of VH

VIN input voltage

SC control signal

SB1 first sub-internal Signal

Second sub-internal signal of SB2

SB3 third sub-internal Signal

SI1 first internal signal

SI2 second internal signal

SI3 third internal Signal

ND drive node

NH upper bridge node

N1 first node

N2 second node

N3 third node

Fourth node of N4

Detailed Description

The following description is an example of the present invention. It is intended to illustrate the general principles of the invention and not to limit the invention, the scope of which is defined by the claims.

It is noted that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The following specific examples and arrangements of components are provided to illustrate the principles of the present invention in a simplified form and are not intended to limit the scope of the invention. Moreover, the following description may repeat reference numerals and/or letters in the various examples. However, this repetition is for the purpose of providing a simplified and clear illustration only and is not intended to limit the scope of the various embodiments and/or configurations discussed below. Moreover, the description below of one feature connected to, coupled to, and/or formed on another feature, and the like, may actually encompass a variety of different embodiments that include the feature in direct contact, or that include other additional features formed between the features, and the like, such that the features are not in direct contact.

Fig. 2 shows a block diagram of a power circuit according to an embodiment of the invention. As shown in fig. 2, the power circuit 200 includes a power transistor 210 and a driving circuit 220. The power transistor 210 draws a power current IP according to the driving voltage VD of the driving node ND. According to an embodiment of the present invention, the power transistor 210 is a gallium nitride (GaN) transistor.

The driving circuit 220 includes an upper bridge transistor 221, a lower bridge transistor 222, and a charge pump 230. The upper bridge transistor 221 supplies the supply voltage VDD to the driving node ND according to the upper bridge voltage VH of the upper bridge node NH. The bottom bridge transistor 222 is coupled between the driving node ND and a ground terminal, and pulls the driving voltage VD to a ground level according to the control signal SC. According to an embodiment of the present invention, the upper bridge transistor 221 and the lower bridge transistor 222 are normally-off transistors.

The charge pump 230 is supplied by a supply voltage VDD and a ground terminal, and the charge pump 230 is coupled to the bridge node NH and the driving node ND. To fully turn on the upper bridge transistor 221, the charge pump 230 is configured to generate an upper bridge voltage VH exceeding the supply voltage VDD such that the gate-source voltage of the upper bridge transistor 221 at least exceeds a threshold voltage (threshold voltage) to apply the supply voltage VDD to the driving node ND. According to an embodiment of the present invention, the driving circuit 220 is a full-swing (rail-to-rail) driving circuit, such that the driving voltage VD ranges from the supply voltage VDD to the ground level.

Fig. 3 shows a circuit diagram of a charge pump of the power circuit 200 of fig. 2 according to an embodiment of the invention. As shown in fig. 3, the charge pump 300 coupled to the driving node ND and the upper bridge node NH includes a first unidirectional conducting device 310, a discharge resistor RD, a capacitor C, a second unidirectional conducting device 320, a third unidirectional conducting device 330 and a switch 340.

When the supply voltage VDD exceeds the voltage of the first node N1, the first unidirectional conducting device 310 is conducting. When the supply voltage VDD does not exceed the voltage at the first node N1, the first unidirectional conducting device 310 is non-conducting. The capacitor C is coupled between the first node N1 and the second node N2, and the discharging resistor RD is coupled between the first node N1 and the upper bridge node NH.

The second unidirectional conducting device 320 is coupled between the second node N2 and the upper bridge node NH. When the voltage at the second node N2 exceeds the upper bridge voltage VH, the second unidirectional flux device 320 is turned on. When the voltage at the second node N2 does not exceed the upper bridge voltage VH, the second unidirectional flux device 320 is non-conductive.

The third unidirectional conducting device 330 is coupled between the driving node ND and the second node N2. When the driving voltage VD of the driving node ND exceeds the voltage of the second node N2, the third unidirectional conducting device 330 is turned on. When the driving voltage VD does not exceed the voltage of the second node N2, the third unidirectional conducting device 330 is non-conducting.

The switch 340 receives the control signal SC and is coupled between the upper bridge node NH and ground. In addition, the switch 340 is used for coupling the upper bridge node NH to the ground terminal according to the control signal SC.

For simplicity, the switch 340 is an N-type transistor as an example. According to an embodiment of the present invention, when the control signal SC is at a high voltage level (e.g., the supply voltage VDD), the switch 340 is turned on and the supply voltage VDD charges the capacitor C to the ground terminal through the first unidirectional conducting device 310, the second unidirectional conducting device 320 and the switch 340.

According to another embodiment of the present invention, when the control signal SC is at a low voltage level (e.g., ground level), the switch 340 is turned off, and the third unidirectionally conducting device 330 provides the driving voltage VD to the second node N2, so that the capacitor C is discharged to the driving node ND through the discharging resistor RD.

According to an embodiment of the present invention, the resistance of the discharge resistor RD determines the highest voltage that the capacitor C can charge and also determines the highest voltage that the upper bridge voltage VH can reach. Further, the larger the resistance value of the discharge resistor RD is, the slower the rise time of the upper bridge voltage VD is caused. Therefore, there is a trade-off in the resistance value of the discharge resistor RD.

According to an embodiment of the present invention, each of the first unidirectional conducting device 310, the second unidirectional conducting device 320 and the third unidirectional conducting device 330 is a diode. According to other embodiments of the present invention, each of the first unidirectional conducting device 310, the second unidirectional conducting device 320 and the third unidirectional conducting device 330 is a normally-closed transistor coupled in a diode form.

Fig. 4 shows a block diagram of a power circuit according to another embodiment of the invention. In the power circuit 400 shown in fig. 4, the power transistor 410 and the driving circuit 420 correspond to the power transistor 210 and the driving circuit 220 of fig. 2, respectively.

The driver circuit 420 also includes an upper bridge normally-on transistor 423. The source and gate terminals of the top-bridge normally-on transistor 423 are coupled to the driving node ND, and the drain terminal of the top-bridge normally-on transistor 423 is powered by the supply voltage VDD. The upper bridge normally-on transistor 423 is turned on continuously to improve the driving capability of the upper bridge transistor 221.

Fig. 5 shows a block diagram of a power circuit according to another embodiment of the invention. As shown in fig. 5, the power circuit 500 includes a power transistor 510, a driving circuit 520, and a first pre-driving circuit 530, wherein the power transistor 510 and the driving circuit 520 correspond to the power transistor 210 and the driving circuit 220 of fig. 2, respectively.

The first pre-driver 530 receives the control signal SC and generates a first internal signal SI1 to the driver 520 for improving the driving capability of the control signal SC. The first pre-driver circuit 530 includes a first normally-on transistor 531 and a first normally-off transistor 532.

The gate terminal and the source terminal of the first normally-on transistor 531 are both coupled to the driving circuit 520, and the drain terminal of the first normally-on transistor 531 is powered by the supply voltage. The gate terminal of the first normally-off transistor 532 receives the control signal SC, the source terminal of the first normally-off transistor 532 is coupled to the ground terminal, and the drain terminal of the first normally-off transistor 532 is coupled to the driving circuit 520.

Fig. 6 shows a block diagram of a power circuit according to another embodiment of the invention. As shown in fig. 6, the power circuit 600 includes a power transistor 610, a driving circuit 620, a first pre-driving circuit 630 and a second pre-driving circuit 640, wherein the power transistor 610, the driving circuit 620 and the first pre-driving circuit 630 correspond to the power transistor 510, the driving circuit 520 and the first pre-driving circuit 530 of fig. 5, respectively.

The second pre-driver 640 receives the control signal SC and generates a second internal signal SI2 to the first pre-driver 630 for further improving the driving capability of the control signal SC. The second pre-driver circuit 640 includes a second normally-on transistor 641 and a second normally-off transistor 642.

The gate terminal and the source terminal of the second normally-on transistor 641 are both coupled to the gate terminal of the first normally-off transistor 532 of the first pre-driving circuit 630, and the drain terminal of the second normally-on transistor 641 is powered by the supply voltage VDD. The gate terminal of the second normally-off transistor 642 receives the control signal SC, the source terminal of the second normally-off transistor 642 is coupled to the ground terminal, and the drain terminal of the second normally-off transistor 642 is coupled to the gate terminal of the first normally-off transistor 532 of the first pre-driving circuit 630.

Fig. 7 shows a block diagram of a power circuit according to another embodiment of the invention. As shown in fig. 7, the power circuit 700 includes a power transistor 710, a driving circuit 720, a first pre-driving circuit 730, a second pre-driving circuit 740, and a first hysteresis circuit 750, wherein the power transistor 710, the driving circuit 720, the first pre-driving circuit 730, and the second pre-driving circuit 740 correspond to the power transistor 610, the driving circuit 620, the first pre-driving circuit 630, and the second pre-driving circuit 640 of fig. 6, respectively.

The first hysteresis circuit 750 receives the control signal SC and generates a third internal signal SI3 for further providing a hysteresis function to the control signal SC. The first hysteresis circuit 750 includes a first resistor R1, a third normally-off transistor 751, a fourth normally-off transistor 752, a fifth normally-off transistor 753, and a second resistor R2.

The first resistor R1 is coupled between the supply voltage VDD and the gate terminal of the second normally-closed transistor 642 of the second pre-driver circuit 740, the gate terminal of the third normally-closed transistor 751 is coupled to the third node N3, the source terminal of the third normally-closed transistor 751 is coupled to the fourth node N4, and the drain terminal of the third normally-closed transistor 751 is coupled to the first resistor R1 and the gate terminal of the second normally-closed transistor 642 of the second pre-driver circuit 740. A gate terminal of the fourth normally-off transistor 752 is coupled to the third node N3, a source terminal of the fourth normally-off transistor 752 is coupled to the ground terminal, and a drain terminal of the fourth normally-off transistor is coupled to the fourth node N4.

A gate terminal of the fifth normally-off transistor 753 is coupled to the first resistor R1 and a gate terminal of the second normally-off transistor 642 of the second pre-driver circuit 740, a source terminal of the fifth normally-off transistor 753 is coupled to the fourth node N4, and a drain terminal of the fifth normally-off transistor 753 is powered by the supply voltage VDD. The second resistor R2 is coupled to the third node N3 and receives the control signal SC.

Fig. 8 shows a block diagram of a power circuit according to another embodiment of the invention. As shown in fig. 8, the power circuit 800 includes a power transistor 810, a driving circuit 820, a pre-driving circuit 830, and a first hysteresis circuit 850, wherein the power transistor 810, the driving circuit 820, and the first hysteresis circuit 850 correspond to the power transistor 710, the driving circuit 720, and the first hysteresis circuit 750 of fig. 7, respectively.

According to an embodiment of the present invention, the pre-driver circuit 830 generates the first internal signal SI1 according to the second internal signal SI2 for improving the driving capability of the control signal SC. According to an embodiment of the present invention, the first internal signal SI1 and the second internal signal SI2 are in phase.

Fig. 9 shows a block diagram of a power circuit according to another embodiment of the invention. As shown in fig. 9, the power circuit 900 includes a power transistor 910, a driving circuit 920, a pre-driving circuit 930, and a first hysteresis circuit 950, wherein the power transistor 910, the driving circuit 920, the pre-driving circuit 930, and the first hysteresis circuit 950 correspond to the power transistor 810, the driving circuit 820, the pre-driving circuit 830, and the first hysteresis circuit 850 of fig. 8, respectively.

As shown in fig. 9, the pre-driver circuit 930 includes a first sub pre-driver circuit 931 and a second sub pre-driver circuit 932. The first sub pre-driver circuit 931 includes a first sub normally-off transistor E1, a second sub normally-off transistor E2, and a first sub normally-on transistor D1, wherein the first sub pre-driver circuit 931 generates the first internal signal SI1 according to the first sub internal signal SB 1.

The gate terminal of the first sub normally-closed transistor E1 receives the first sub internal signal SB1, and the source terminal of the first sub normally-closed transistor E1 is coupled to the ground terminal. The gate terminal of the second sub normally-closed transistor E2 receives the second internal signal SI 2. That is, the gate terminal of the second sub-normally-closed transistor E2 is coupled to the gate terminal of the third sub-normally-closed transistor E3. The drain terminal of the second sub normally-closed transistor E2 is powered by the supply voltage VDD.

The source terminal of the second sub normally-closed transistor E2 is coupled to the drain terminal of the first sub normally-closed transistor E1, wherein the drain terminal of the first sub normally-closed transistor E1 is called the first internal signal SI1 and is provided to the driving circuit 920. The gate terminal and the source terminal of the first sub normally-on transistor D1 are coupled together, and the source terminal of the first sub normally-on transistor D1 is powered by the supply voltage VDD.

The second sub pre-driver circuit 932 includes a third sub normally-closed transistor E3, a fourth sub normally-closed transistor E4, and a second sub normally-on transistor D2, wherein the second sub pre-driver circuit 932 generates the first sub internal signal SB1 according to the second internal signal SI 2.

The gate terminal of the third sub normally-closed transistor E3 receives the second internal signal SI2, and the source terminal of the third sub normally-closed transistor E3 is coupled to the ground terminal. The gate terminal of the fourth sub normally-closed transistor E4 is coupled to the third node N3 of the first hysteresis circuit 950, and the drain terminal of the fourth sub normally-closed transistor E4 is powered by the supply voltage VDD.

The source terminal of the fourth sub normally-closed transistor E4 is coupled to the drain terminal of the third sub normally-closed transistor E3, wherein the drain terminal of the third sub normally-closed transistor E4 generates the first sub internal signal SB1 and provides the first sub pre-driver circuit 931. The gate terminal and the source terminal of the second sub normally-on transistor D2 are coupled together, and the drain terminal of the second sub normally-on transistor D2 is powered by the supply voltage VDD.

Fig. 10 shows a block diagram of a power circuit according to another embodiment of the invention. As shown in fig. 10, the power circuit 1000 includes a power transistor 1010, a driving circuit 1020, a pre-driving circuit 1030, and a first hysteresis circuit 1050, wherein the power transistor 1010, the driving circuit 1020, the pre-driving circuit 1030, and the first hysteresis circuit 1050 correspond to the power transistor 910, the driving circuit 920, the pre-driving circuit 930, and the first hysteresis circuit 950 of fig. 9, respectively.

As shown in fig. 10, the pre-driving circuit 1030 includes a first sub pre-driving circuit 1031, a second sub pre-driving circuit 1032, a third sub pre-driving circuit 1033 and a fourth sub pre-driving circuit 1034, wherein the first sub pre-driving circuit 1031 and the second sub pre-driving circuit 1032 correspond to the first sub pre-driving circuit 931 and the second sub pre-driving circuit 932 of fig. 9, respectively, and the description thereof is not repeated here.

The second sub pre-driver circuit 1032 includes a third sub normally-off transistor E3, a fourth sub normally-off transistor E4, and a second sub normally-on transistor D2, wherein the second sub pre-driver circuit 1032 generates the first sub internal signal SB1 according to the second sub internal signal SB 2.

The gate terminal of the third sub normally-closed transistor E3 receives the second sub internal signal SB2, and the source terminal of the third sub normally-closed transistor E3 is coupled to the ground terminal. The gate terminal of the fourth sub normally-closed transistor E4 receives the third sub internal signal SB 3. The drain terminal of the fourth sub normally-closed transistor E4 is supplied by the supply voltage VDD.

A source terminal of the fourth sub normally-closed transistor E4 is coupled to a drain terminal of the third sub normally-closed transistor E3, wherein a drain terminal of the third sub normally-closed transistor E3 generates the second sub internal signal SB2 to the first sub pre-driver circuit 1031. The gate terminal and the source terminal of the second sub normally-on transistor D2 are coupled together, and the drain terminal of the second sub normally-on transistor D2 is powered by the supply voltage VDD.

The third sub pre-driver circuit 1033 includes a fifth sub normally-closed transistor E5, a sixth sub normally-closed transistor E6, and a third sub normally-on transistor D3, wherein the third sub-driver circuit 1033 generates the second sub internal signal SB2 according to the third sub internal signal SB 3.

The gate terminal of the fifth sub normally-closed transistor E5 receives the third sub internal signal SB3, and the source terminal of the fifth sub normally-closed transistor E5 is coupled to the ground terminal. The gate terminal of the sixth sub normally-closed transistor E6 receives the second internal signal SI2, and the drain terminal of the sixth sub normally-closed transistor E6 is powered by the supply voltage VDD.

A source terminal of the sixth sub normally-off transistor E6 is coupled to a drain terminal of the fifth sub normally-off transistor E5, wherein a drain terminal of the fifth sub normally-off transistor E5 generates the second sub internal signal SB2 to the second sub pre-driver circuit 1032. The gate terminal and the source terminal of the third sub normally-on transistor D3 are coupled together, and the drain terminal of the third sub normally-on transistor D3 is powered by the supply voltage VDD.

The fourth sub pre-driver circuit 1034 includes a seventh sub normally-closed transistor E7, an eighth sub normally-closed transistor E8, and a fourth sub normally-on transistor D4, wherein the fourth sub pre-driver circuit 1034 generates the third sub internal signal SB3 according to the second internal signal SI 2.

The gate terminal of the seventh sub normally-closed transistor E7 receives the second internal signal SI2, and the source terminal of the seventh sub normally-closed transistor E7 is coupled to the ground terminal. A gate terminal of the eighth sub normally-closed transistor E8 is coupled to the third node N3 of the first hysteresis circuit 1050. The drain terminal of the eighth sub normally-closed transistor E8 is supplied by the supply voltage VDD.

The source terminal of the eighth sub normally-closed transistor E8 is coupled to the drain terminal of the seventh sub normally-closed transistor E7, wherein the drain terminal of the seventh sub normally-closed transistor E7 generates the third sub internal signal SB3 to the third sub pre-driver circuit 1033. The gate terminal and the source terminal of the fourth sub normally-on transistor D4 are coupled together, and the drain terminal of the fourth sub normally-on transistor D4 is powered by the supply voltage VDD.

According to other embodiments of the present invention, the pre-driver circuit 830 of fig. 8 may include an even number of sub-pre-driver circuits, such that the phases of the first internal signal SI1 and the second internal signal SI2 are in phase.

Fig. 11 shows a block diagram of an integrated circuit according to another embodiment of the invention. As shown in fig. 11, the integrated circuit 1100 includes an isolator 1110, a first power circuit 1120, a second power circuit 1130, a bootstrap diode DB, and a bootstrap capacitor CB.

The isolator 1110 generates a first control signal SC1 and a second control signal SC2 according to the input signal SIN. According to some embodiments of the invention, the input signal SIN may be externally generated. As shown in fig. 11, the inverted input signal SINB is generated by the inverter INV. Isolator 1110 generates a first control signal SC1 based on the inverted input signal SINB and a second control signal SC2 based on the input signal SIN. According to other embodiments of the present invention, the inverted input signal SINB and the input signal SIN may be generated externally.

The first power circuit 1120 includes a first driving circuit 1121 and a first power transistor 1122, and the second power circuit 1130 includes a second driving circuit 1131 and a second power transistor 1132. According to an embodiment of the present invention, the first driving circuit 1121 is the same as the second driving circuit 1131, and the first power transistor 1122 is the same as the second power transistor 1132.

According to an embodiment of the invention, each of the first driving circuit 1121 and the second driving circuit 1131 may correspond to one of the driving circuit 220 of fig. 2 and 3, the driving circuit 420 of fig. 4, the combination of the driving circuit 520 and the first pre-driving circuit 530 of fig. 5, the combination of the driving circuit 620, the first pre-driving circuit 630 and the second pre-driving circuit 640 of fig. 6, the combination of the driving circuit 720, the first pre-driving circuit 730, the second pre-driving circuit 740, and the first hysteresis circuit 750 of fig. 7, the combination of the driving circuit 820, the pre-driving circuit 830, and the first hysteresis circuit 850 of fig. 8, the combination of the driving circuit 920, the pre-driving circuit 930, and the first hysteresis circuit 950 of fig. 9, and the combination of the driving circuit 1020, the pre-driving circuit 1030, and the first hysteresis circuit 1050 of fig. 10.

According to an embodiment of the invention, the first power transistor 1122 and the second power transistor 1132 may correspond to any one of the power transistor 210 of fig. 2, the power transistor 410 of fig. 4, the power transistor 510 of fig. 5, the power transistor 610 of fig. 6, the power transistor 710 of fig. 7, the power transistor 810 of fig. 8, the power transistor 910 of fig. 9, and the power transistor 1010 of fig. 10.

As shown in fig. 11, the bootstrap diode DB includes a bootstrap anode NBA coupled to the first supply voltage VDD1 and a bootstrap cathode NBC coupled to the second supply voltage VDD 2. The bootstrap capacitor CB is coupled to the second supply voltage VDD2 and the switch node NSW. According to an embodiment of the present invention, the bootstrap diode DB and the bootstrap capacitor CB are configured to mute the first supply voltage VDD1 to the second supply voltage VDD2 according to the switching voltage VSW of the switching node NSW.

The first driving circuit 1121 is powered by the second supply voltage VDD2 and the switching voltage VSW and generates the first driving voltage VD1 according to the first control signal SC 1. The first power transistor 1122 supplies the high voltage VHV to the switching node NSW according to the first driving voltage VD 1.

The second driving circuit 1131 is powered by the first supply voltage VDD1 and the first ground GND1, and generates the second driving voltage VD2 according to the second control signal SC 2. The second power transistor 1132 couples the switch node NSW to the first ground GND1 according to the second driving voltage VD 2.

According to an embodiment of the invention, when the first power transistor 1122 is turned off and the second power transistor 1132 is turned on, the switching voltage VSW is coupled to the first ground GND1, and the second supply voltage VDD2 is equal to the first supply voltage VDD1 minus the forward conduction voltage of the bootstrap diode DB.

According to another embodiment of the present invention, when the first power transistor 1122 is turned on and the second power transistor 1132 is turned off, the switching voltage VSW is coupled to the high voltage VHV, such that the second supply voltage VDD2 is boosted to the sum of the high voltage VHV and the first supply voltage VDD1, thereby turning on the first power transistor 1122 completely.

Fig. 12 shows a block diagram of an integrated circuit according to another embodiment of the invention. As shown in fig. 12, the integrated circuit 1200 includes an isolator 1110, a first power transistor 1120, a second power circuit 1130, a bootstrap diode DB, and a bootstrap capacitor CB, wherein the isolator 1110 includes a transmitter TX, a first receiver R1, a first isolation barrier IB1, a second receiver R2, and a second isolation barrier IB 2.

The transmitter TX is powered by a third supply voltage VDD3 and a second ground GND2, wherein the transmitter TX modulates the input signal SIN to generate a first RF signal RF1 across the first isolation barrier IB1 and modulates the inverted input signal SINB to generate a second RF signal RF2 across the second isolation barrier IB 2.

The first receiver R1 is powered by the second supply voltage VDD2 and the second switching voltage VSW, wherein the first receiver R1 demodulates the first RF signal RF1 to generate the first control signal SC 1. The first isolation barrier IB1 is used to electrically isolate the transmitter TX and the first receiver R1.

The second receiver R2 is powered by the first supply voltage VDD1 and the first ground GND1, wherein the second receiver R2 demodulates the second RF signal RF2 to generate the second control signal SC 2. The second isolation barrier IB2 is used to electrically isolate the transmitter TX and the second receiver R2.

According to an embodiment of the invention, the first ground GND1 may be the same as the second ground GND 2. According to another embodiment of the invention, the first ground GND1 may be different from the second ground GND 2. According to an embodiment of the present invention, the high voltage VHV exceeds the first supply voltage VDD1, the second supply voltage VDD2 and the third supply voltage VDD 3.

According to an embodiment of the invention, the first supply voltage VDD1 may be the same as the third supply voltage VDD 3. According to another embodiment of the present invention, the first supply voltage VDD1 may be different from the third supply voltage VDD 3.

As shown in fig. 12, the integrated circuit 1200 further includes a decoupling capacitor CD. The decoupling capacitor CD is coupled to the high voltage VHV and the first ground GND 1. According to an embodiment of the invention, the isolator 1110, the first power circuit 1120, the second power circuit 1130, and the decoupling capacitor CD are packaged together. According to another embodiment of the present invention, the isolator 1110, the first power circuit 1120, the second power circuit 1130, the bootstrap capacitor CB, and the decoupling capacitor CD are packaged together.

Fig. 13 shows a block diagram of an integrated circuit according to another embodiment of the invention. As shown in fig. 13, the integrated circuit 1300 includes an isolator 1110, a first power circuit 1120, a second power circuit 1130, a bootstrap diode DB, and a bootstrap capacitor CB, wherein the isolator 1110 includes a first sub-isolator 1111 and a second sub-isolator 1112.

The first sub-isolator 1111 includes a first transmitter T1, a first receiver R1 and a first isolation barrier IB 1. The first transmitter T1 is powered by the third supply voltage VDD3 and the second ground GND2, wherein the first transmitter T1 modulates the input signal SIN to generate the first RF signal RF1 across the first isolation barrier IB 1. The first receiver R1 is powered by the second supply voltage VDD2 and the switch voltage SW, wherein the first receiver R1 demodulates the first RF signal RF1 to generate the first control signal SC 1. The first isolation barrier IB1 is used to electrically isolate the first transmitter T1 from the first receiver R1.

The second sub-isolator 1112 includes a second transmitter T2, a second receiver R2, and a second isolation barrier IB 2. The second transmitter T2 is powered by a third supply voltage VDD3 and a second ground GND2, wherein the second transmitter T2 modulates the inverted input signal SINB to generate a second RF signal RF2 across the second isolation barrier IB 2. The second receiver R2 is powered by the first supply voltage VDD1 and the first ground GND1, wherein the second receiver R2 demodulates the second RF signal RF2 to generate the second control signal SC 2. The second isolation barrier IB2 is used to electrically isolate the second transmitter T2 from the second receiver R2.

As shown in fig. 13, integrated circuit 1300 further includes decoupling capacitor CD. The decoupling capacitor CD is coupled between the high voltage VHV and the first ground GND 1. According to an embodiment of the present invention, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, the second power circuit 1130, and the decoupling capacitor CD are packaged together. According to another embodiment of the present invention, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, the second power circuit 1130, the bootstrap capacitor CB, and the decoupling capacitor CD are packaged together.

Fig. 14 is a top view illustrating a package structure according to an embodiment of the invention. As shown in fig. 14, the package structure 1400 includes the decoupling capacitor CD, the bootstrap capacitor CB, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, and the second power circuit 1130 shown in fig. 13. According to an embodiment of the invention, the package structure 1400 is located on the substrate 14.

As shown in fig. 14, the package structure 1400 further includes a first conductive layer 1401, a second conductive layer 1402, and a third conductive layer 1403. A first conductive layer 1401, a second conductive layer 1402, and a third conductive layer 1403 are formed over the substrate 14.

As shown in fig. 14, the first power circuit 1120 and the bootstrap capacitor CB are located on the first conductive layer 1401. The second power circuit 1130 and the decoupling capacitor CD are located on the second conductive layer 1402. The first sub-isolator 1111 and the second sub-isolator 1112 are located on the third conductive layer 1403.

According to an embodiment of the invention, the first conductive layer 1401, the second conductive layer 1402 and the third conductive layer 1403 are electrically isolated from each other. According to an embodiment of the invention, the first conductive layer 1401 is electrically coupled to the first ground GND1, and the second conductive layer 1402 is electrically coupled to the switching voltage VSW, wherein the switching voltage VSW is coupled to the fifth reference node NR 5.

As shown in fig. 14, the fifth reference node NR5 is coupled to the source terminal S1 of the first power transistor 1122, wherein the fifth reference node NR5 is electrically coupled to the first conductive layer 1401 via the conductive trace and the first conductor 1411.

The sixth reference node NR6 is coupled to the source terminal S2 of the second power transistor 1132, wherein the sixth reference node NR6 is used to electrically connect the conductive trace layer to the second conductive layer 1402.

The bootstrap diode DB shown in fig. 13 is placed outside the package structure 1400 according to an embodiment of the present invention.

Fig. 15 is a cross-sectional view of a package structure according to an embodiment of the invention. As shown in fig. 15, the package structure 1500 is a cross-sectional view along the dashed line from the first end a to the second end a' in fig. 14.

The package structure 1500 includes a substrate 14, a first sub-isolator 1111, a first power circuit 1120, a bootstrap capacitor CB, a decoupling capacitor CD, and a conductive line layer 1521. The substrate 14 includes a first carrier 141, a second carrier 142, and a third carrier 143, wherein the first carrier 141, the second carrier 142, and the third carrier 143 are isolated from each other.

The first power circuit 1120 and the bootstrap capacitor CB are located on the first carrier 141, and the decoupling capacitor CD and the second power circuit 1130 (not shown in fig. 15) are located on the second carrier 142. The first sub-isolator 1111 and the second sub-isolator 1112 (not shown in fig. 15) are located on the third carrier 143.

According to some embodiments of the present invention, the first conductive unit 1522 and the first power circuit 1120 are located on the first conductive layer 1401, wherein the first conductive layer 1401 is located on the first carrier 141. The decoupling capacitor CD and the second power circuit 1130 (not shown in fig. 15) are located on the second conductive layer 1402, wherein the second conductive layer 1402 is located on the second carrier 142. The first sub-isolator 1111 and the second sub-isolator 1112 (not shown in fig. 15) are located on the third conductive layer 1403, wherein the third conductive layer 1403 is located on the third carrier 143.

The material of the first, second and

third carriers

141, 142 and 143 may be (or include) copper, aluminum, gold, silver, tin, platinum, alloys thereof, and the like. The first carrier 141 and the first conductive layer 1401 may be the same or different materials. The third carrier 143 and the third conductive layer 1403 may be the same or different materials.

The package structure 1500 further includes a first dielectric layer 1510 and a second dielectric layer 1520, wherein the first sub-isolator 1111, the second sub-isolator 1112 (not shown in fig. 15), the first power circuit 1120, the second power circuit 1130 (not shown in fig. 15), the bootstrap capacitor CB, and the decoupling capacitor CD are fixed together in the first dielectric layer 1510.

The conductive line 1521 is disposed on the first dielectric layer 1510 and passes through the second dielectric layer 1520. In some embodiments, the first dielectric layer 1510 is formed by a molding process of a first dielectric, thereby fixing the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120 and the second power circuit 1130.

The conductive layer 1521 is electrically coupled to the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120 and the second power circuit 1130. In some embodiments, the material of the conductive line layer 1521 is metal, and is formed by using laser drilling and metal plating processes. The detailed manufacturing method will be described in detail below.

As shown in fig. 15, the bootstrap capacitor CB includes a first conductive unit 1522, a first dielectric unit 1523 and a second conductive unit 1524. The first conductive element 1522 and the second conductive element 1524 may be copper pillars. The first conductive unit 1522 is located in the first dielectric layer 1510. Similarly, the decoupling capacitor CD includes a third conductive element 1525, a second dielectric element 1526 and a fourth conductive element 1527. The first conductive unit 1522, the second conductive unit 1524, the third conductive unit 1525 and the fourth conductive unit 1527 may be copper pillars. The third conductive unit 1525 is located in the first dielectric layer 1510.

As shown in fig. 15, a first dielectric element 1523 and a second conductive element 1524 are disposed on the first conductive element 1522, and a second dielectric element 1526 and a fourth conductive element 1527 are disposed on the third conductive element 1525. The first conductive unit 1522, the first dielectric unit 1523 and the second conductive unit 1524 form a bootstrap capacitor CB, and the third conductive unit 1525, the second dielectric unit 1526 and the fourth conductive unit 1527 form a decoupling capacitor CD.

In order to adjust the capacitance of the bootstrap capacitor CB, the material of the first dielectric unit 1523 may be different from the material of the first dielectric layer 1510 and the material of the second dielectric layer 1520. For example, the first dielectric element 1523 may be ceramic or mica, wherein the material of the first dielectric element 1523 is different from the material of the first dielectric. In some other embodiments, the bootstrap capacitor CB does not include the first dielectric unit 1523. The first conductive element 1522 is a first distance from the second conductive element 1524, and a first dielectric of the first dielectric layer 1510 can fill a space between the first conductive element 1522 and the second conductive element 1524. In other words, the material of the first dielectric unit 1523 may be the same as the material of the first dielectric layer 1510.

To adjust the capacitance of the decoupling capacitor CD, the material of the second dielectric unit 1526 may be different from the material of the first dielectric layer 1510 and the material of the second dielectric layer 1520. For example, the material of the second dielectric element 1526 may be ceramic or mica, wherein the material of the second dielectric element 1526 is different from the material of the first dielectric. In all other embodiments, the decoupling capacitor CD does not include the second dielectric element 1525. The third conductive element 1525 is a second distance from the fourth conductive element 1527. the first dielectric of the first dielectric layer 1510 can fill a space between the third conductive element 1525 and the fourth conductive element 1527. In other words, the material of the second dielectric unit 1526 may be the same as the material of the first dielectric layer 1510.

According to some embodiments of the present invention, the first distance of the bootstrap capacitor CB is the same as or different from the second distance of the decoupling capacitor CD.

As shown in fig. 15, in some embodiments, a first conductive element 1522 and a first dielectric element 1523 are disposed within a first dielectric layer 1510, and a second conductive element 1524 is disposed within a second dielectric layer 1520. The second conductive element 1524 and the conductive line layer 1521 are fixed by the second dielectric layer 1520, and the second conductive element 1524 is electrically coupled to the first power circuit 1120 through the conductive line layer 1521. However, in other embodiments, the first conductive element 1522, the first dielectric element 1523, and the second conductive element 1524 may all be disposed within the first dielectric layer 1510 and fixed by the first dielectric of the first dielectric layer 1510, depending on the manufacturing method. The second conductive element 1524 is electrically coupled to the first power circuit 1120 through the conductive layer 1521. The detailed manufacturing method will be described in detail below.

As shown in fig. 15, in some embodiments, the third conductive element 1525 and the second dielectric element 1526 are both disposed in the first dielectric layer 1510, and the fourth conductive element 1527 is disposed in the second dielectric layer 1520. The fourth conductive element 1527 and the conductive line layer 1521 are fixed by the second dielectric layer 1520, and the fourth conductive element 1527 is electrically coupled to the first power circuit 1120 through the conductive line layer 1521. However, in other embodiments, the third conductive element 1525, the second dielectric element 1526 and the fourth conductive element 1527 may all be disposed within the first dielectric layer 1510 and fixed by the first dielectric of the first dielectric layer 1510 according to different manufacturing methods. The fourth conductive element 1527 is electrically coupled to the first power circuit 1120 through the conductive layer 1521. The detailed manufacturing method will be described in detail below.

Fig. 16A-16B are top and cross-sectional views of a first power circuit according to an embodiment of the invention. Fig. 16A shows a top view of the first power circuit 1120. As shown in fig. 16A, the source terminal S1, the gate terminal G1, and the drain terminal D1 of the first power transistor 1122 are as shown. The first driving circuit 1121 is located below the source terminal S1 and the gate terminal G1 of the first power transistor 1122.

Fig. 16B shows a cross-sectional view of the first power circuit 1120. As shown in fig. 16B, the first power transistor 1122 is located below the first driving circuit 1121 and the drain terminal D1 of the first power transistor 1122.

Referring to fig. 14 and 15, the first conductor 1411 of fig. 14 may be a copper pillar. The first conductor 1411 is disposed above the first carrier 141 and coupled to one end (i.e., the bottom) of the bootstrap capacitor CB through the first conductive layer 1401, and the wiring layer 1521 of fig. 15 is electrically coupled to the other end (i.e., the top) of the bootstrap capacitor CB. In other words, the source terminal S1 (i.e., the fifth reference node NR5) of the first power transistor 1122 is electrically coupled to the first conductive layer 1401 via the conductive line layer 1521 and the first conductor 1411.

The second conductor 1412 of fig. 14 may be a copper pillar. The second conductor 1412 is located above the second carrier 142 and is electrically coupled to one end (i.e., the bottom) of the decoupling capacitor CD through the second conductive layer 1402. The conductive line layer 1521 of fig. 15 is electrically coupled to the other end (i.e., the top surface) of the decoupling capacitor CD. In other words, the source terminal S2 (i.e., the sixth reference node NR6) of the second power transistor 1132 is electrically coupled to the second conductive layer 1402 through the conductive line layer 1521 and the second conductor 1412.

Fig. 17A-17F illustrate a manufacturing flow diagram of the package structure 1400 of fig. 14 and the package structure 1500 of fig. 15 according to an embodiment of the invention. As shown in fig. 17A, a first conductive unit 1522, a third conductive unit 1525, a first sub-isolator 1111, a second sub-isolator 1112, a first power circuit 1120, a second power circuit 1130, a first conductor 1411, and a second conductor 1412 are located on the substrate 14.

In some embodiments, the first conductive unit 1522 of the bootstrap capacitor CB is formed on the first carrier 141, and the first conductive layer 1401 is located between the first conductive unit 1522 and the first carrier 141. The first power circuit 1120 and the second power circuit 1130 are located on the first carrier 141. The decoupling capacitor CD is formed on the second carrier 142, and the second conductive layer 1402 is located between the decoupling capacitor CD and the second carrier 142. The first sub-isolator 1111 and the second sub-isolator 1112 are located on the third carrier 143, and the third conductive layer 1403 is located between the first sub-isolator 1111 and the second sub-isolator 1112 and the third carrier 143.

As shown in fig. 17A, a first dielectric element 1523 and a second dielectric element 1526 are formed over the first conductive element 1522 and the third conductive element 1525, respectively.

As shown in fig. 17B, the first conductive element 1522, the first dielectric element 1523, the third conductive element 1525, the second dielectric element 1526, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, and the second power circuit 1130 are fixed together by a first dielectric, and form a first dielectric layer 1510. In some embodiments, the material of the first dielectric may be Epoxy Resin (Epoxy) or BT Resin (Bismaleimide Triazine Resin).

As shown in fig. 17C to 17E, the first fixing layer 1520a over the first dielectric layer 1510 is formed by a molding process. Next, a plurality of first metal units 1521a are formed by laser drilling and metal plating processes. In some embodiments, as shown in fig. 17C and 17D, after the first fixing layer 1520a is formed by an encapsulation process, the first fixing layer 1520a is etched to generate a plurality of holes H corresponding to all the terminals of the first dielectric element 1522, the first conductor 1411, the second conductor 1412, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120 and the second power circuit 1130. Next, as shown in fig. 17E, a first metal unit 1521a is formed on the first dielectric layer 1510 through the first fixed layer 1520a processed by laser drilling and metal plating processes. In some embodiments, one of the first metal cells 1521a becomes a second conductive cell 1524 and one of the first metal cells 1521a becomes a fourth conductive cell 1527. The first fixing layer 1520a on the first dielectric layer 1510 is used to fix the second conductive unit 1524, the fourth conductive unit 1527 and the first metal unit 1521 a.

Referring to fig. 17F, after the first pinned layer 1520a is stroked, a second pinned layer 1520b and a plurality of second metal units 1521b are formed on the first pinned layer 1520 a. The first metal unit 1521a and the second metal unit 1521b form a conductive line layer 1521, such that the first sub-isolator 1111, the second sub-isolator 1112, the first power single circuit 1120, the second power circuit 1130, the bootstrap capacitor CB, and the decoupling capacitor CD are electrically coupled as shown in fig. 13.

The manufacturing method provided herein can directly place the bootstrap capacitor CB and the decoupling capacitor CD packaged in the same package structure on the substrate 14. That is, the first conductive unit 1522, the first dielectric unit 1523 and the second conductive unit 1524 are formed as the bootstrap capacitor CB, and the third conductive unit 1525, the second dielectric unit 1526 and the fourth conductive unit 1527 are formed as the decoupling capacitor CD. Then, the bootstrap capacitor CB and the decoupling capacitor CD are disposed on the substrate 14.

According to other embodiments of the present invention, the first conductive element 1522, the first dielectric element 1523, the third conductive element 1525 and the second dielectric element 1526 are packaged together and then placed on the substrate 14. Next, after forming a first dielectric layer 1510 covering the first conductive unit 1522, the first dielectric unit 1523, the third conductive unit 1525 and the second dielectric unit 1526, a second conductive unit 1524 and a fourth conductive unit 1527 are formed on the first dielectric layer 1510.

In the embodiment shown in fig. 17A-17F, a second conductive element 1524 is formed over the first dielectric element 1523 and over the second dielectric layer 1520, and a fourth conductive element 1527 is formed over the second dielectric element 1526 and over the second dielectric layer 1520. In some embodiments of other fabrication methods, after forming the first and second

dielectric elements

1523 and 1526 over the first and third

conductive elements

1522 and 1525, respectively, the second conductive element 1522 is formed over the first dielectric element 1523 and the fourth conductive element 1527 is formed over the second dielectric element 1526.

Next, the first conductive element 1522, the first dielectric element 1523, the second conductive element 1524, the third conductive element 1525, the second dielectric element 1526, and the fourth conductive element 1527 are fixed by using the first dielectric. That is, the first conductive element 1522, the first dielectric element 1523, the second conductive element 1524, the third conductive element 1525, the second dielectric element 1526 and the fourth conductive element 1527 are all disposed in the first dielectric layer 1510.

In some embodiments, after the first conductive unit 1522 and the third conductive unit 1526 are formed on the substrate 14, the first dielectric fixes the first conductive unit 1522, the third conductive unit 1526, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, and the second power circuit 1130. In this embodiment, the first dielectric is used as a material for the first dielectric element 1523 and/or the second dielectric element 1526.

After the first dielectric layer 1510 is formed, the second conductive unit 1524 is disposed on the first dielectric layer 1510, and the fourth conductive unit 1527 is disposed on the first dielectric layer 1510. The first conductive element 1522 is a first distance from the second conductive element 1524, and the third conductive element 1525 is a second distance from the fourth conductive element 1527, wherein the first distance and the second distance are the same or different.

Therefore, the first conductive unit 1522, the second conductive unit 1524 and the first dielectric between the first conductive unit 1522 and the second conductive unit 1524 form a bootstrap capacitor CB, and the third conductive unit 1525, the fourth conductive unit 1527 and the first dielectric between the third conductive unit 1525 and the fourth conductive unit 1527 form a decoupling capacitor CD.

According to some embodiments of the invention, after the metal unit 1521a is formed by using laser drilling and metal plating processes, the second dielectric layer 1520 is formed again, and a plurality of holes are formed again. Next, a metal unit 1522b is formed by laser drilling and a metal plating process. Accordingly, the first sub-isolator 1111, the second sub-isolator 1112, the first power circuit 1120, the second power circuit 1130, the bootstrap capacitor CB, and the decoupling capacitor CD are electrically coupled together.

What has been described above is a general characterization of the embodiments. Those skilled in the art should readily appreciate that they can readily use the present disclosure as a basis for designing or modifying other structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that the same may be used without departing from the spirit and scope of the present invention and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention. The illustrative method represents exemplary steps only, and the steps are not necessarily performed in the order represented. Additional, alternative, permuted and/or eliminated steps may be added, substituted, permuted and/or modified as appropriate and consistent with the spirit and scope of the disclosed embodiments.

Claims

1. An integrated circuit, comprising:

a first power transistor integrated with a first driving circuit;

a second power transistor integrated with a second driving circuit; and

an isolator can provide a first control signal to the first power transistor and a second control signal to the second power transistor according to an input signal.

2. The integrated circuit of claim 1, further comprising a first power circuit and a second power circuit, wherein the first power circuit comprises the first driver circuit and the first power transistor, and the second power circuit comprises the second driver circuit and the second power transistor.

3. The integrated circuit of claim 2, further comprising:

a bootstrap diode comprising a bootstrap anode and a bootstrap cathode, wherein the bootstrap anode is coupled to a first supply voltage, and the bootstrap cathode is coupled to a second supply voltage; and

the bootstrap capacitor is coupled to the second supply voltage and a switching voltage of a switching node.

4. The integrated circuit of claim 3, wherein the first driving circuit is powered by the second supply voltage and the switching voltage and generates a first driving voltage at a first driving node according to the first control signal, wherein the first power transistor powers a high voltage to the switching node according to the driving voltage.

5. The integrated circuit of claim 4, wherein the second driving circuit is powered by the first supply voltage and a first ground and generates a second driving voltage at a second driving node according to the second control signal, wherein the second power transistor pulls the switching voltage down to the first ground according to the second driving voltage.

6. The integrated circuit of claim 5 wherein the first power transistor and the second power transistor are both gan transistors.

7. The integrated circuit of claim 5, wherein the high voltage exceeds the first supply voltage and the second supply voltage.

8. The integrated circuit of claim 5, wherein said isolator comprises:

a first sub-isolator comprising:

a first transmitter powered by a third supply voltage and a second ground and capable of transmitting a first RF signal according to the input signal;

a first receiver powered by a second supply voltage and the switching voltage and generating the first control signal according to the first RF signal; and

a first isolation barrier for electrically isolating the first transmitter from the first receiver; and

a second sub-isolator comprising:

a second transmitter, powered by a third supply voltage and a second ground terminal, for transmitting a second radio frequency signal according to the input signal;

a second receiver powered by the first supply voltage and the first ground and capable of generating the second control signal according to the second RF signal; and

a second isolation barrier for electrically isolating the second transmitter from the second receiver.

9. The integrated circuit of claim 5, wherein said isolator comprises:

a transmitter, powered by a third supply voltage and a second ground terminal, for transmitting a first RF signal and a second RF signal according to the input signal;

a first receiver powered by the second supply voltage and the switching voltage and generating the first control signal according to the first RF signal;

a first isolation barrier for electrically isolating the transmitter from the first receiver;

a second receiver powered by the first supply voltage and the first ground and capable of generating the second control signal according to the first RF signal; and

a second isolation barrier for electrically isolating the transmitter from the second receiver.

10. The integrated circuit of claim 8, further comprising:

and a decoupling capacitor coupled between the high voltage and the first ground, wherein the first sub-isolator, the second sub-isolator, the first power circuit, the second power circuit, and the decoupling capacitor are packaged together.

11. The integrated circuit of claim 5, wherein each of the first power circuit and the second power circuit comprises:

the pre-driver circuit generates a first internal signal according to a control signal, wherein the pre-driver circuit is used for improving the driving capability of the control signal, and a driver circuit generates a driving voltage according to the first internal signal.

12. The integrated circuit of claim 11, wherein each of the first power circuit and the second power circuit further comprises:

an upper bridge transistor for providing a supply voltage to a driving node according to an upper bridge voltage of an upper bridge node;

a lower bridge transistor coupling the driving node to a ground terminal according to the first internal signal; and

a charge pump coupled to the upper bridge node and the driving node, wherein the charge pump is configured to generate the upper bridge voltage exceeding the supply voltage according to the first internal signal.

13. The integrated circuit of claim 12, wherein each of the first power circuit and the second power circuit further comprises:

a hysteresis circuit, coupled between the control signal and the pre-driver circuit, for receiving the control signal and generating a second internal signal, such that the pre-driver circuit generates the first internal signal according to the second internal signal, wherein the hysteresis circuit is configured to provide a hysteresis function to the control signal.

14. The integrated circuit of claim 12, wherein each of the first power circuit and the second power circuit further comprises:

an upper bridge normally-on transistor including a source terminal coupled to the driving node, a gate terminal coupled to the driving node, and a drain terminal powered by the supply voltage, wherein the upper bridge normally-on transistor is configured to enhance a driving capability of the upper bridge transistor.

15. A package structure, comprising:

a substrate;

a decoupling capacitor located on the substrate;

an integrated circuit fixed in a first dielectric layer together with the decoupling capacitor; and

a conductive layer for electrically coupling the decoupling capacitor to the integrated circuit, wherein the conductive layer is disposed on the first dielectric layer and penetrates a second dielectric layer.

16. The package structure of claim 15, wherein the decoupling capacitor comprises:

a first conductive unit formed in the first dielectric layer;

a first dielectric element formed on the first conductive element; and

a second conductive element formed on the first dielectric element.

17. The package structure of claim 16, further comprising:

and a bootstrap capacitor disposed on the substrate, wherein the integrated circuit and the bootstrap capacitor are fixed in the first dielectric layer or the second dielectric layer.

18. The package structure of claim 17, wherein the bootstrap capacitor comprises:

a third conductive unit formed in the first dielectric layer;

a second dielectric unit formed on the first conductive unit; and

a fourth conductive element formed on the second dielectric element.

19. The package structure of claim 18, wherein the material of the first dielectric element and the second dielectric element is different from the material of the first dielectric layer and the material of the second dielectric layer.

20. The package structure of claim 17, wherein the integrated circuit comprises:

an isolator for providing a first control signal and a second control signal according to an input signal;

a first power circuit comprising:

a first driving circuit powered by a second supply voltage and a switching voltage

Generating a first driving voltage at a first driving node according to the first control signal, wherein a bootstrap diode and the bootstrap capacitor are used for boosting a first supply voltage to the second supply voltage, wherein the bootstrap diode includes a bootstrap anode coupled to the first supply voltage and a bootstrap cathode coupled to the second supply voltage, and the bootstrap capacitor is coupled between the second supply voltage and the switching voltage of a switching node; and

a first power transistor for supplying a high voltage to the switching node according to the first driving voltage; and

a second power circuit, comprising:

a second driving circuit, powered by the first supply voltage and a first ground terminal, for generating a second driving voltage at a second driving node according to the second control signal;

and

a second power transistor, pulling down the switch voltage to the first ground terminal according to the second driving voltage.

21. The package structure of claim 20 wherein each of the first and second power transistors is a gan transistor.

22. The package structure of claim 20, wherein said isolator comprises:

a first sub-isolator comprising:

a first emitter powered by a third supply voltage and a second ground terminal

A first radio frequency signal can be sent according to the input signal;

a first receiver powered by a second supply voltage and the switching voltage

Generating the first control signal according to the first RF signal; and

a second sub-isolator comprising:

a second transmitter powered by a third supply voltage and a second ground terminal

A second radio frequency signal can be sent according to the input signal;

23. The package structure of claim 20, wherein said isolator comprises:

24. The package structure of claim 20, wherein the decoupling capacitor is coupled between the high voltage and the first ground.

25. The package structure of claim 20, wherein each of the first power circuit and the second power circuit comprises:

26. The package structure of claim 25, wherein each of the first power circuit and the second power circuit comprises:

a lower bridge transistor for coupling the driving node to a ground terminal according to the first internal signal; and

a charge pump, coupled to the upper bridge node and the driving node, for generating the upper bridge voltage exceeding the supply voltage according to the first internal signal.

27. The package of claim 26 wherein the top bridge transistor and the bottom bridge transistor are both normally-off transistors.

28. A manufacturing method for manufacturing a package structure includes:

providing a decoupling capacitor on a substrate;

providing an integrated circuit on the substrate;

fixing the decoupling capacitor and the integrated circuit through a first dielectric and forming a first dielectric layer;

forming a conductive line layer on the first dielectric layer to electrically couple the decoupling capacitor to the integrated circuit through the conductive line layer; and

the conductive layer and the first dielectric layer are fixed by a second dielectric substance, and a second dielectric layer is formed and placed on the first dielectric layer.

29. The method of claim 28, wherein said step of providing said decoupling capacitor on said substrate further comprises:

forming a first conductive unit in the first dielectric layer;

forming a first dielectric unit on the first conductive unit; and

a second conductive element is formed over the first dielectric element.

30. The method of manufacturing of claim 28, further comprising:

providing a bootstrap capacitor on the substrate; and

the bootstrap capacitor, the decoupling capacitor and the integrated circuit are fixed by the first dielectric substance, and the first dielectric layer is formed.

31. The method of claim 30, wherein said step of providing said bootstrap capacitor disposed on said substrate further comprises:

forming a third conductive unit in the first dielectric layer;

forming a second dielectric unit on the third conductive unit; and

forming a fourth conductive unit on the second dielectric unit.

32. The method of manufacturing of claim 30, wherein said integrated circuit comprises:

an isolator including a first supply node, a second supply node, a third supply node, a fourth supply node, a first reference node, a second reference node, a third reference node, a fourth reference node, a first input node, a second input node, a first output node, and a second output node;

a first power circuit including a fifth supply node coupled to the second supply node, a sixth supply node, a fifth reference node coupled to the second reference node, and a first PWM node coupled to the first output node; and

a second power circuit includes a seventh supply node coupled to the fourth supply node, an eighth reference node coupled to the fifth reference node, a sixth reference node, and a second PWM node coupled to the second output node.

33. The method of manufacturing of claim 32, further comprising:

forming a first conductive layer on the substrate, wherein the first power circuit and the bootstrap capacitor are disposed on the first conductive layer, wherein the first conductive layer is coupled to a first terminal of the bootstrap capacitor and the fifth reference node, a second terminal of the bootstrap capacitor is coupled to the fifth supply node through the conductive line layer, and the sixth supply node is coupled to a third terminal of the decoupling capacitor through the conductive line layer.

34. The method of manufacturing of claim 33, further comprising:

forming a second conductive layer on the substrate, wherein the second power circuit and the decoupling capacitor are disposed on the second conductive layer, and wherein the second conductive layer is coupled to a fourth terminal of the decoupling capacitor and a sixth reference node.

35. The method of manufacturing of claim 34, further comprising:

forming a third conductive layer on the substrate, wherein the isolator is located on the third conductive layer.

36. The method of claim 35, wherein the first supply node and the third supply node are powered by a third supply voltage, the second supply node and the fifth supply node are powered by a second supply voltage, the first input node receives an input signal, the second input node receives an inverted input signal, the first output node generates a first control signal, the second output node generates a second control signal, the fourth supply node and the seventh supply node are powered by a first supply voltage, the sixth supply node is powered by a high voltage, the first reference node and the third reference node are coupled to a second ground, the fourth reference node and the sixth reference node are coupled to a first ground, wherein the input signal and the inverted input signal are inverted.

37. The method of manufacturing of claim 36, wherein said first power circuit comprises:

a first driving circuit powered by the second supply voltage and a switching voltage and generating a first driving voltage at a first driving node according to the first control signal; and

a first power transistor couples the sixth supply node to the fifth reference node according to the first driving voltage.

38. The method of manufacturing of claim 37, wherein said second power circuit comprises:

a second driving circuit, powered by the first supply voltage and a first ground terminal, for generating a second driving voltage at a second driving node according to the second control signal; and

a second power transistor, coupling an eighth supply node to the first ground terminal according to the second driving voltage.

39. The method of claim 38, wherein either of the first power transistor and the second power transistor is a gan transistor.

40. The method of manufacturing of claim 38, wherein said integrated circuit further comprises:

a bootstrap diode includes a bootstrap anode terminal and a bootstrap cathode terminal, wherein the bootstrap anode terminal is coupled to a first supply voltage, and the bootstrap cathode terminal is coupled to a second supply voltage.

41. The method of claim 38, wherein the high voltage exceeds the first supply voltage and the second supply voltage.

42. The method of manufacturing of claim 38, wherein said isolator comprises:

a first sub-isolator comprising:

a first emitter powered by a third supply voltage and a second ground terminal

Sending a first radio frequency signal according to the input signal;

a first receiver powered by a second supply voltage and the switching voltage

Generating the first control signal according to the first radio frequency signal; and

a second sub-isolator comprising:

Sending a second radio frequency signal according to the input signal;

a second receiver powered by the first supply voltage and the first ground, the second receiver generating the second control signal according to the second RF signal; and

43. The method of manufacturing of claim 38, wherein each of the first power circuit and the second circuit comprises:

44. The method of manufacturing of claim 43, wherein each of the first power circuit and the second circuit comprises:

45. The method of manufacturing of claim 44, wherein each of the first power circuit and the second circuit comprises:

a hysteresis circuit coupled between the control signal and the pre-driver circuit, wherein the hysteresis circuit receives the control signal to generate a second internal signal, such that the pre-driver circuit generates the first internal signal according to the second internal signal, and the hysteresis circuit is configured to provide a hysteresis function to the control signal.