CN111509353A - Electronic device and antenna device - Google Patents
Electronic device and antenna device Download PDFInfo
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- CN111509353A CN111509353A CN201910848956.XA CN201910848956A CN111509353A CN 111509353 A CN111509353 A CN 111509353A CN 201910848956 A CN201910848956 A CN 201910848956A CN 111509353 A CN111509353 A CN 111509353A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/02—Arrangements for de-icing; Arrangements for drying-out ; Arrangements for cooling; Arrangements for preventing corrosion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/48—Earthing means; Earth screens; Counterpoises
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
Abstract
The present invention provides an antenna device, including: a first substrate, a multilayer electrode, a second substrate and a liquid crystal layer; the multilayer electrode is disposed on the first substrate, and the multilayer electrode includes: the second conductive layer is arranged on the first conductive layer, and the third conductive layer is arranged on the second conductive layer. The liquid crystal layer is arranged between the first substrate and the second substrate; and the third conductive layer includes a first portion that extends beyond the second conductive layer. The invention also provides an electronic device.
Description
Technical Field
The present invention relates to an electronic device and an antenna device, and more particularly, to an electronic device including a multilayer electrode and an antenna device.
Background
The existing electronic products, such as smart phones, tablet computers, notebook computers, displays, televisions or other portable and mobile terminals, have become indispensable necessities of modern society. With the explosion of such portable electronic products, consumers have a high expectation on the quality, functionality, or price of these products. Such electronic products are often used as electronic modulation devices, for example, as antenna devices that modulate electromagnetic waves.
While existing electronic devices may generally satisfy their intended purpose, they have not been satisfactory in every aspect. For example, the difference in Coefficient of Thermal Expansion (CTE) between the metal electrode of the antenna device and the passivation layer makes the passivation layer susceptible to microcracking (microcracking), which may lead to the risk of corrosion of the metal electrode.
Therefore, developing a structure design capable of effectively improving the stability or operation reliability of the electronic device is still one of the issues of the present industry.
Disclosure of Invention
According to some embodiments of the present invention, there is provided an antenna apparatus, including: the liquid crystal display device comprises a first substrate, a multilayer electrode, a second substrate and a liquid crystal layer. The multilayer electrode is disposed on the first substrate, and the multilayer electrode includes: the second conductive layer is arranged on the first conductive layer, and the third conductive layer is arranged on the second conductive layer. The liquid crystal layer is arranged between the first substrate and the second substrate. And the third conductive layer includes a first portion that extends beyond the second conductive layer.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is a schematic cross-sectional view of an electronic device according to some embodiments of the invention;
FIGS. 2A-2C are enlarged schematic views of region B of FIG. 1 according to some embodiments of the invention;
FIGS. 3A-3F are schematic cross-sectional views of an electronic device at an intermediate stage of processing according to some embodiments of the present invention;
fig. 4A-4F are schematic cross-sectional views of an electronic device at an intermediate stage of processing according to some embodiments of the present invention.
Description of the symbols
100 an antenna device;
102 a first substrate;
104a multilayer electrode;
104a first conductive layer;
104ab bottom surface;
104ap second portion;
104 ap' bottom surface;
104as side surface;
104at the top surface;
104b a second conductive layer;
104bb bottom surface;
104be edge;
104bs side surface;
104bt top surface;
104c a third conductive layer;
104cb bottom surface;
104cp first portion;
104 cp' bottom surface;
104cs1, 104cs2 side surfaces;
104ct top surface;
106 a first passivation layer;
106b bottom surface;
106t top surface;
204 electrodes;
206 a second passivation layer;
300 a working medium;
310 a spacing element;
a region B;
e L extended line;
l1 a first length;
l2 a second length;
PR photoresist;
s1 first surface;
s2 second surface;
a first thickness T1;
t2 second thickness;
t3 third thickness;
t4 fourth thickness.
Detailed Description
The antenna device and the method for manufacturing the same according to the embodiments of the present invention will be described in detail below. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of embodiments of the invention. The specific elements and arrangements described below are merely illustrative of some embodiments of the invention for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting. Moreover, similar and/or corresponding elements may be labeled with similar and/or corresponding reference numerals in different embodiments in order to clearly describe the invention. However, the use of such like and/or corresponding reference numerals is merely for simplicity and clarity in describing some embodiments of the invention and does not represent any correlation between the various embodiments and/or structures discussed.
It is to be understood that the drawings of the present invention are not to scale and that in fact any enlargement or reduction of the dimensions of the elements is possible in order to clearly show the nature of the invention.
Furthermore, when a first material layer is located on or above a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more layers of other materials may be present, in which case there may not be direct contact between the first and second layers of material.
Furthermore, the elements or devices of the drawings may exist in a variety of forms well known to those of ordinary skill in the art to which the invention pertains. Further, it should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, or sections, these elements, components, or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
The terms "range from a first value to a second value," and "range between a first value and a second value," as used herein, mean that the range includes the first value, the second value, and other values therebetween.
In some embodiments of the present invention, terms concerning bonding and connecting, such as "connecting," "interconnecting," "contacting," and the like, may refer to two structures being in direct contact or, alternatively, to two structures not being in direct contact, wherein another structure is disposed between the two structures, unless otherwise specified. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.
Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view illustrating an electronic device 100 according to some embodiments of the invention. It should be understood that additional features may be added to the electronic device 100 described below, according to some embodiments. In other embodiments, some of the features of electronic device 100 described below may be replaced or omitted.
As shown in fig. 1, the electronic device 100 may include a first substrate 102 and a second substrate 202, and the second substrate 202 may be disposed opposite to the first substrate 102. In detail, the first substrate 102 may have a first surface S1And a second surface S2And the first surface S1And the second surface S2May be located on opposite sides. Similarly, the second substrate 202 may have first surfaces S on opposite sides1And a second surface S2. In some embodiments, the first surface S of the first substrate 1021Adjacent to the first surface S of the second substrate 2021And are disposed opposite to each other.
In some embodiments, the first substrate 102 and the second substrate 202 may be flexible substrates, rigid substrates, or a combination thereof, in an embodiment, the first substrate 102 and the second substrate 202 may include a glass substrate, a sapphire substrate, a ceramic substrate, a plastic substrate, a liquid-crystal polymer (L CP) substrate, other suitable substrate materials, or a combination thereof, but is not limited thereto, in an embodiment, the plastic substrate may include Polyimide (PI), polyethylene terephthalate (PET), Polycarbonate (PC), Polyethersulfone (PES), polybutylene terephthalate (PBT), polyethylene naphthalate (PEN) or Polyarylate (PAR), other suitable materials, or a combination thereof, in some embodiments, the first substrate 102 may be made of the same material as or different from the second substrate 202.
Furthermore, as shown in fig. 1, the electronic device 100 may include a multi-layer electrode 104, and the multi-layer electrode 104 may be disposed on the first substrate 102. In detail, the multi-layer electrode 104 may be disposed on the first surface S of the first substrate 1021The above. According to some embodiments, the multilayer electrode 104 may include a first conductive layer 104a, a second conductive layer 104b, and a third conductive layer 104c, the second conductive layer 104b may be disposed on the first conductive layer 104a, and the third conductive layer 104c may be disposed on the second conductive layer 104 b. In some embodiments, the first conductive layer 104a may be in contact with the first substrate 102.
It is noted that the adhesion and the thermal expansion coefficient difference between the second conductive layer 104b and the first passivation layer 16 are not good. The structure of the first passivation layer 16 formed on the second conductive layer 104b is easily affected or damaged by temperature change, for example, cracks are easily generated at the corners of the first passivation layer 106. In this way, moisture generated in the subsequent process or chemical solvents used in the subsequent process may easily penetrate into the second conductive layer 104b through the micro cracks, resulting in corrosion or oxidation of the second conductive layer 104 b.
However, according to some embodiments of the present invention, the electronic device 100 includes the multi-layer electrode 104 having the first conductive layer 104a, the second conductive layer 104b and the third conductive layer 104c, and the third conductive layer 104c can be used as a buffer layer to completely cover the second conductive layer 104b to protect the second conductive layer 104b, and the third conductive layer 104a can be used to improve the above-mentioned problems, such as the difference of adhesion or thermal expansion coefficient between the passivation layer and the multi-layer electrode, thereby reducing the risk of microcracks in the passivation layer or corrosion of the multi-layer electrode.
It should be understood that although the drawings illustrate the multi-layer electrode 104 having a three-layer structure, the invention is not limited thereto, and the multi-layer electrode 104 may have other suitable numbers of layers according to different embodiments.
In detail, according to some embodiments of the present invention, the adhesion may be measured by a Cross-Cut method (astm d3359, ISO/DIN 2409 standard specification). Among the results of the hundred grid test, those meeting the specifications of ASTM grade 5B indicate good adhesion. Further, in some embodiments, the coefficient of thermal expansion of the material of the third conductive layer 104c is between the coefficient of thermal expansion of the second conductive layer 104b and the coefficient of thermal expansion of the first passivation layer 106 (10)-6/K @20 deg.C), for example, from 2 to 17, or from 4 to 15, e.g., 5, 6, 7, 8, 9, 10, 11, 12, 13, or 14, etc.
Further, as shown in fig. 1, according to some embodiments, the second conductive layer 104b is completely covered by the third conductive layer 104 c. The term "completely" refers to that both the top surface 104bt and the side surface 104bs of the second conductive layer 104b are completely covered. In detail, in some embodiments, the bottom surface 104bb of the second conductive layer 104b is in contact with the first conductive layer 104a, and the top surface 104bt and the side surface 104bs of the second conductive layer 104b are in contact with the third conductive layer 104 c. In other words, in some embodiments, the third conductive layer 104c may completely cover the top surface 104bt and the side surface 104bs of the second conductive layer 104 b. In some embodiments, the third conductive layer 104c may also cover a top surface 104at of a portion of the first conductive layer 104 a. In some embodiments, the third conductive layer 104c may also cover a portion of the side surface 104as of the first conductive layer 104 a.
In some embodiments, the material of the first conductive layer 104a may include titanium (Ti), molybdenum (Mo), a titanium alloy, a molybdenum alloy, Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the first conductive layer 104a may comprise a material selected from the group consisting of titanium, molybdenum, indium zinc oxide, and indium tin oxide. For example, in some embodiments, the material of the first conductive layer 104a may include molybdenum titanium alloy (MoTi), molybdenum tantalum alloy (MoTa), molybdenum niobium alloy (MoNb), or a combination thereof, but is not limited thereto.
In some embodiments, the material of the second conductive layer 104b may include copper (Cu), aluminum (Al), a copper alloy, an aluminum alloy, other suitable materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the second conductive layer 104b may comprise a material selected from the group consisting of copper and aluminum. In some embodiments, the material of the second conductive layer 104b may be the same as the material of the gate, the source, or the drain of the thin film transistor used to control the multilayer electrode 104 or the electrode 204.
In some embodiments, the material of the third conductive layer 104c may include titanium (Ti), molybdenum (Mo), a titanium alloy, a molybdenum alloy, Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the third conductive layer 104c may comprise a material selected from the group consisting of titanium, molybdenum, indium zinc oxide, and indium tin oxide. For example, in some embodiments, the material of the first conductive layer 104a may include molybdenum titanium alloy (MoTi), molybdenum tantalum alloy (MoTa), molybdenum niobium alloy (MoNb), or a combination thereof, but is not limited thereto.
In addition, the first conductive layer 104a may have a first thickness T1. In some embodiments, the first thickness T of the first conductive layer 104a1Can range between 5nm and 200nm (i.e., 5nm ≦ first thickness T1≦ 200nm), between 5nm and 100nm, or between 10nm and 40nm, for example 15nm, 20nm, 25nm, 30nm, or 35 nm. According to some embodiments, the first thickness T1Refers to the distance between the bottom surface 104ab and the top surface 104at of the first conductive layer 104a in the normal direction (e.g., Z direction shown in the figure) of the first substrate 102. Specifically, the first thickness T1The average thickness (e.g., 3 to 5 thickness values are measured and then averaged) or the maximum thickness of the first conductive layer 104a along the normal direction (e.g., Z direction) of the first substrate 102 can be measured, for example, by a Scanning Electron Microscope (SEM). In some embodiments, when the first substrate 102 has flexibility, the first substrate 102 is first flattened, and then the average thickness or the maximum thickness of the first conductive layer 104a is measured along the normal direction of the first substrate 102 in the cross section.
The second conductive layer 104b may have a second thickness T2. In some embodiments, the second thickness T of the second conductive layer 104b2Can be greater than 1 micrometer (μm), e.g., can be between 0.5 μm and 10 μm (i.e., 0.5 μm ≦ second thickness T210 μm), between 1 μm and 9 μm, or between 3 μm and 8 μm, for example 4 μm, 5 μm, 6 μm, or 7 μm. According to some embodiments, the second thickness T2Refers to the distance between the bottom surface 104bb and the top surface 104bt of the second conductive layer 104b in the normal direction (e.g., Z direction shown in the figure) of the first substrate 102. Second conductive layer104b of a second thickness T2And the first thickness T of the first conductive layer 104a1Similarly, it will not be repeated here.
Furthermore, the third conductive layer 104c may have a third thickness T3. In some embodiments, the third thickness T of the third conductive layer 104c3Can range between 10 nanometers (nm) and 200 nanometers (i.e., 10nm ≦ third thickness T3≦ 200nm), between 10nm and 100nm, or between 20nm and 40nm, for example 25nm, 30nm, or 35 nm. According to some embodiments, the third thickness T3Refers to a distance between the bottom surface 104cb of the third conductive layer 104c and the top surface 104ct in a normal direction (e.g., Z direction shown in the figure) of the first substrate 102. Third thickness T of third conductive layer 104c3And the first thickness T of the first conductive layer 104a1Similarly, it will not be repeated here.
It should be understood that if the third thickness T of the third conductive layer 104c is provided3Too small (e.g., less than 10nm), the third conductive layer 104c may not completely cover the second conductive layer 104b, or may be easily uneven in thickness due to process factors, thereby reducing the effect of protecting the second conductive layer 104 b; on the contrary, if the third thickness T3Too large (e.g., greater than 100nm), the manufacturing cost of the third conductive layer 104c may be increased.
Further, details of the positional relationship among the first conductive layer 104a, the second conductive layer 104b, and the third conductive layer 104c will be described later.
Further, in some embodiments, the multi-layer electrode 104 may be formed by one or more deposition processes, photolithography processes, and etching processes, in some embodiments, the deposition processes may include, but are not limited to, a chemical vapor deposition process (L PCVD), a low temperature chemical vapor deposition process (L TCVD), a rapid thermal chemical vapor deposition process (RTCVD), a plasma enhanced chemical vapor deposition Process (PECVD), or an atomic layer deposition process (A L D), for example, but not limited to, a low pressure chemical vapor deposition process (L PCVD), a low temperature chemical vapor deposition process (L TCVD), a rapid thermal chemical vapor deposition process (RTCVD), a plasma enhanced chemical vapor deposition Process (PECVD), or an atomic layer deposition process (A L D).
The steps of the method for manufacturing the first conductive layer 104a, the second conductive layer 104b, and the third conductive layer 104c will be described in detail later.
Furthermore, as shown in fig. 1, in some embodiments, the electronic device 100 may further include a first passivation layer 106, and the first passivation layer 106 may be disposed on the multi-layer electrode 104. In detail, in some embodiments, the first passivation layer 106 may be conformally (conformally) formed on the third conductive layer 104c of the multi-layer electrode 104, for example, it means that the first passivation layer 106 may be disposed along with the thickness variation of the underlying third conductive layer 104c, for example, the first passivation layer 106 may be disposed along the top surface 104ct and the side surface 104cs of the third conductive layer 104 c. In some embodiments, the first passivation layer 106 may be in contact with the top surface 104ct and the side surface 104cs of the third conductive layer 104c1And side surface 104cs2And the first passivation layer 106 may also be in contact with the side surface 104as of the first conductive layer 104 a. In other words, in some embodiments, the first passivation layer 106 may completely cover the top surface 104ct and the side surface 104cs of the third conductive layer 104c1And side surface 104cs2. Furthermore, in some embodiments, the first passivation layer 106 may further extend to the first surface S of the first substrate 1021The above.
Furthermore, it should be understood that although the second conductive layer 104b is illustrated in the figures as having a sharp top corner, according to other embodiments, the second conductive layer 104b may have an arc-shaped top corner. In the embodiment where the second conductive layer 104b has an arc-shaped top corner, the problem of peeling of the second conductive layer 104b from the subsequently formed layers can be improved.
In some embodiments, the first passivation layer 106 may have a single-layer structure or a multi-layer structure. In some embodiments, the material of the first passivation layer 106 may include an inorganic material, an organic material, or a combination of the foregoing, but is not limited thereto. In some embodiments, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the organic material may include polyethylene terephthalate (PET), Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), Polyimide (PI), photosensitive polyimide (PSPI), other suitable materials, or a combination thereof, but is not limited thereto.
In addition, the first passivation layer 106 may have a fourth thickness T4. In some embodiments, the fourth thickness T of the first passivation layer 1064Can range between 10nm and 500nm (i.e., 10nm ≦ fourth thickness T4≦ 500nm), between 50nm and 200nm, or between 80nm and 150nm, for example 90nm, 100nm, 110nm, 120nm, 130nm, or 140 nm. According to some embodiments, the fourth thickness T4Refers to a distance between the bottom surface 106b and the top surface 106t of the first passivation layer 106 on the multi-layer electrode 104 in a normal direction (e.g., Z direction shown in the figure) of the first substrate 102. Fourth thickness T of the first passivation layer 1064And the first thickness T of the first conductive layer 104a1Similarly, it will not be repeated here.
It should be understood that if the fourth thickness T of the first passivation layer 106 is provided4Too small (e.g., less than 10nm), the first passivation layer 106 may not completely cover the multi-layer electrode 104, thereby reducing the effect of protecting the multi-layer electrode 104, or may be more prone to thickness non-uniformity due to process factors; on the contrary, if the fourth thickness T is smaller4Too large (e.g., greater than 500nm), the manufacturing cost of the first passivation layer 106 may be increased.
In some embodiments, the first passivation layer 106 may be formed by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof. Furthermore, the first passivation layer 106 may be patterned by one or more photolithography processes and etching processes. In some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. In some embodiments, the etching process includes a dry etching process, a wet etching process, or other suitable etching processes.
Referring to fig. 1, the electronic device 100 may further include an electrode 204, and the electrode 204 may be disposed on the second substrate 202. In detail, the electrode 204 may be located between the first substrate 102 and the second substrate 102, and may be disposed on the first surface S of the second substrate 102b1The above.
In some embodiments, the multi-layer electrode 104 may have an opening (not shown), and the opening may overlap with the electrode 204 in a normal direction (e.g., the Z direction shown in the figure) of the first substrate 102. In some embodiments, the multilayer electrode 104 may be patterned with openings. In some embodiments, the electrode 204 may also be patterned to have multiple regions (only a portion of the electrode 204 is shown in the figures). In some embodiments, multiple regions of the electrode 204 may be connected to different circuits.
In some embodiments, the electrode 204 and/or the multi-layer electrode 104 may be electrically connected to a functional circuit (not shown). The functional circuit may include active elements (e.g., thin film transistors) or passive elements (e.g., controlled by an Integrated Circuit (IC) or microchip). The thin film transistor may be, for example, a switching transistor, a driving transistor, a reset transistor, or other thin film transistors. In some embodiments, the aforementioned functional circuit may be located on the first surface S of the second substrate 202 (or the first substrate 102) as the electrode 204 (or the multi-layer electrode 104)1The above. In other embodiments, the functional circuit may be located on the second surface S of the second substrate 202 (or the first substrate 102)2The functional circuit may be electrically connected to the electrode 204 (or the multi-layer electrode 104), for example, by penetrating the second substrate 202 (or the first substrate 102)Vias (not shown), flexible circuit boards, or other suitable electrical connections, but not limited thereto.
In some embodiments, the electrode 204 may comprise a conductive material, such as a metallic conductive material, a transparent conductive material, or a combination of the foregoing. In some embodiments, the aforementioned metallic conductive material may include copper (Cu), aluminum (Al), molybdenum (Mo), silver (Ag), tin (Sn), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), a copper alloy, an aluminum alloy, a molybdenum alloy, a silver alloy, a tin alloy, a tungsten alloy, a gold alloy, a chromium alloy, a nickel alloy, a platinum alloy, other suitable metallic materials, or a combination of the foregoing, but is not limited thereto. In some embodiments, the transparent conductive material may include Transparent Conductive Oxide (TCO). For example, the transparent conductive oxide may include Indium Tin Oxide (ITO), tin oxide (SnO), zinc oxide (ZnO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Oxide (IGZO), Indium Tin Zinc Oxide (ITZO), Antimony Tin Oxide (ATO), Antimony Zinc Oxide (AZO), other suitable transparent conductive materials, or a combination thereof, but is not limited thereto.
Further, in some embodiments, the electrode 204 may have a single layer structure or a multi-layer structure. According to some embodiments, the structure of the electrode 204 may be the same as or similar to the structure of the multi-layer electrode 104, but the invention is not limited thereto. Specifically, in some embodiments, the electrode 204 may also include a first surface S sequentially formed on the second substrate 2021A first conductive layer 104a, a second conductive layer 104b, and a third conductive layer 104 c.
Further, in some embodiments, the electrode 204 may be formed using one or more deposition processes, photolithography processes, and etching processes. In some embodiments, the deposition process may include, but is not limited to, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof. In addition, in some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist developing, cleaning, and drying. In some embodiments, the etching process includes a dry etching process, a wet etching process, or other suitable etching processes.
Moreover, it should be understood that although only one multilayer electrode 104 and one electrode 204 are illustrated in the figures, according to some embodiments, the electronic device 100 may be adapted to include a plurality of multilayer electrodes 104 and/or electrodes 204 as desired.
With continued reference to fig. 1, according to some embodiments, the electronic device 100 may further include a second passivation layer 206, and the second passivation layer 206 may be disposed on the electrode 204. In detail, in some embodiments, the second passivation layer 206 may be conformally formed on the electrode 204. In some embodiments, the second passivation layer 206 may further extend to the first surface S of the second substrate 2021The above.
In some embodiments, the second passivation layer 206 may have a single-layer structure or a multi-layer structure. In some embodiments, the material of the second passivation layer 206 may include an inorganic material, an organic material, or a combination of the foregoing, but is not limited thereto. In some embodiments, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or a combination thereof, but is not limited thereto. In some embodiments, the organic material may include polyethylene terephthalate (PET), Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), Polyimide (PI), photosensitive polyimide (PSPI), other suitable materials, or a combination thereof, but is not limited thereto.
In some embodiments, the second passivation layer 206 may be formed by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof. Furthermore, the second passivation layer 206 may be patterned by one or more photolithography processes and etching processes. In some embodiments, the photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. In some embodiments, the etching process includes a dry etching process, a wet etching process, or other suitable etching processes.
In addition, as shown in fig. 1, the electronic device 100 may further include a working medium 300, and the working medium 300 may be disposed between the first substrate 102 and the second substrate 202, and a portion may be located between the multilayer electrode 104 and the electrode 204. According to some embodiments, materials having different properties (e.g., permittivity) that can be adjusted via application of an electric field or otherwise may be used as the working medium 300. In some embodiments, the transmission direction of the electromagnetic signal passing through the opening (not shown) can be controlled by applying different electric fields to the working medium 300 to adjust the capacitance.
In some embodiments, the working medium 300 may include a liquid crystal layer, but is not limited thereto. In some embodiments, the material of the liquid crystal layer may include nematic (nematic) liquid crystal, smectic (cholesteric) liquid crystal, cholesteric (cholesteric) liquid crystal, blue-phase (blue-phase) liquid crystal, other suitable liquid crystal material, or a combination thereof, but is not limited thereto.
In detail, in some embodiments, the functional circuit may apply a voltage to the electrode 204, and change the property of the working medium between the multi-layer electrode 104 and the electrode 204 by the electric field generated between the multi-layer electrode 104 and the electrode 204. Furthermore, the functional circuit may also apply another voltage to the multi-layer electrode 104, but is not limited thereto. In other embodiments, the multi-layer electrode 104 may be electrically floating, grounded, or connected to other functional circuits (not shown), but is not limited thereto.
In addition, according to some embodiments, the electronic device 100 may further include a spacing element 310 disposed between the first substrate 102 and the second substrate 202 for supporting the first substrate 102 and the second substrate 202 to enhance the structural strength of the electronic device 100. In some embodiments, the spacer elements 310 may have a ring-like structure. In some embodiments, the spacing elements 310 may have a columnar structure and be arranged in parallel.
Furthermore, the spacer elements 310 may comprise an insulating material. In some embodiments, the insulating material may include polyethylene terephthalate (PET), Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), glass, or a combination thereof, but is not limited thereto.
In addition, according to some embodiments, the electronic device 100 may further include alignment layers (not shown) disposed between the first passivation layer 106 and the working medium 300 and between the second passivation layer 206 and the working medium 300 to control the alignment direction of the liquid crystal molecules in the working medium 300. In some embodiments, the material of the alignment layer may comprise an organic material, an inorganic material, or a combination of the foregoing. For example, the organic material may include Polyimide (PI), a photoreactive polymer material, or a combination thereof, but is not limited thereto. The inorganic material may comprise, for example, silicon dioxide (SiO)2) But is not limited thereto.
According to some embodiments of the present invention, the electronic device 100 may be a display device, an antenna device, a sensing device, a splicing device, or other devices for modulating electromagnetic waves, but is not limited thereto.
In some embodiments of the invention, the electronic device 100 may also include an organic light emitting diode (O L ED) display device or an inorganic light emitting diode (inorganic light emitting diode) display device (not shown), wherein the organic light emitting diode may include an upper electrode, a lower electrode and an organic light emitting layer formed therebetween, and the inorganic light emitting diode may include a quantum dot light emitting diode (Q-L ED), a micro light emitting diode (micro L ED) or a sub-millimeter light emitting diode (mini L ED), wherein the light emitting material of the micro light emitting diode or the sub-millimeter light emitting diode may include a fluorescent (fluorescent), phosphorescent (phosphor) or other suitable material or any combination thereof, but is not limited thereto.
In other embodiments of the present invention, the electronic device 100 may be an antenna device, such as a liquid crystal antenna device, but not limited thereto. The electronic device 100 may also be a tiled device, such as a display tiled device or an antenna tiled device, but not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto.
Referring to fig. 2A to 2C, fig. 2A to 2C are enlarged schematic views of a region B shown in fig. 1 according to some embodiments of the present invention. Furthermore, fig. 2A to 2C illustrate the electronic device 100 as an antenna device, however, it should be understood that the structure may be applied to other electronic devices according to some embodiments. Specifically, fig. 2A to 2C illustrate the arrangement relationship between the first conductive layer 104a, the second conductive layer 104b, the third conductive layer 104C and the first insulating layer 106 according to some embodiments of the present invention. It should be understood that the same or similar components or elements are denoted by the same or similar reference numerals, and the same or similar materials, manufacturing methods and functions are the same or similar to those described above, so that the detailed description thereof will not be repeated.
As shown in fig. 2A-2C, according to some embodiments of the present invention, third conductive layer 104C includes first portion 104cp, and first portion 104cp extends beyond second conductive layer 104 b. As shown in fig. 2A, in some embodiments, the first portion 104cp of the third conductive layer 104c can cover the first surface S of the first substrate 1021And a side surface 104as of the first conductive layer 104 a. In some embodiments, the side surface 104bs of the second conductive layer 104b is not flush with the side surface 104as of the first conductive layer 104 a. In some embodiments, side surface 104as of first conductive layer 104a protrudes more than side surface 104bs of second conductive layer 104b, e.g., closer to first portion 104 cp. The bottom surface 104bb of the second conductive layer 104b has an end point 104be thereon. According to some embodiments, the extension can be performed byThe line E L defines a first portion 104cp of the third conductive layer 104c, the extended line E L being a reference line passing through the end point 104be and parallel to a normal direction (e.g., Z direction shown in the figure) of the first substrate 102. in detail, the first portion 104cp of the third conductive layer 104c can be defined as starting from the extended line E L, and the third conductive layer 104c is along a direction parallel to the first surface S of the first substrate 1021In other words, the first portion 104cp of the third conductive layer 104c may be the side surface 104cs of the third conductive layer 104c1And side surface 104cs2And the portion between the extension line E L.
Furthermore, the first portion 104cp has a first length L1First length L, according to some embodiments1Refers to the length of the bottom surface 104 cp' of the first portion 104cp of the third conductive layer 104c (along a direction parallel to the first surface S of the first substrate 102)1E.g., the X-direction shown in the figure.) in some embodiments, the first length L of the first portion 104cp1May be greater than 0.1 μm (i.e., first length L)1≧ 0.1 μm), for example, between 0.1 μm and 4 μm (i.e., 0.1 μm ≦ first length L1≦ 4 μm), or between 0.1 μm and 3 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, or 2.5 μm, but not limited thereto.
It will be appreciated that if the first length L of the first portion 104cp is first1Too small (e.g., less than 0.1 μm), the third conductive layer 104c may be difficult to completely cover the second conductive layer 104b, thereby reducing the effect of protecting the second conductive layer 104b, whereas if the first length L is small1Too large (e.g., greater than 4 μm), the manufacturing cost of the third conductive layer 104c may increase.
As shown in fig. 2B, the difference from fig. 2A is that, in some embodiments, a bottom surface 104 cp' of the third conductive layer 104c overlaps a top surface 104at of the first conductive layer 104a in the Z direction. According to some embodiments of the invention, the first conductive layer 104a may include a second portion 104ap, the second portion 104ap extending beyond the second conductive layer 104b and also being in contact with a first portion 104cp of the third conductive layer 104 c.It should be understood that, for clarity of illustration, the second portion 104 ap. is omitted from the embodiment shown in FIG. 2A, and the bottom surface 104bb of the second conductive layer 104b has an endpoint 104 be.. according to some embodiments, the second portion 104ap of the first conductive layer 104a can be defined by an extended line E L, the extended line E L being a reference line passing through the endpoint 104be and parallel to the normal direction (e.g., the Z direction shown in the figure) of the first substrate 102. in detail, the second portion 104ap of the first conductive layer 104a can be defined as extending from the extended line E L, the first conductive layer 104a being along a direction parallel to the first surface S of the first substrate 1021In other words, the second portion 104ap of the first conductive layer 104a may be a portion between the side surface 104as of the first conductive layer 104a and the extension line E L.
Further, second portion 104ap has a second length L2According to some embodiments, second length L2Refers to the length of the bottom surface 104 ap' of the second portion 104ap of the first conductive layer 104a (along a line parallel to the first surface S of the first substrate 102)1E.g., along the X-direction shown in the figure.) in some embodiments, the second length L of the second portion 104ap2May be greater than 0.1 μm (i.e., second length L)2≧ 0.1 μm), for example, between 0.1 μm and 4 μm (i.e., 0.1 μm ≦ second length L2≦ 4 μm), or between 0.1 μm and 3 μm, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, or 2.5 μm, but not limited thereto.
It should be understood that if second length L of second portion 104ap were to be provided2Too small (e.g., less than 0.1 μm), the first conductive layer 104a may expose a portion of the second conductive layer 104b, thereby reducing the effectiveness of protecting the second conductive layer 104b, whereas the second length L2Too large (e.g., greater than 4 μm), the manufacturing cost of the first conductive layer 104a may increase.
Furthermore, as shown in fig. 2B, in some embodiments, the side surface 104cs of the third conductive layer 104c2May be aligned with the side surface 104as of the first conductive layer 104 a. However, as shown in FIG. 2C, the difference from FIG. 2B isIn some embodiments, the side surface 104cs of the third conductive layer 104c2May not be aligned with the side surface 104as of the first conductive layer 104 a. According to some embodiments, aligned refers to flush surfaces. In detail, in some embodiments, the side surface 104cs of the third conductive layer 104c is compared to the side surface 104as of the first conductive layer 104a2May be retracted.
In detail, in some embodiments, after the working medium 300 is removed, a cross-sectional image of the structure may be obtained by using the scanning electron microscope, and the thickness, the length, or the distance between the elements may be measured.
Referring to fig. 3A to 3F, fig. 3A to 3F are schematic cross-sectional views of some components (e.g., the multi-layer electrode 104) of the electronic device 100 at an intermediate stage of the manufacturing process according to some embodiments of the present invention. It is understood that additional operational steps may be provided before, during, and/or after the fabrication process of the electronic device 100, according to some embodiments. According to some embodiments, some of the described operational steps may be replaced or deleted. According to some embodiments, the order of the operational steps is interchangeable.
Referring to fig. 3A, in some embodiments, a first substrate 102 may be provided, and a first conductive layer 104a and a second conductive layer 104b are sequentially formed on the first substrate 102. Next, a photoresist PR may be formed on the second conductive layer 104b to define a subsequent patterned shape of the second conductive layer 104 b.
In some embodiments, the first conductive layer 104a and the second conductive layer 104b may be formed by the above-mentioned physical vapor deposition process, the above-mentioned chemical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof. In addition, in some embodiments, the photoresist PR may be patterned by a patterning process. In some embodiments, the patterning process may include a photolithography process and an etching process. The photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include, but is not limited to, a dry etching process or a wet etching process.
Next, referring to fig. 3B, in some embodiments, a portion of the second conductive layer 104B may be removed to form a patterned second conductive layer 104B. In detail, a portion of the second conductive layer 104b not shielded by the photoresist PR may be removed by an etching process. In this embodiment, the etching process may be a selective etching process, for example, only a portion of the second conductive layer 104b may be removed, and the first conductive layer 104a may not be removed. In this embodiment, the etching process may be a wet etching process. However, in other embodiments, a portion of the second conductive layer 104b may be removed by a dry etching process.
Next, referring to fig. 3C, in some embodiments, after the patterned second conductive layer 104b is formed, the photoresist PR may be removed. In some embodiments, the photoresist PR may be removed by a wet strip process, a plasma ashing process, or a combination thereof.
Next, referring to fig. 3D, in some embodiments, a third conductive layer 104c may be formed on the first substrate 102. In some embodiments, the third conductive layer 104c may be conformally formed on the first conductive layer 104a and the second conductive layer 104 b.
In some embodiments, the third conductive layer 104c may be formed by the above-mentioned physical vapor deposition process, the above-mentioned chemical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination thereof.
Next, referring to fig. 3E, in some embodiments, a photoresist PR may be formed on the first substrate 102 to define a subsequent patterned shape of the first conductive layer 104a and the third conductive layer 104 c. In some embodiments, the photoresist PR may completely cover the second conductive layer 104b, and cover a portion of the first conductive layer 104a and the third conductive layer 104 c.
In some embodiments, the photoresist PR may be patterned by a patterning process. In some embodiments, the patterning process may include a photolithography process and an etching process. The photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include, but is not limited to, a dry etching process or a wet etching process.
Next, referring to fig. 3F, in some embodiments, a portion of the first conductive layer 104a and the third conductive layer 104c can be removed to form the patterned first conductive layer 104a and the third conductive layer 104 c. In detail, the first conductive layer 104a and the third conductive layer 104c that are not masked by the photoresist PR may be removed by an etching process. In this embodiment, the etching process may be a dry etching process. However, in other embodiments, a portion of the first conductive layer 104a and the third conductive layer 104c may be removed by a wet etching process.
Further, after the patterned first conductive layer 104a and the third conductive layer 104c are formed, the photoresist PR may be removed. In some embodiments, the photoresist PR may be removed by a wet strip process, a plasma ashing process, or a combination thereof.
As shown in fig. 3F, the process flow of the multi-layered electrode 104 is substantially completed. In view of the foregoing, according to some embodiments, the multi-layer electrode 104 is formed by a two-step etching process (e.g., as shown in fig. 3B and 3F). In addition, in some embodiments, the first conductive layer 104a and the third conductive layer 104c are formed by the same etching process (e.g., as shown in fig. 3F).
Referring to fig. 4A to 4F, fig. 4A to 4F are schematic cross-sectional views of some components (e.g., the multi-layer electrode 104) of the electronic device 100 at an intermediate stage of a manufacturing process according to other embodiments of the present invention.
Referring to fig. 4A, in some embodiments, a first substrate 102 may be provided, and a first conductive layer 104A and a second conductive layer 104b are sequentially formed on the first substrate 102. Next, a photoresist PR may be formed on the second conductive layer 104b to define a subsequent patterned shape of the second conductive layer 104 b.
Next, referring to fig. 4B, in some embodiments, a portion of the first conductive layer 104a and the second conductive layer 104B can be removed to form the patterned first conductive layer 104a and the second conductive layer 104 bb. In detail, a portion of the first conductive layer 104a and the second conductive layer 104b not shielded by the photoresist PR may be removed by an etching process. In this embodiment, the etching process may be a wet etching process. However, in other embodiments, a portion of the first conductive layer 104a and the second conductive layer 104b may be removed by a dry etching process.
Next, referring to fig. 4C, in some embodiments, after the patterned first conductive layer 104a and the patterned second conductive layer 104b are formed, the photoresist PR may be removed. In some embodiments, the photoresist PR may be removed by a wet strip process, a plasma ashing process, or a combination thereof.
Next, referring to fig. 4D, in some embodiments, a third conductive layer 104c may be formed on the first substrate 102. In some embodiments, the third conductive layer 104c may be conformally formed on the first conductive layer 104a and the second conductive layer 104 b.
Next, referring to fig. 4E, in some embodiments, a photoresist PR may be formed on the first substrate 102 to define a subsequent patterned shape of the third conductive layer 104 c. In some embodiments, the photoresist PR may completely cover the first conductive layer 104a, the second conductive layer 104b, and a portion of the third conductive layer 104 c.
Next, referring to fig. 4F, in some embodiments, a portion of the third conductive layer 104c may be removed to form a patterned third conductive layer 104 c. In detail, the third conductive layer 104c not shielded by the photoresist PR may be removed by an etching process. In this embodiment, the etching process may be a dry etching process. However, in other embodiments, a portion of the third conductive layer 104c may also be removed by a wet etching process.
Further, after the patterned third conductive layer 104c is formed, the photoresist PR may be removed. In some embodiments, the photoresist PR may be removed by a wet strip process, a plasma ashing process, or a combination thereof.
As shown in fig. 4F, the process flow of the multi-layered electrode 104 is substantially completed. In view of the foregoing, according to some embodiments, the multi-layer electrode 104 is formed by a two-step etching process (e.g., as shown in fig. 4B and 4F). In addition, in some embodiments, the first conductive layer 104a and the second conductive layer 104B are formed by the same etching process (e.g., as shown in fig. 4B).
In summary, according to some embodiments of the present invention, an electronic device is provided that includes a multi-layer electrode having a first conductive layer, a second conductive layer, and a third conductive layer, wherein the third conductive layer can be used as a buffer layer to completely cover the second conductive layer to protect the second conductive layer, or can improve adhesion between a passivation layer and the multi-layer electrode or reduce a difference in thermal expansion coefficient therebetween, thereby reducing a risk of microcracks in the passivation layer or corrosion of the multi-layer electrode.
Although the embodiments of the present invention and their advantages have been described above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the invention. Features of the embodiments of the invention can be combined and matched arbitrarily without departing from the spirit or conflict of the invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but it is to be understood that any process, machine, manufacture, composition of matter, means, method and steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present application. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes combinations of the respective claims and embodiments. The scope of the invention is to be determined by the claims appended hereto.
Claims (16)
1. An antenna device, comprising:
a first substrate;
a multilayer electrode disposed on the first substrate, the multilayer electrode comprising:
a first conductive layer;
the second conducting layer is arranged on the first conducting layer; and
the third conducting layer is arranged on the second conducting layer;
the second substrate is arranged opposite to the first substrate; and
the liquid crystal layer is arranged between the first substrate and the second substrate;
wherein the third conductive layer includes a first portion that extends beyond the second conductive layer.
2. The antenna assembly of claim 1 wherein the first conductive layer includes a second portion that extends beyond the second conductive layer and contacts the first portion.
3. The antenna device of claim 2, wherein a length of the second portion ranges from 0.1 microns to 4 microns.
4. The antenna device of claim 1, wherein a thickness of the third conductive layer ranges from 10nm to 100 nm.
5. The antenna device of claim 4, wherein the thickness of the third conductive layer ranges between 20 nanometers and 40 nanometers.
6. The antenna device of claim 1, wherein a length of the first portion ranges from 0.1 microns to 4 microns.
7. The antenna device of claim 1, wherein a material of the first conductive layer comprises titanium, molybdenum, a titanium alloy, a molybdenum alloy, indium zinc oxide, indium tin oxide, or a combination of the foregoing materials.
8. The antenna device of claim 1, wherein a material of the second conductive layer comprises copper, aluminum, a copper alloy, an aluminum alloy, or a combination of the foregoing materials.
9. The antenna device of claim 1, wherein a material of the third conductive layer comprises titanium, molybdenum, a titanium alloy, a molybdenum alloy, indium zinc oxide, indium tin oxide, or a combination of the foregoing materials.
10. The antenna device of claim 1, wherein the multi-layer electrode is formed by a two-step etching process.
11. The antenna device of claim 10, wherein the first conductive layer and the third conductive layer are formed by a same etching process.
12. An electronic device, comprising:
a first substrate;
a multilayer electrode disposed on the first substrate, the multilayer electrode comprising:
a first conductive layer;
the second conducting layer is arranged on the first conducting layer; and
the third conducting layer is arranged on the second conducting layer;
the second substrate is arranged opposite to the first substrate; and
the liquid crystal layer is arranged between the first substrate and the second substrate;
wherein the third conductive layer includes a first portion that extends beyond the second conductive layer.
13. The electronic device of claim 12, wherein the first conductive layer includes a second portion that extends beyond the second conductive layer and contacts the first portion.
14. The electronic device of claim 12, wherein a material of the first conductive layer comprises titanium, molybdenum, a titanium alloy, a molybdenum alloy, indium zinc oxide, indium tin oxide, or a combination of the foregoing materials.
15. The electronic device of claim 12, wherein a material of the second conductive layer comprises copper, aluminum, a copper alloy, an aluminum alloy, or a combination of the foregoing materials.
16. The electronic device according to claim 12, wherein a material of the third conductive layer comprises titanium, molybdenum, a titanium alloy, a molybdenum alloy, indium zinc oxide, indium tin oxide, or a combination of the foregoing materials.
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