CN111509033B - 一种极化掺杂的sbd二极管及其制备方法 - Google Patents

一种极化掺杂的sbd二极管及其制备方法 Download PDF

Info

Publication number
CN111509033B
CN111509033B CN202010263036.4A CN202010263036A CN111509033B CN 111509033 B CN111509033 B CN 111509033B CN 202010263036 A CN202010263036 A CN 202010263036A CN 111509033 B CN111509033 B CN 111509033B
Authority
CN
China
Prior art keywords
layer
type
gan
doped
gan layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN202010263036.4A
Other languages
English (en)
Other versions
CN111509033A (zh
Inventor
高博
刘新科
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southwest University of Science and Technology
Original Assignee
Shenzhen Third Generation Semiconductor Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Third Generation Semiconductor Research Institute filed Critical Shenzhen Third Generation Semiconductor Research Institute
Priority to CN202010263036.4A priority Critical patent/CN111509033B/zh
Publication of CN111509033A publication Critical patent/CN111509033A/zh
Application granted granted Critical
Publication of CN111509033B publication Critical patent/CN111509033B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204Diodes
    • H01L29/66212Schottky diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提出一种极化掺杂的SBD二极管及其制备方法,所述SBD二极管结构自下而上依次为GaN衬底、n型GaN层、n型GaN层、渐变掺杂的AlGaN结构、嵌入所述n型GaN层的高阻区、位于所述GaN衬底底部的阴极和位于顶部所述GaN层上的阳极,其中渐变掺杂的AlxGa1‑xN结构底层为n‑AlGaN层,顶层为n‑GaN层,Al组分自下而上逐渐减小,其中0≤x≤1;所述高阻区上表面与顶部所述n‑GaN层共面。用渐变掺杂方法对n型区域进行极性掺杂,采用氧化层终端结构提高SBD击穿电压的同时解决正向导通电压低和正向导通电流小的问题。

Description

一种极化掺杂的SBD二极管及其制备方法
技术领域
本发明属于半导体器件领域,具体为一种极化掺杂的SBD二极管及其制备方法。
背景技术
肖特基二极管肖特基(Schottky)二极管,为一种低功耗、超高速半导体器件。最显著的特点为反向恢复时间极短(可以小到几纳秒),正向导通压降仅0.4V左右。其多用作高频、低压、大电流整流二极管、续流二极管、保护二极管,也有用在微波通信等电路中作整流二极管、小信号检波二极管使用。在通信电源、变频器等中比较常见。传统的SBD结构,在通过增大肖特基势垒高度,提升击穿电压的同时,存在增大正向导通电压、降低正向导通电流的缺点。
发明内容
为解决上述问题,本发明提供一种采用极化掺杂的SBD二极管,所述SBD二极管结构自下而上依次为GaN衬底、n型GaN层、n-型GaN层、渐变掺杂的n型AlGaN结构、嵌入所述n-型GaN层的高阻区、位于所述GaN衬底底部的阴极和位于顶部所述GaN层上的阳极,其中渐变掺杂的AlxGa1-xN结构底层为n-AlGaN层,顶层为n-GaN层,Al组分自下而上逐渐减小,其中0≤x≤1;所述高阻区上表面与顶部所述n-GaN层共面。
优选的,所述GaN衬底厚度为300μm-500μm。
优选的,所述n型GaN层厚度为5μm-12μm,所述n型GaN层为Si掺杂,掺杂的载流子浓度为5x1015 cm-3-8x1018 cm-3
优选的,所述n-型GaN层厚度为0.1μm-3μm,所述n-型GaN层为Si掺杂,掺杂的载流子浓度为1x1015 cm-3-9x1015 cm-3
优选的,所述渐变掺杂的n型AlxGa1-xN结构厚度为3nm-10nm。
基于同样的发明构思,本发明另提供一种极化掺杂的SBD二极管制备方法,包括如下步骤
步骤1:准备厚度为300μm-500μm的GaN衬底;
步骤2:在所述GaN衬底上依沉积长n型GaN层和n-型GaN层;
步骤3:在所述n-型GaN层上沉积渐变掺杂的n型AlxGa1-xN结构,使Al组分自下而上逐渐减小,渐变掺杂的n型AlxGa1-xN结构底层为n-AlGaN层,顶层为n-GaN层,其中0≤x ≤1。
步骤4:刻蚀所述渐变掺杂的n型AlxGa1-xN结构两端部和部分所述n-型GaN层并沉积氧化层形成高阻区;
步骤5:沉积和剥离工艺在顶层所述的n-GaN层沉积阳极,在所述GaN衬底底部形成阴极。
优选的,所述步骤2至步骤4生长方式为金属有机化学气相沉积或分子束外延。
优选的,所述步骤3选取氨气为N源,三甲基铝为Al源,三甲基镓为Ga源,H2为载气。
优选的,所述步骤4刻蚀方式为干法刻蚀或湿法刻蚀。
阳极金属与顶层的n-GaN层接触形成势垒,形成的势垒具有整流特性形成金属-半导体器件。由于n-GaN层中存在着大量的电子,阳极金属中仅有极少量的自由电子,所以电子便从浓度高的n-GaN层向浓度低的阳极金属中扩散。显然,金属阳极金属中没有空穴,也就不存在空穴自阳极金属向n-GaN层的扩散运动。随着电子不断从n-GaN层扩散到阳极金属,n- GaN层表面电子浓度逐渐降低,表面电中性被破坏,于是形成势垒,其电场方向为n-GaN层→阳极金属。但在该电场作用之下,阳极金属中的电子也会产生从阳极金属→n-GaN层的漂移运动,从而消弱了由于扩散运动而形成的电场。当建立起一定宽度的空间电荷区后,电场引起的电子漂移运动和浓度不同引起的电子扩散运动达到相对的平衡,便形成了肖特基势垒。
本发明中,n-AlGaN层及n-GaN层形成极性掺杂结构,利用渐变AlGaN材料诱导自由载流子的原理如下:
首先,当沿(0001)方向外延生长Al组分逐渐减小的AlGaN基材料时,由于AlGaN材料电偶极子强度随着Al组分降低而降低,沿(0001)面,随Al组分由高到低变化,会产生负净极化电荷,负净极化电荷可提高材料能带,从而提高施主杂质电离能,降低背景电子载流子产生概率同时,促进载流子的产生,从而进一步提高了肖特基势垒,增大反向击穿电压,降低漏电流;因此,利用极化效应可以提高AlGaN材料的载流子浓度,提高掺杂效率,增大器件的输出电流。
通过加入氧化层形成高阻区终端结构,降低了器件最大电场,从而引起器件击穿电压的增大。因此,通过极性掺杂和形成氧化层终端结构增大了器件击穿电压,提高掺杂效率,增大器件的输出电流。
有益效果:
(1)形成极性掺杂结构n-AlGaN层及n-GaN层,肖特基结势垒高度升高,将增大反向击穿电压,降低漏电流;
(2)外延生长薄层n-AlGaN及n-GaN时,形成极性掺杂层,增大肖特基势垒高度,理论上有增大正向导通电压、降低正向导通电流的缺点,但因为加入的是薄层n-AlGaN及n-GaN层,导致正向导通电压变化不大,正向导通电流也没有降低;
(3)通过加入氧化层形成终端结构,降低了器件最大电场,从而引起器件击穿电压的增大。
附图说明
图1-5为本发明实施例制备的采用极化掺杂的SBD二极管工艺流程图。
双面抛光的n型GaN衬底1,n型GaN层2,n-型GaN层3,AlGaN渐变结构4,SiO2氧化层5,Pt/Au阳极6,Ti/Al/Au阴极7。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本发明作进一步的详细说明。
实施例本实施例提供一种采用极化掺杂具有终端结构的新型SBD二极管制备方法
本实例的SBD二极管结构自下而上依次为GaN衬底、n型GaN层、n-型GaN层、渐变掺杂的n型AlGaN结构、嵌入所述n-型GaN层的高阻区、位于所述GaN衬底底部的阴极和位于顶部所述GaN层上的阳极,其中渐变掺杂的AlxGa1-xN结构底层为n-AlGaN层,顶层为 n-GaN层,Al组分自下而上逐渐减小,其中0≤x≤1;所述高阻区上表面与顶部所述n-GaN 层共面。
如图1-5所示,SBD二极管制备方法具体包括如下步骤:
步骤1:准备一个双面抛光的n型GaN衬底,厚度350μm,衬底掺杂浓度为1x1018 cm-3
步骤2:利用金属有机化学气相沉积(MOCVD)或者分子束外延(MBE)在GaN衬底上依次生长8μm,载流子浓度约为1x1017cm-3的n型Si掺杂GaN层和0.5μm的,载流子浓度约为8x1016cm-3的n-型Si掺杂的GaN层;氢基硅烷可以用为n型GaN中提供Si的原料;
步骤3:通过金属有机化学气相沉积(MOCVD)生长n掺杂的AlxGa1-xN形成渐变掺杂结构,AlxGa1-xN层厚度为5nm,其中Al和Ga组分范围依据AlxGa1-xN进行调节,其中x从 1到0,这样就形成了在渐变掺杂结构中底层部分为n-AlGaN层,然后逐渐渐变成n-GaN层结构;在通过金属有机化学气相沉积(MOCVD)生长形成AlxGa1-xN层时采用氨气(NH3),三甲基铝(TMA),三甲基镓分别作为N源,Al源和Ga源,H2为载气;
步骤4:通过干法或湿法进行刻蚀,在n掺杂的AlxGa1-xN结构两端部刻蚀,刻蚀深度至 n-型Si掺杂的GaN层内部,刻蚀厚度为0.35μm;之后再通过等离子体增强化学的气相沉积法(PECVD)或金属有机化学气相沉积(MOCVD)方法再生长一层SiO2氧化层高阻区材料;
步骤5:沉积和剥离脱离工艺在顶层n-GaN层形成器件阳极Pt/Au,厚度为40nm/100nm,最后在GaN衬底底部形成阴极Ti/Al/Au,厚度为50nm/200nm/50nm。
以上所述仅是本发明的较佳实施例而已,并非对本发明做任何形式的限制。虽然本发明已以较佳实例揭露如上,然而并非用以限定本发明。任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述所述的方法及技术内容做出些许的更改或修饰为等同变化的等效实施例,但凡是未脱离本发明技术发案的内容,依据本发明的技术实质对以上实例所做的任何简单修改、等同变化与修饰,仍属于本发明技术方案的范围。

Claims (9)

1.一种极化掺杂的SBD二极管,其特征在于:所述SBD二极管结构自下而上依次为位于GaN衬底底部的阴极、所述GaN衬底、n型GaN层、n-型GaN层、渐变掺杂的n型AlxGa1-xN结构和嵌入所述n-型GaN层的高阻区、位于顶部n-GaN层上的阳极,其中所述渐变掺杂的n型AlxGa1-xN结构底层为n-AlGaN层,顶层为所述n-GaN层,Al组分自下而上逐渐减小,其中0≤x≤1;所述高阻区上表面与顶部所述n-GaN层共面。
2.如权利要求1所述的SBD二极管,其特征在于:所述GaN衬底厚度为300μm -500μm。
3.如权利要求1所述的SBD二极管,其特征在于:所述n型GaN层厚度为5μm -12μm,所述n型GaN层为Si掺杂,掺杂的载流子浓度为5x1015 cm-3-8x1018 cm-3
4.如权利要求1所述的SBD二极管,其特征在于:所述n-型GaN层厚度为0.1μm -3μm,所述n-型GaN层为Si掺杂,掺杂的载流子浓度为1x1015 cm-3-9x1015 cm-3
5.如权利要求1所述的SBD二极管,其特征在于:所述渐变掺杂的n型AlxGa1-xN结构厚度为3nm-10nm。
6.一种极化掺杂的SBD二极管制备方法,其特征在于:包括如下步骤
步骤1:准备厚度为300μm -500μm的GaN衬底;
步骤2:在所述GaN衬底上依次沉积n型GaN层和n-型GaN层;
步骤3:在所述n-型GaN层上沉积渐变掺杂的n型AlxGa1-xN结构,使Al组分自下而上逐渐减小,渐变掺杂的n型AlxGa1-xN结构底层为n-AlGaN层,顶层为n-GaN层,其中0≤x≤1;
步骤4:刻蚀所述渐变掺杂的n型AlxGa1-xN结构两端部和部分所述n-型GaN层并沉积氧化层形成高阻区;
步骤5:沉积和剥离工艺在顶层所述n-GaN层沉积阳极,在所述GaN衬底底部形成阴极。
7.如权利要求6所述的SBD二极管制备方法,其特征在于:所述步骤2至步骤4生长方式为金属有机化学气相沉积或分子束外延。
8.如权利要求6所述的SBD二极管制备方法,其特征在于:所述步骤3选取氨气为N源,三甲基铝为Al源,三甲基镓为Ga源,H2为载气。
9.如权利要求6所述的SBD二极管制备方法,其特征在于:所述步骤4刻蚀方式为干法刻蚀或湿法刻蚀。
CN202010263036.4A 2020-04-07 2020-04-07 一种极化掺杂的sbd二极管及其制备方法 Expired - Fee Related CN111509033B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010263036.4A CN111509033B (zh) 2020-04-07 2020-04-07 一种极化掺杂的sbd二极管及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010263036.4A CN111509033B (zh) 2020-04-07 2020-04-07 一种极化掺杂的sbd二极管及其制备方法

Publications (2)

Publication Number Publication Date
CN111509033A CN111509033A (zh) 2020-08-07
CN111509033B true CN111509033B (zh) 2022-04-19

Family

ID=71877469

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010263036.4A Expired - Fee Related CN111509033B (zh) 2020-04-07 2020-04-07 一种极化掺杂的sbd二极管及其制备方法

Country Status (1)

Country Link
CN (1) CN111509033B (zh)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070096239A1 (en) * 2005-10-31 2007-05-03 General Electric Company Semiconductor devices and methods of manufacture
US20080067549A1 (en) * 2006-06-26 2008-03-20 Armin Dadgar Semiconductor component
KR20130014849A (ko) * 2011-08-01 2013-02-12 삼성전자주식회사 쇼트키 배리어 다이오드 및 이의 제조방법
US8836071B2 (en) * 2011-11-18 2014-09-16 Avogy, Inc. Gallium nitride-based schottky barrier diode with aluminum gallium nitride surface layer
CN103400864B (zh) * 2013-07-31 2016-12-28 中国电子科技集团公司第十三研究所 基于极化掺杂的GaN横向肖特基二极管
CN103887385B (zh) * 2014-03-13 2016-08-24 中国科学院半导体研究所 提高发光效率的极性面氮化镓基发光器件
US9899482B2 (en) * 2015-08-11 2018-02-20 Hrl Laboratories, Llc Tunnel barrier schottky
CN110137267A (zh) * 2019-05-15 2019-08-16 上海科技大学 一种垂直型氮化镓肖特基二极管器件及其制备方法

Also Published As

Publication number Publication date
CN111509033A (zh) 2020-08-07

Similar Documents

Publication Publication Date Title
US9362389B2 (en) Polarization induced doped transistor
US8981381B2 (en) GaN-based Schottky diode having dual metal, partially recessed electrode
US8981528B2 (en) GaN-based Schottky diode having partially recessed anode
CN106024914A (zh) 混合阳极电极结构的GaN基肖特基二极管及其制备方法
CN107978642B (zh) 一种GaN基异质结二极管及其制备方法
US20170033098A1 (en) GaN-BASED SCHOTTKY DIODE RECTIFIER
JP4474292B2 (ja) 半導体装置
US10297714B1 (en) Heterogeneous tunneling junctions for hole injection in nitride based light-emitting devices
US20130075748A1 (en) Method and system for diffusion and implantation in gallium nitride based devices
WO2014172164A2 (en) Method of fabricating a merged p-n junction and schottky diode with regrown gallium nitride layer
CN109950324A (zh) p型阳极的Ⅲ族氮化物二极管器件及其制作方法
CN115775730B (zh) 一种准垂直结构GaN肖特基二极管及其制备方法
CN111180335A (zh) 一种GaN基垂直二极管及其制备方法
CN111509033B (zh) 一种极化掺杂的sbd二极管及其制备方法
CN110752260A (zh) 新型GaN结势垒肖特基二极管及其制备方法
US11588096B2 (en) Method to achieve active p-type layer/layers in III-nitrtde epitaxial or device structures having buried p-type layers
CN114496788A (zh) 一种p型沟道氮化镓晶体管及其制备方法
CN110504327B (zh) 基于纳米阵列的弹道输运肖特基二极管及其制作方法
CN205911315U (zh) 混合阳极电极结构的GaN基肖特基二极管
CN103560146A (zh) 一种用于制备GaN异质结场效应晶体管的外延结构及生长方法
US20040104384A1 (en) Growth of high temperature, high power, high speed electronics
CN110634943B (zh) 利用MBE再生长的横向结构GaN基JFET器件及其制备方法
CN109817728B (zh) 一种pin二极管器件结构及其制备方法
US20130256688A1 (en) Nitride semiconductor schottky diode and method for manufacturing same
CN114927578A (zh) p-NiO或p-LiNiO/n-GaN异质结共振隧穿二极管及制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20230417

Address after: No. 1088, Xueyuan Avenue, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province

Patentee after: SOUTH University OF SCIENCE AND TECHNOLOGY OF CHINA

Address before: Taizhou building, No. 1088, Xueyuan Avenue, Xili University Town, Nanshan District, Shenzhen City, Guangdong Province

Patentee before: SHENZHEN THIRD GENERATION SEMICONDUCTOR Research Institute

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20220419

CF01 Termination of patent right due to non-payment of annual fee