CN111508422A - Pixel circuit, driving method thereof and display panel - Google Patents
Pixel circuit, driving method thereof and display panel Download PDFInfo
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- CN111508422A CN111508422A CN202010346404.1A CN202010346404A CN111508422A CN 111508422 A CN111508422 A CN 111508422A CN 202010346404 A CN202010346404 A CN 202010346404A CN 111508422 A CN111508422 A CN 111508422A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
Abstract
The embodiment of the invention discloses a pixel circuit, a driving method thereof and a display panel. Wherein the pixel circuit includes: the device comprises a data writing module, a driving transistor, a compensation module, a light emitting control module, a light emitting module, a first storage capacitor, at least one second storage capacitor and a storage control module corresponding to the second storage capacitors one to one; the storage control module is used for responding to a signal input by the first control end to control the second storage capacitor to be connected with the first pole of the driving transistor in a data writing stage, wherein the first pole of the driving transistor is electrically connected with the data writing module; the second storage capacitor is used for controlling the connection of the second storage capacitor and the grid electrode of the driving transistor in response to a signal input by the second control end in a light-emitting stage; the driving transistor is used for driving the light-emitting module to emit light according to the data voltage when the light-emitting control module is conducted. According to the technical scheme, the problem of flicker of the display panel during low-frequency display is solved, and meanwhile, the charging rate of the grid electrode of the driving transistor in the pixel circuit is ensured.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof and a display panel.
Background
As the demand for longer standby time of display products increases, low frequency display tends to be the trend.
A pixel circuit is generally included in the conventional display panel, wherein a storage capacitor for storing a gate voltage of a driving transistor is included in the pixel circuit.
However, the existing display panel has the problems that the improvement of the flicker phenomenon during low-frequency display and the guarantee of the grid charging rate of the driving transistor cannot be realized simultaneously.
Disclosure of Invention
The invention provides a pixel circuit, a driving method thereof and a display panel, which are used for improving the flicker problem of the display panel during low-frequency display and ensuring the charging rate of a grid electrode of a driving transistor in the pixel circuit.
In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a data writing module, a driving transistor, a compensation module, a light emitting control module, a light emitting module, a first storage capacitor, at least one second storage capacitor and a storage control module corresponding to the second storage capacitors one to one;
the data writing module is used for writing data voltage into the grid electrode of the driving transistor in a data writing stage, and the compensation module is used for writing a compensation signal containing threshold voltage information of the driving transistor into the grid electrode of the driving transistor before a light-emitting stage;
the first storage capacitor is electrically connected with the grid electrode of the driving transistor;
the storage control module comprises a first control end and a second control end, the storage control module is respectively electrically connected with the second storage capacitor, the grid electrode of the driving transistor and the first electrode of the driving transistor, and the storage control module is used for responding to a signal input by the first control end to control the connection of the second storage capacitor and the first electrode of the driving transistor in a data writing stage, wherein the first electrode of the driving transistor is electrically connected with the data writing module; the second storage capacitor is used for controlling the connection of the second storage capacitor and the grid electrode of the driving transistor in response to a signal input by the second control end in a light-emitting stage;
the driving transistor is used for driving the light-emitting module to emit light according to the data voltage when the light-emitting control module is conducted.
Optionally, the storage control module includes a first switch unit and a second switch unit, a control end of the first switch unit is used as a first control end of the storage control module, a first end of the first switch unit is electrically connected to a first pole of the driving transistor, a second end of the first switch unit is electrically connected to a first end of the second storage capacitor, and the first switch unit is configured to be turned on under control of an input signal at a control end of the first switch unit in a data writing stage;
the control end of the second switch unit is used as the second control end of the storage control module, the first end of the second switch unit is electrically connected with the grid electrode of the driving transistor, the second end of the second switch unit is electrically connected with the first end of the second storage capacitor, and the second switch unit is used for being conducted under the control of the input signal of the control end of the second switch unit in the light-emitting stage;
the first end of the first storage capacitor is electrically connected with the grid electrode of the driving transistor, and the second end of the first storage capacitor is electrically connected with the second end of the second storage capacitor.
Optionally, the capacitance value of the first storage capacitor is smaller than the capacitance value of the second storage capacitor.
Optionally, the control end of the data writing module and the control end of the compensation module are both electrically connected to the first scanning signal input end, the first end of the data writing module is electrically connected to the data voltage input end, and the second end of the data writing module is electrically connected to the first pole of the driving transistor;
the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;
the first control end of the storage control module is electrically connected with the first scanning signal input end.
Optionally, the first switch unit includes a first transistor, the data writing module includes a second transistor, and the compensation module includes a third transistor, where channel types of the first transistor, the second transistor, and the third transistor are the same.
Optionally, the light-emitting control module includes a first light-emitting control unit and a second light-emitting control unit, a control end of the first light-emitting control unit and a control end of the second light-emitting control unit are both electrically connected to the light-emitting control signal input end, and a first electrode of the driving transistor is electrically connected to the first power voltage input end through the first light-emitting control unit; the second pole of the driving transistor is electrically connected with the first end of the light-emitting module through the second light-emitting control unit, and the second end of the light-emitting module is electrically connected with the second power supply voltage input end;
the second end of the first storage capacitor and the second end of the second storage capacitor are both electrically connected with the first power supply voltage input end;
the second control end of the storage control module is electrically connected with the light-emitting control signal input end;
optionally, the second switch unit includes a fourth transistor, the first light emission control unit includes a fifth transistor, the second light emission control unit includes a sixth transistor, and channel types of the fourth transistor, the fifth transistor, and the sixth transistor are the same.
Optionally, the display device further includes a first initialization module, a control end of the first initialization module is electrically connected to the second scan signal input end, a first end of the first initialization module is electrically connected to the reference voltage input end, and a second end of the first initialization module is electrically connected to the gate of the driving transistor; optionally, the first initialization module and the compensation module include double-gate transistors;
optionally, the pixel circuit further includes a second initialization module, a control end of the second initialization module is electrically connected to the second scan signal input end, a first end of the second initialization module is electrically connected to the reference voltage input end, a second end of the second initialization module is electrically connected to the first end of the light emitting module, and a second end of the light emitting module is electrically connected to the second power voltage input end.
Optionally, a control end of the data writing module is electrically connected to the first scanning signal input end, a first end of the data writing module is electrically connected to the data voltage input end, and a second end of the data writing module is electrically connected to the first electrode of the driving transistor;
the control end of the compensation module is electrically connected with the second scanning signal input end, the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;
the first control end of the storage control module is electrically connected with the first scanning signal input end;
the pixel circuit further comprises a first initialization module, wherein the control end of the first initialization module is electrically connected with the third scanning signal input end, the first end of the first initialization module is electrically connected with the reference voltage input end, and the second end of the first initialization module is electrically connected with the second pole of the driving transistor;
the first initialization module and the compensation module are used for transmitting a signal input by the reference voltage input end to the grid electrode of the driving transistor in an initialization stage;
optionally, the pixel circuit further includes a second initialization module, where the second initialization module is configured to initialize a potential of the first end of the light emitting module in an initialization stage.
In a second aspect, an embodiment of the present invention further provides a driving method for a pixel circuit, for driving the pixel circuit of the first aspect, where the driving method for the pixel circuit includes:
in the data writing stage, controlling the second storage capacitor to be connected with the first pole of the driving transistor;
and in the light-emitting stage, controlling the second storage capacitor to be connected with the grid electrode of the driving transistor.
In a third aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in the first aspect.
According to the pixel circuit, the driving method thereof and the display panel provided by the embodiment of the invention, in the data writing stage, the storage control module controls the second storage capacitor to be electrically connected with the first electrode of the driving transistor, so that the data voltage is written into the second storage capacitor and the first storage capacitor at the same time in the data writing stage, and the storage capacitor connected with the grid electrode of the driving transistor is only provided with the first storage capacitor, so that the total capacitance value of the storage capacitor connected with the grid electrode of the driving transistor cannot be overlarge, and the grid electrode charging rate of the driving transistor can be further ensured; in the light-emitting stage, the storage control module controls the second storage capacitor to be electrically connected with the grid electrode of the driving transistor, the grid electrode of the driving transistor is connected with the first storage capacitor and the second storage capacitor, the potential of the grid electrode of the driving transistor is stored and maintained through the first storage capacitor and the second storage capacitor, the first storage capacitor and the second storage capacitor form a parallel structure, the total capacitance value of the storage capacitor connected with the grid electrode of the driving transistor is increased, the grid voltage stability of the driving transistor is favorably maintained, the stability of the driving current generated by the driving transistor is favorably ensured, and the flicker phenomenon during low-frequency display of the existing display panel is favorably improved. In addition, when the pixel circuit works in a data writing stage, the first storage capacitor and the second storage capacitor are charged simultaneously, and the problem that the charging rate is influenced by the fact that the grid electrode charge of the driving transistor rushes back to the second storage capacitor in a light emitting stage can be avoided.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 3 is a driving timing diagram of a pixel circuit according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 5 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 7 is a driving timing diagram of another pixel circuit according to an embodiment of the invention;
fig. 8 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, in the conventional display panel, there are problems that improvement of a flicker phenomenon at the time of low frequency display and assurance of a gate charging rate of a driving transistor cannot be simultaneously achieved. The inventors found that the above problems occur due to the following reasons: the conventional display panel generally includes a plurality of pixel circuits including a driving transistor driving a light emitting device to emit light, the driving transistor controlling light emission luminance of the light emitting device by controlling a driving current flowing through the light emitting device. In order to prolong the standby time of the display panel, the display panel needs to be controlled to perform low-frequency display, and during the low-frequency display, the number of frames displayed by the display panel per second is small, so that the time of the light-emitting device working in a light-emitting stage in one frame is increased, and the leakage time of the grid electrode of the driving transistor is prolonged. The too long leakage time of the gate of the driving transistor can cause the gate voltage of the driving transistor to be unstable, and the unstable gate voltage of the driving transistor causes the unstable driving current of the driving transistor for driving the light-emitting device to emit light, so that the light-emitting device flickers. However, since the gate voltage value of the driving transistor is equal to the ratio of the charging charge amount to the capacitance value of the storage capacitor, if the capacitance value of the storage capacitor is increased and it is ensured that the same voltage is written into the gate of the driving transistor, the charging charge amount of the storage capacitor needs to be increased. However, the pixel circuit has a limited time for charging the storage capacitor, and the increase of the amount of charge required by the storage capacitor causes the amount of charge required by the storage capacitor to be unable to be charged to the target amount of charge (i.e., the amount of charge required by the storage capacitor) within the limited time, which may cause the charging rate of the gate of the driving transistor to decrease. Therefore, the conventional display panel cannot improve the flicker phenomenon in the low-frequency display and ensure the charging rate of the gate of the driving transistor.
In view of the above problems, embodiments of the present invention provide a pixel circuit. Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 1, the pixel circuit includes: the data writing module 110, the driving transistor DT, the compensation module 120, the light emitting control module 130, the light emitting module 140, the first storage capacitor C1, at least one second storage capacitor C2, and the storage control modules 150 corresponding to the second storage capacitors C2 one to one; the data writing module 110 is used for writing a data voltage into the gate electrode of the driving transistor DT in a data writing phase, and the compensation module 120 is used for writing a compensation signal containing threshold voltage information of the driving transistor DT into the gate electrode of the driving transistor DT before a light emitting phase; the first storage capacitor C1 is electrically connected to the gate of the driving transistor DT; the memory control module 150 includes a first control terminal g1 and a second control terminal g2, and the memory control module 150 is electrically connected to the second storage capacitor C2, the gate of the driving transistor DT, and the first pole of the driving transistor DT, respectively, the memory control module 150 is configured to control the second storage capacitor C2 to be connected to the first pole of the driving transistor DT in response to a signal input from the first control terminal g1 during a data writing phase, wherein the first pole of the driving transistor DT is electrically connected to the data writing module 110; and is used for controlling the connection of the second storage capacitor C2 and the gate of the driving transistor DT in response to the signal input from the second control terminal g2 during the light-emitting period; the driving transistor DT is used to drive the light emitting module 140 to emit light according to the data voltage when the light emitting control module 130 is turned on.
Referring to fig. 1, in particular, when the pixel circuit operates, the operation timing generally includes at least a data writing phase and a light emitting phase. In the data writing phase, the data writing module 110 and the compensation module 120 are controlled to be turned on, and the data voltage is written to the gate of the driving transistor DT and one end of the first storage capacitor C1 through the data writing module 110, the driving transistor DT and the compensation module 120, so that the writing of the data voltage at the gate of the driving transistor DT, the charging of the first storage capacitor C1 and the threshold voltage compensation of the driving transistor DT are realized. Meanwhile, in the data writing phase, the storage control module 150 may control the connection between the second storage capacitor C2 and the driving transistor DT according to the signal input from the first control terminal g1, and the data voltage is also written into the second storage capacitor C2 through the data writing module 110 to charge the second storage capacitor C2; in the light emitting phase, the light emitting control module 130 is controlled to be turned on, so that the driving transistor DT drives the light emitting module 140 to emit light according to the data voltage written by the gate thereof. In addition, in the light emitting phase, the storage control module 150 controls the second storage capacitor C2 to be connected to the gate of the driving transistor DT according to a signal input from the second control terminal g2, so that the first storage capacitor C1 and the second storage capacitor C2 form a parallel structure, and the first storage capacitor C1 and the second storage capacitor C2 are both electrically connected to the gate of the driving transistor DT, so that the total capacitance of the storage capacitors connected to the driving transistor DT is increased, and the potential of the gate of the driving transistor DT is well maintained.
According to the pixel circuit provided by the embodiment of the invention, in the data writing stage, the storage control module controls the second storage capacitor to be electrically connected with the first electrode of the driving transistor, so that the data voltage is written into the second storage capacitor and the first storage capacitor at the same time in the data writing stage, and the storage capacitor connected with the grid electrode of the driving transistor is only provided with the first storage capacitor, so that the total capacitance value of the storage capacitors connected with the grid electrode of the driving transistor is not too large, and the grid electrode charging rate of the driving transistor can be further ensured; in the light-emitting stage, the storage control module controls the second storage capacitor to be electrically connected with the grid electrode of the driving transistor, the grid electrode of the driving transistor is connected with the first storage capacitor and the second storage capacitor, the potential of the grid electrode of the driving transistor is stored and maintained through the first storage capacitor and the second storage capacitor, the first storage capacitor and the second storage capacitor form a parallel structure, the total capacitance value of the storage capacitor connected with the grid electrode of the driving transistor is increased (the sum of the capacitance values of the first storage capacitor and the second storage capacitor), the grid voltage stability of the driving transistor is favorably maintained, the stability of the driving current generated by the driving transistor is favorably ensured, and the flicker phenomenon during low-frequency display of the existing display panel is favorably improved. In addition, when the pixel circuit works in a data writing stage, the first storage capacitor and the second storage capacitor are charged simultaneously, so that when the second storage capacitor is connected with the grid electrode of the driving transistor in a light emitting stage, the potential of the first end of the second storage capacitor is the same as the potential of the grid electrode of the driving transistor (namely the potential of the first end of the first storage capacitor), and the influence of the reverse charging of the grid electrode charge of the driving transistor to the second storage charge in the light emitting stage on the charging rate is avoided.
It should be noted that the pixel circuit shown in fig. 1 is only a schematic structure of the embodiment of the present invention, and exemplarily shows that the pixel circuit includes only one second storage capacitor C2 and its corresponding storage control module 150, in practical applications, the pixel circuit of the embodiment of the present invention may also have other structures, and the number of the second storage capacitors C2 and their corresponding storage control modules 150 in the pixel circuit may be set according to practical requirements, which is not limited in the embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, where the pixel circuit may correspond to an embodiment of the pixel circuit shown in fig. 1. As shown in fig. 2, optionally, the storage control module 150 is arranged to include a first switch unit 151 and a second switch unit 152, a control terminal of the first switch unit 151 is used as a first control terminal g1 of the storage control module 150, a first terminal of the first switch unit 151 is electrically connected to the first pole of the driving transistor DT, a second terminal of the first switch unit 151 is electrically connected to a first terminal of the second storage capacitor C2, and the first switch unit 151 is configured to be turned on under the control of an input signal at its control terminal in the data writing phase; the control terminal of the second switch unit 152 is used as the second control terminal g2 of the storage control module 150, the first terminal of the second switch unit 152 is electrically connected to the gate of the driving transistor DT, the second terminal of the second switch unit 152 is electrically connected to the first terminal of the second storage capacitor C2, and the second switch unit 152 is configured to be turned on under the control of the input signal of its control terminal during the light-emitting phase; a first terminal of the first storage capacitor C1 is electrically connected to the gate of the driving transistor DT, and a second terminal of the first storage capacitor C1 and a second terminal of the second storage capacitor C2 are electrically connected.
Referring to fig. 2, for example, in the data writing phase, the data writing module 110, the compensation module 120 and the first switching unit 151 are controlled to be turned on, and the second switching unit 152 is controlled to be turned off, and the data voltage is written to the gate of the driving transistor DT and the first terminal of the first storage capacitor C1 through the data writing module 110, the driving transistor DT and the compensation module 120, and written to the first terminal of the second storage capacitor C2 through the data writing module 110. In the data writing phase, the same data voltage is written into the first storage capacitor C1 and the second storage capacitor C2 at the same time. In the data writing phase, the second storage capacitor C1 is electrically connected to the first pole of the driving transistor DT, and only the first storage capacitor C1 is used as a storage capacitor for the gate potential of the driving transistor DT, so that the total capacitance of the capacitor connected to the gate of the driving transistor DT is small, thereby ensuring that the gate of the driving transistor DT can be charged at a high rate. In the light emitting stage, the second switch unit 152 and the light emitting control module 130 are controlled to be turned on, the first switch unit 151 is controlled to be turned off, the first end of the first storage capacitor C1 and the first end of the second storage capacitor C2 are both electrically connected with the gate of the driving transistor DT, the first storage capacitor C1 and the second storage capacitor C2 after being connected in parallel are used as storage capacitors of the gate potential of the driving transistor DT, the capacitance value of the storage capacitor of the gate of the driving transistor DT is the sum of the capacitance values of the first storage capacitor C1 and the second storage capacitor C2, and the capacitance value of the storage capacitor is further increased, so that the gate voltage of the driving transistor DT can be well maintained, and further the gate voltage of the driving transistor DT is relatively stable, and the driving current generated by the driving transistor DT is relatively stable, and further the low-frequency flicker phenomenon of the display panel. In addition, since the data voltage is written into the first storage capacitor C1 and the second storage capacitor C2 simultaneously in the data writing phase, when the second storage capacitor C2 is connected to the gate of the driving transistor DT in the light emitting phase, the potential of the gate of the driving transistor DT (i.e., the potential of the first end of the first storage capacitor C1) is the same as the potential of the first end of the second storage capacitor C2, thereby preventing the influence of the reverse charging of the gate charge of the driving transistor DT to the second storage charge C2 in the light emitting phase on the charging rate.
With continued reference to fig. 2, optionally, the capacitance value of the first storage capacitor C1 is set to be smaller than the capacitance value of the second storage capacitor C2. Specifically, when the pixel circuit operates in the data writing phase, a data voltage is written into the first storage capacitor C1 and the gate of the driving transistor DT; when the pixel circuit operates in a light-emitting phase, the potential of the gate of the driving transistor DT is stored and held simultaneously by the first storage capacitor C1 and the second storage capacitor C2, and the capacitance value of the storage capacitor of the gate of the driving transistor DT is the sum of the capacitance values of the first storage capacitor C1 and the second storage capacitor C2. By setting the capacitance value of the first storage capacitor C1 to be smaller than the capacitance value of the second storage capacitor C2, the total capacitance value of the storage capacitor connected to the gate of the driving transistor DT in the data writing phase can be further made smaller, thereby ensuring the charging rate; meanwhile, the total storage capacitance value connected with the grid electrode of the driving transistor DT can be ensured to be larger in the light-emitting stage, and the good holding effect on the grid electrode potential of the driving transistor DT in the light-emitting stage is further ensured.
With continued reference to fig. 1 and fig. 2, optionally, the control terminal of the data writing module 110 and the control terminal of the compensation module 120 are both electrically connected to the first Scan signal input terminal Scan1, the first terminal of the data writing module 110 is electrically connected to the data voltage input terminal Vdata, and the second terminal of the data writing module 110 is electrically connected to the first pole of the driving transistor DT; a first end of the compensation module 120 is electrically connected with the second pole of the driving transistor DT, and a second end of the compensation module 120 is electrically connected with the gate of the driving transistor DT; the first control terminal g1 of the memory control module 150 is electrically connected to the first Scan signal input terminal Scan 1.
Illustratively, in the data writing phase, the control terminal of the data writing module 110 and the compensation module 120 are turned on according to the first Scan signal input by the first Scan signal input terminal Scan1, and the data voltage signal of the data voltage input terminal Vdata is written into the gate of the driving transistor DT and the first terminal of the first storage capacitor C1 through the data writing module 110, the driving transistor DT and the compensation module 120, so that the writing of the data voltage of the gate of the driving transistor DT, the charging of the first storage capacitor C1 and the threshold voltage compensation of the driving transistor DT are realized. Meanwhile, in the data writing phase, the storage control module 150 controls the second storage capacitor C2 to be electrically connected to the first pole of the driving transistor DT according to the signal of the first Scan signal terminal Scan1, specifically, the first switch unit 151 is turned on according to the first Scan signal input by the first Scan signal input terminal Scan1, and the data voltage signal of the data voltage input terminal Vdata is further written into the first terminal of the second storage capacitor C2 through the data writing module 110 and the first switch unit 151 to charge the second storage capacitor C2.
In conjunction with fig. 1 and 2, on the basis of the above scheme, it may be arranged that the first switching unit 151 includes a first transistor T1, the data writing module 110 includes a second transistor T2, the compensation module 120 includes a third transistor T3, and the channel types of the first transistor T1, the second transistor T2 and the third transistor T3 are the same.
Specifically, the channel types of the first transistor T1, the second transistor T2, and the third transistor T3 may be both N-channel or P-channel, and fig. 2 exemplarily shows a case where the channel types of the first transistor T1, the second transistor T2, and the third transistor T3 are both P-channel. Referring to fig. 2, since the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on during the data writing phase and turned off during the light emitting phase, the first transistor T1, the second transistor T2, and the third transistor T3 are set to be the same type, so that it can be ensured that the first transistor T1, the second transistor T2, and the third transistor T3 are turned on and off in the same state under the same signal control, and further, the first transistor T1, the second transistor T2, and the third transistor T3 can be simultaneously controlled by the same first Scan signal input from the first Scan signal input terminal Scan 1. For example, the gates of the first transistor T1, the second transistor T2, and the third transistor T3 may be connected to the same scan line, thereby reducing the wiring of the display panel including the pixel circuit and simplifying the wiring structure of the display panel.
With reference to fig. 1 and fig. 2, optionally, the light emission control module 130 includes a first light emission control unit 131 and a second light emission control unit 132, a control terminal of the first light emission control unit 131 and a control terminal of the second light emission control unit 132 are both electrically connected to the light emission control signal input terminal EM, and a first electrode of the driving transistor DT is electrically connected to the first power voltage input terminal Vdd through the first light emission control unit 131; the second pole of the driving transistor DT is electrically connected to the first end of the light emitting module 140 through the second light emission control unit 132, and the second end of the light emitting module 140 is electrically connected to the second power voltage input terminal Vss; the second end of the first storage capacitor C1 and the second end of the second storage capacitor C2 are both electrically connected to the first power voltage input terminal Vdd; the second control terminal g2 of the memory control module 150 is electrically connected to the emission control signal input terminal EM.
Specifically, in conjunction with fig. 1 and 2, in the light emitting phase, the first light emitting control unit 131 and the second light emitting control unit 132 are turned on according to the light emitting control signal input by the light emitting control signal input terminal EM. The light emitting module 140 may include a light emitting device D1, the light emitting device D1 may be an organic light emitting device, an anode of the organic light emitting device D1 may serve as a first end of the light emitting module 140, and a cathode of the organic light emitting device D1 may serve as a second end of the light emitting module 140. Meanwhile, in the light emitting stage, the second switch unit 152 is turned on according to the light emitting control signal input by the light emitting control signal input end EM, the first end of the second storage capacitor C2 is connected to the gate of the driving transistor DT, and the first storage capacitor C1 and the second storage capacitor C2 are simultaneously used as storage capacitors for the gate potential of the driving transistor DT, so that the gate voltage of the driving transistor DT is maintained stable, the driving transistor DT is ensured to control the light emitting device D1 to emit light normally, and the flicker phenomenon of the display panel during low-frequency display is avoided.
With reference to fig. 1 and fig. 2, on the basis of the above scheme, optionally, the second switching unit 152 includes a fourth transistor T4, the first light emission control unit 131 includes a fifth transistor T5, the second light emission control unit 132 includes a sixth transistor T6, and the channel types of the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are the same. The channel types of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be the same N-channel or P-channel, and fig. 2 exemplarily shows a case where the channel types of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are the same P-channel. Referring to fig. 2, since the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off in the data writing stage and turned on in the light emitting stage, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are provided in the same type, so that the on and off states of the first transistor T1, the second transistor T2, and the third transistor T3 under the same signal control can be ensured to be the same, and further, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be simultaneously controlled by the same light emitting control signal input from the light emitting control signal input terminal EM, for example, the gates of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be connected to the same light emitting control line, and thus, the wiring of the display panel including the pixel circuit can be reduced, and the wiring structure of the display panel can be simplified.
Fig. 3 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention, where the driving timing diagram is applicable to the pixel circuits shown in fig. 1 and fig. 2, and an example of the operation of the pixel circuit shown in fig. 2 is taken as an example for illustration. In this embodiment, each transistor included in the pixel circuit provided in this embodiment may be a P-type transistor or an N-type transistor, and in this embodiment and the following embodiments, the transistors included in the pixel circuit are all P-type transistors (for the on control signal of the P-type transistor, the on control signal is a low level signal).
With reference to fig. 2 and 3, the operation process of the pixel circuit includes a data writing phase t11 and a light emitting phase t12, and the specific operation process is as follows.
In the data writing phase T11, the light emission control signal input terminal EM inputs a high level signal, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The first Scan signal input terminal Scan1 inputs a low level signal, the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, the data voltage input terminal Vdata inputs a data voltage signal, and the data voltage is written into the gate of the driving transistor DT and the first storage capacitor C1 through the second transistor T2, the driving transistor DT and the third transistor T3, thereby implementing the writing of the gate data voltage of the driving transistor DT, the charging of the first storage capacitor C1 and the threshold voltage compensation of the driving transistor DT. Meanwhile, the data voltage is also written into the second storage capacitor C2 through the second transistor T2 and the first transistor T1, and the first storage capacitor C1 and the second storage capacitor C2 realize synchronous charging. In the data writing phase t11, the first storage capacitor C1 alone serves as a gate potential storage capacitor of the driving transistor DT to secure a gate charging rate of the driving transistor DT.
In the light emitting period T12, the first Scan signal input terminal Scan1 inputs a high level signal, and the first transistor T1, the second transistor T2, and the third transistor T3 are turned off. The light emission control signal input terminal EM inputs a low level signal, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on, and simultaneously the driving transistor DT is turned on, and the driving transistor DT drives the light emitting device D1 to emit light. In the light-emitting period t12, the first storage capacitor C1 and the second storage capacitor C2 are both connected to the gate of the driving transistor DT, and the first storage capacitor C1 and the second storage capacitor C2 connected in parallel are simultaneously used as the gate potential storage capacitor of the driving transistor DT, so that the gate voltage of the driving transistor DT can be effectively kept stable, and the flicker phenomenon of the display panel during low-frequency display can be improved.
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. As shown in fig. 4, optionally, the pixel circuit further includes a first initialization block 160, a control terminal of the first initialization block 160 is electrically connected to the second Scan signal input terminal Scan2, a first terminal of the first initialization block 160 is electrically connected to the reference voltage input terminal Vref, and a second terminal of the first initialization block 160 is electrically connected to the gate of the driving transistor DT.
Optionally, the first initialization module 160 and the compensation module 120 include double gate transistors. Specifically, the first initialization module 160 includes a ninth transistor T9, and the compensation module 120 includes an eighth transistor T8. Since the first initialization module 160 and the compensation module 120 are directly electrically connected to the gate of the driving transistor DT, and the eighth transistor T8 and the ninth transistor T9 are both double-gate transistors, when the display panel operates in the low frequency mode, the leakage current of the eighth transistor T8 and the ninth transistor T9 can be reduced, thereby further maintaining the stability of the gate voltage of the driving transistor DT and improving the flicker phenomenon of the display panel during low frequency display.
With continued reference to fig. 4, optionally, the pixel circuit further includes a second initialization module 170, a control terminal of the second initialization module 170 is electrically connected to the second Scan signal input terminal Scan2, a first terminal of the second initialization module 170 is electrically connected to the reference voltage input terminal Vref, a second terminal of the second initialization module 170 is electrically connected to the first terminal of the light emitting module 140, and a second terminal of the light emitting module 140 is electrically connected to the second power supply voltage input terminal Vss. Optionally, the second initialization module 170 includes a seventh transistor T7.
Fig. 5 is a timing diagram of another driving sequence of the pixel circuit according to the embodiment of the invention, which can be applied to the pixel circuit shown in fig. 4. The operation of the pixel circuit shown in fig. 4 will be described with reference to fig. 4 and 5. The operation timing of the pixel circuit shown in fig. 4 includes an initialization phase t21, a data writing phase t22, and a light emitting phase t 23.
In the initialization period T21, the light emission control signal input terminal EM inputs a high level signal, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The first Scan signal input terminal Scan1 inputs a high level signal, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. The second Scan signal input terminal Scan2 inputs a low level signal, and the seventh transistor T7 and the ninth transistor T9 are turned on. The reference voltage signal is input to the reference voltage input terminal Vref, the reference voltage is written to the gate of the driving transistor DT through the ninth transistor T9, and the potential of the gate of the driving transistor DT is initialized to the potential of the reference voltage. The reference voltage is also written to the anode of the light emitting device D1 through the seventh transistor T7, and the potential of the first terminal of the light emitting device D1 is also initialized to the potential of the reference voltage.
In the data writing phase T22, the light emission control signal input terminal EM inputs a high level signal, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The second Scan signal input terminal Scan2 inputs a high level signal, and the seventh transistor T7 and the ninth transistor T9 are turned off. The first Scan signal input terminal Scan1 inputs a low level signal, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned on. The data voltage signal is input to the data voltage input terminal Vdata, and the data voltage is written to the gate of the driving transistor DT and the first storage capacitor C1 through the second transistor T2, the driving transistor DT, and the eighth transistor T8, thereby implementing the writing of the data voltage to the gate of the driving transistor DT, the charging of the first storage capacitor C1, and the threshold voltage compensation of the driving transistor DT. Meanwhile, the data voltage is also written into the second storage capacitor C2 through the second transistor T2 and the first transistor T1, and the first storage capacitor C1 and the second storage capacitor C2 realize synchronous charging.
In the light emitting period T23, the second Scan signal input terminal Scan2 inputs a high level signal, and the seventh transistor T7 and the ninth transistor T9 are turned off. The first Scan signal input terminal Scan1 inputs a high level signal, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off. The light emission control signal input terminal EM inputs a low level signal, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor DT is turned on while the driving transistor DT drives the light emitting device D1 to emit light. In the light-emitting period t23, the first storage capacitor C1 and the second storage capacitor C2 are both connected to the gate of the driving transistor DT, and the first storage capacitor C1 and the second storage capacitor C2 connected in parallel are simultaneously used as the gate potential storage capacitor of the driving transistor DT, so that the gate voltage of the driving transistor DT can be effectively kept stable, and the flicker phenomenon of the display panel during low-frequency display can be improved.
Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. As shown in fig. 6, optionally, the control terminal of the data writing module 110 is electrically connected to the first Scan signal input terminal Scan1, the first terminal of the data writing module 110 is electrically connected to the data voltage input terminal Vdata, and the second terminal of the data writing module 110 is electrically connected to the first pole of the driving transistor DT; the control terminal of the compensation module 120 is electrically connected to the second Scan signal input terminal Scan2, the first terminal of the compensation module 120 is electrically connected to the second pole of the driving transistor DT, and the second terminal of the compensation module 120 is electrically connected to the gate of the driving transistor DT; the first control terminal g1 of the memory control module 150 is electrically connected to the first Scan signal input terminal Scan 1.
Referring to fig. 6, the pixel circuit further includes a first initializing module 160, a control terminal of the first initializing module 160 is electrically connected to the third Scan signal input terminal Scan3, a first terminal of the first initializing module 160 is electrically connected to the reference voltage input terminal Vref, and a second terminal of the first initializing module 160 is electrically connected to the second pole of the driving transistor DT; the first initialization module 160 and the compensation module 120 are configured to transmit a signal input from the reference voltage input terminal Vref to the gate of the driving transistor DT during an initialization phase. Compared with the pixel circuit shown in fig. 4 and the pixel circuit shown in fig. 6, in the pixel circuit shown in fig. 4, the first initialization block 160 (the ninth transistor T9) is directly electrically connected to the gate of the driving transistor DT, and in the pixel circuit shown in fig. 6, the first initialization block 160 (the ninth transistor T9) is not directly electrically connected to the gate of the driving transistor DT, so that the leakage path of the gate potential of the driving transistor DT can be reduced, the stability of the gate voltage of the driving transistor DT is further maintained, and the flicker phenomenon during the low-frequency display of the display panel can be improved.
With continued reference to fig. 6, the pixel circuit preferably further includes a second initialization module 170, and the second initialization module 170 is configured to initialize the potential of the first terminal of the light emitting module 140 in an initialization phase.
Fig. 7 is a timing diagram of another driving sequence of the pixel circuit according to the embodiment of the invention, which can be applied to the pixel circuit shown in fig. 6. The operation of the pixel circuit shown in fig. 6 will be described with reference to fig. 6 and 7. The operation timing of the pixel circuit shown in fig. 6 includes an initialization phase t31, a data writing phase t32, and a light emitting phase t 33.
In the initialization period T31, the light emission control signal input terminal EM inputs a high level signal, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The first Scan signal input terminal Scan1 inputs a high level signal, and the first transistor T1 and the second transistor T2 are turned off. The second Scan signal input terminal Scan2 inputs a low level signal, and the eighth transistor T8 is turned on. The third Scan signal input terminal Scan3 inputs a low level signal, and the seventh transistor T7 and the ninth transistor T9 are turned on. A reference voltage signal is input to the reference voltage input terminal Vref, and the reference voltage is written into the gate of the driving transistor DT through the ninth transistor T9 and the eighth transistor T8, so that the initialization of the gate potential of the driving transistor DT is realized. The reference voltage is also written to the anode of the light emitting device D1 through the seventh transistor T7, and the potential of the first terminal of the light emitting device D1 is also initialized to the potential of the reference voltage.
In the data writing phase T32, the light emission control signal input terminal EM inputs a high level signal, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The third Scan signal input terminal Scan3 inputs a high level signal, and the seventh transistor T7 and the ninth transistor T9 are turned off. The first Scan signal input terminal Scan1 inputs a low level signal, and the first transistor T1 and the second transistor T2 are turned on. The second Scan signal input terminal Scan2 inputs a low level signal, and the eighth transistor T8 is turned on. The data voltage signal is input to the data voltage input terminal Vdata, and the data voltage is written to the gate of the driving transistor DT and the first storage capacitor C1 through the second transistor T2, the driving transistor DT, and the eighth transistor T8, thereby implementing the writing of the data voltage to the gate of the driving transistor DT, the charging of the first storage capacitor C1, and the threshold voltage compensation of the driving transistor DT. Meanwhile, the data voltage is also written into the second storage capacitor C2 through the second transistor T2 and the first transistor T1, and the first storage capacitor C1 and the second storage capacitor C2 realize synchronous charging. In the data writing phase t32, the first storage capacitor C1 alone serves as a gate potential storage capacitor of the driving transistor DT to secure a gate charging rate of the driving transistor DT.
In the light emitting period T33, the light emission control signal input terminal EM inputs a low level signal, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on. The driving transistor DT drives the light emitting device D1 to emit light. In the light-emitting period t33, the first storage capacitor C1 and the second storage capacitor C2 are both connected to the gate of the driving transistor DT, and the first storage capacitor C1 and the second storage capacitor C2 connected in parallel are simultaneously used as the gate potential storage capacitor of the driving transistor DT, so that the gate voltage of the driving transistor DT can be effectively kept stable, and the flicker phenomenon of the display panel during low-frequency display can be improved.
Embodiments of the present invention further provide a driving method for a pixel circuit, where the driving method can be used to drive the pixel circuit provided in any of the above embodiments of the present invention. Fig. 8 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present invention, and referring to fig. 8, the driving method of the pixel circuit specifically includes:
and S110, controlling the second storage capacitor to be connected with the first pole of the driving transistor in the data writing stage.
A driving method of a pixel circuit according to an embodiment of the present invention is described with reference to fig. 1. As shown in fig. 1, when the pixel circuit operates in the data writing phase, the data voltage charges the first storage capacitor C1 and the second storage capacitor C2 at the same time, the gate of the driving transistor DT is connected to the first storage capacitor C1, and the potential of the gate of the driving transistor DT is stored and held by the first storage capacitor C1, so that the gate voltage of the driving transistor DT is kept stable and the charging rate of the gate of the driving transistor DT is ensured since the capacitance value of the single first storage capacitor C1 in the pixel circuit is not too large.
And S120, controlling the second storage capacitor to be connected with the grid electrode of the driving transistor in the light-emitting stage.
With continued reference to fig. 1, when the pixel circuit operates in the light-emitting phase, the gate of the driving transistor DT is connected to the first storage capacitor C1 and the second storage capacitor C2, and the potential of the gate of the driving transistor DT is stored and held simultaneously by the first storage capacitor C1 and the second storage capacitor C2, so that the storage capacitor of the gate of the driving transistor DT is the first storage capacitor C1 and the second storage capacitor C2 which are connected in parallel, and the capacitance value of the storage capacitor is the sum of the capacitance values of the first storage capacitor C1 and the second storage capacitor C2, so that the storage capacitor of the gate of the driving transistor DT is increased, which is beneficial to keeping the gate voltage of the driving transistor DT stable.
The pixel circuit provided by the embodiment can maintain the stable grid voltage of the driving transistor when the pixel circuit works in the light-emitting stage, does not influence the normal light emission of the display panel, is beneficial to improving the flicker phenomenon of the existing display panel during low-frequency display, and simultaneously ensures the grid charging rate of the driving transistor, so that the display panel can normally work in the low-frequency state to prolong the standby time of the display panel. In addition, when the pixel circuit works in a data writing stage, the first storage capacitor and the second storage capacitor are charged simultaneously, and the phenomenon that grid charges of the driving transistor reversely rush to the second storage capacitor in a light emitting stage can be avoided.
Fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 9, a display device 200 according to an embodiment of the present invention includes a pixel circuit according to any embodiment of the present invention. The display panel 200 further includes a scan driving circuit 210, a data driving circuit 220, and a driving chip 230, the data driving circuit 220 being integrated in the driving chip 230, and a plurality of data lines (D1, D2, D3 … …), a plurality of scan lines (S1, S2, S3 … …); the port of the scan driving circuit 210 is electrically connected to the scan line, and the port of the data driving circuit 220 is electrically connected to the data line. Taking the display device shown in fig. 9 including the pixel circuit shown in fig. 1 as an example, in conjunction with fig. 1 and 9, the pixel circuit includes a data voltage input terminal Vdata and a first Scan signal input terminal Scan1, the data voltage input terminal Vdata of each pixel circuit is connected to one data line, the first Scan signal input terminal Scan1 of each pixel circuit is connected to one Scan line, and fig. 9 schematically shows the data voltage input terminal Vdata and the first Scan signal input terminal Scan1 of the pixel circuit corresponding to one pixel. The display device provided by the embodiment of the invention comprises the pixel circuit provided by any embodiment of the invention, so that the display device has the beneficial effects, and the description is omitted.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A pixel circuit, comprising: the device comprises a data writing module, a driving transistor, a compensation module, a light emitting control module, a light emitting module, a first storage capacitor, at least one second storage capacitor and a storage control module corresponding to the second storage capacitors one to one;
the data writing module is used for writing data voltage into the grid electrode of the driving transistor in a data writing phase, and the compensation module is used for writing a compensation signal containing threshold voltage information of the driving transistor into the grid electrode of the driving transistor before a light-emitting phase;
the first storage capacitor is electrically connected with the grid electrode of the driving transistor;
the storage control module comprises a first control end and a second control end, the storage control module is respectively connected with the second storage capacitor, the grid electrode of the driving transistor and the first pole of the driving transistor, the storage control module is used for responding to a signal input by the first control end to control the second storage capacitor to be connected with the first pole of the driving transistor in a data writing phase, and the first pole of the driving transistor is electrically connected with the data writing module; the second storage capacitor is controlled to be connected with the grid electrode of the driving transistor in response to a signal input by the second control end in a light-emitting stage;
the driving transistor is used for driving the light-emitting module to emit light according to the data voltage when the light-emitting control module is switched on.
2. The pixel circuit according to claim 1, wherein the storage control module comprises a first switch unit and a second switch unit, a control terminal of the first switch unit serves as a first control terminal of the storage control module, a first terminal of the first switch unit is electrically connected to the first pole of the driving transistor, a second terminal of the first switch unit is electrically connected to a first terminal of the second storage capacitor, and the first switch unit is configured to be turned on under control of a signal input from the control terminal thereof in a data writing phase;
the control end of the second switch unit is used as a second control end of the storage control module, the first end of the second switch unit is electrically connected with the grid electrode of the driving transistor, the second end of the second switch unit is electrically connected with the first end of the second storage capacitor, and the second switch unit is used for being conducted under the control of a signal input from the control end of the second switch unit in a light-emitting stage;
the first end of the first storage capacitor is electrically connected with the grid electrode of the driving transistor, and the second end of the first storage capacitor is electrically connected with the second end of the second storage capacitor.
3. The pixel circuit according to claim 1, wherein a capacitance value of the first storage capacitor is smaller than a capacitance value of the second storage capacitor.
4. The pixel circuit according to claim 2, wherein the control terminal of the data writing module and the control terminal of the compensation module are electrically connected to a first scan signal input terminal, the first terminal of the data writing module is electrically connected to a data voltage input terminal, and the second terminal of the data writing module is electrically connected to the first pole of the driving transistor;
the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;
the first control end of the storage control module is electrically connected with the first scanning signal input end.
5. The pixel circuit according to claim 4, wherein the first switching unit comprises a first transistor, the data writing module comprises a second transistor, and the compensation module comprises a third transistor, wherein the first transistor, the second transistor, and the third transistor are of the same channel type.
6. The pixel circuit according to claim 2, wherein the light emission control module comprises a first light emission control unit and a second light emission control unit, a control terminal of the first light emission control unit and a control terminal of the second light emission control unit are both electrically connected to a light emission control signal input terminal, and a first electrode of the driving transistor is electrically connected to a first power supply voltage input terminal through the first light emission control unit; the second pole of the driving transistor is electrically connected with the first end of the light-emitting module through the second light-emitting control unit, and the second end of the light-emitting module is electrically connected with the second power supply voltage input end;
the second end of the first storage capacitor and the second end of the second storage capacitor are both electrically connected with the first power supply voltage input end;
the second control end of the storage control module is electrically connected with the light-emitting control signal input end;
preferably, the second switching unit includes a fourth transistor, the first light emission control unit includes a fifth transistor, the second light emission control unit includes a sixth transistor, and channel types of the fourth transistor, the fifth transistor, and the sixth transistor are the same.
7. The pixel circuit according to claim 1, further comprising a first initialization module, wherein a control terminal of the first initialization module is electrically connected to the second scan signal input terminal, a first terminal of the first initialization module is electrically connected to the reference voltage input terminal, and a second terminal of the first initialization module is electrically connected to the gate of the driving transistor;
preferably, the first initialization module and the compensation module comprise double gate transistors;
preferably, the pixel circuit further includes a second initialization module, a control end of the second initialization module is electrically connected to the second scan signal input end, a first end of the second initialization module is electrically connected to the reference voltage input end, a second end of the second initialization module is electrically connected to the first end of the light emitting module, and a second end of the light emitting module is electrically connected to the second power voltage input end.
8. The pixel circuit according to claim 1, wherein a control terminal of the data writing module is electrically connected to a first scan signal input terminal, a first terminal of the data writing module is electrically connected to a data voltage input terminal, and a second terminal of the data writing module is electrically connected to the first pole of the driving transistor;
the control end of the compensation module is electrically connected with the second scanning signal input end, the first end of the compensation module is electrically connected with the second pole of the driving transistor, and the second end of the compensation module is electrically connected with the grid electrode of the driving transistor;
the first control end of the storage control module is electrically connected with the first scanning signal input end;
the pixel circuit further comprises a first initialization module, wherein a control end of the first initialization module is electrically connected with a third scanning signal input end, a first end of the first initialization module is electrically connected with a reference voltage input end, and a second end of the first initialization module is electrically connected with a second pole of the driving transistor;
the first initialization module and the compensation module are used for transmitting a signal input by a reference voltage input end to a grid electrode of the driving transistor in an initialization stage;
preferably, the pixel circuit further includes a second initialization module, and the second initialization module is configured to initialize a potential of the first end of the light emitting module in an initialization phase.
9. A driving method of a pixel circuit for driving the pixel circuit according to any one of claims 1 to 8, the driving method of the pixel circuit comprising:
in the data writing stage, controlling the second storage capacitor to be connected with the first pole of the driving transistor;
and in the light-emitting stage, controlling the second storage capacitor to be connected with the grid electrode of the driving transistor.
10. A display panel comprising the pixel circuit according to any one of claims 1 to 8.
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| CN112992055B (en) * | 2021-04-27 | 2021-07-27 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit and display panel |
| WO2022227231A1 (en) * | 2021-04-27 | 2022-11-03 | 武汉华星光电半导体显示技术有限公司 | Pixel circuit and display panel |
| CN113192461A (en) * | 2021-05-18 | 2021-07-30 | 云谷（固安）科技有限公司 | Pixel driving circuit, driving method of pixel driving circuit and display panel |
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| CN113870780A (en) * | 2021-09-18 | 2021-12-31 | 合肥维信诺科技有限公司 | Pixel circuit and display panel |
| CN113870781A (en) * | 2021-09-18 | 2021-12-31 | 云谷（固安）科技有限公司 | Pixel circuit and display panel |
| CN114023237A (en) * | 2021-11-12 | 2022-02-08 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN114023237B (en) * | 2021-11-12 | 2024-01-16 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN114023263A (en) * | 2021-11-25 | 2022-02-08 | 云谷（固安）科技有限公司 | Pixel circuit, driving method of pixel circuit and display panel |
| CN114241977A (en) * | 2021-12-17 | 2022-03-25 | 昆山国显光电有限公司 | Pixel circuit, driving method thereof and display panel |
| CN115050334A (en) * | 2022-06-22 | 2022-09-13 | 厦门天马微电子有限公司 | Light-emitting panel, display device and backlight module |
| WO2024036751A1 (en) * | 2022-08-15 | 2024-02-22 | 昆山国显光电有限公司 | Pixel drive circuit and display panel |
| CN117012152A (en) * | 2023-08-31 | 2023-11-07 | 惠科股份有限公司 | Pixel driving circuit and display device |
| CN117012152B (en) * | 2023-08-31 | 2024-05-17 | 惠科股份有限公司 | Pixel driving circuit and display device |
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