CN111491385B - Method and device for reducing interference of synchronous signal block - Google Patents
Method and device for reducing interference of synchronous signal block Download PDFInfo
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- CN111491385B CN111491385B CN201910082622.6A CN201910082622A CN111491385B CN 111491385 B CN111491385 B CN 111491385B CN 201910082622 A CN201910082622 A CN 201910082622A CN 111491385 B CN111491385 B CN 111491385B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W72/00—Local resource management
- H04W72/50—Allocation or scheduling criteria for wireless resources
- H04W72/54—Allocation or scheduling criteria for wireless resources based on quality criteria
- H04W72/541—Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/003—Arrangements for allocating sub-channels of the transmission path
- H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
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- Mobile Radio Communication Systems (AREA)
Abstract
The invention provides a method and a device for reducing interference of a synchronous signal block, belonging to the technical field of wireless communication. A method of reducing synchronization signal block interference, comprising: generating configuration information of a reference signal; and sending configuration information of the reference signals to the terminal, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all the base stations is the same and/or indicates that the density of the reference signals is reduced. By the technical scheme of the invention, the interference of the reference signal of the PBCH can be reduced.
Description
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to a method and an apparatus for reducing interference of a synchronization signal block.
Background
Configurations of SSBs (synchronization signal blocks) are defined in section 7.4.3 of 3GPP protocol TS 38.211, including position configurations of PSS (primary synchronization signal)/SSS (secondary synchronization signal)/DMRS (demodulation reference signal) in SSBs, as shown in the following table, in which For cell identification.
Table 1: resources within an SS (synchronization signal)/PBCH (physical broadcast channel) block for PSS, SSS, PBCH, and DMRS for PBCH
The specific configuration of SSB is shown in fig. 1, where 1 represents idle resources, 2 represents primary synchronization signals, 3 represents secondary synchronization signals, 4 represents physical broadcast channels, 5 represents demodulation reference signals, when the configuration shown in fig. 1 is adopted, the demodulation reference signals of the local area are sent, and when the demodulation reference signals of the local area are sent, PBCH data signals of neighboring areas are also sent, so that the DMRS interference is quite large, DMRS demodulation failure of the local area is easily caused, SSB demodulation failure is likely, and the terminal cannot access to the network.
If the DMRS power is increased, the power of the PBCH RE (resource element) of the same time slot is reduced, resulting in an increase in the DMRS reference signal demodulation success rate, but a decrease in the PBCH demodulation performance.
Disclosure of Invention
The invention aims to provide a method and a device for reducing the interference of a synchronous signal block, which can reduce the interference of a reference signal of a PBCH.
In order to solve the technical problems, the embodiment of the invention provides the following technical scheme:
the embodiment of the invention provides a method for reducing the interference of a synchronous signal block, which comprises the following steps:
generating configuration information of a reference signal;
and sending configuration information of the reference signals to the terminal, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all the base stations is the same and/or indicates that the density of the reference signals is reduced.
Further, when the configuration information of the reference signals indicates that the time-frequency domain configurations of the reference signals of all the base stations are identical, the method further comprises:
the reference signal is scrambled with a cell identity before the reference signal is transmitted.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention provides a method for reducing interference of a synchronous signal block, which is applied to a terminal and comprises the following steps:
receiving configuration information of reference signals, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all base stations is the same and/or indicates that the density of the reference signals is reduced;
and receiving the reference signal according to the configuration information of the reference signal.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention provides a device for reducing the interference of a synchronous signal block, which is applied to network side equipment and comprises a processor and a transceiver,
the processor is used for generating configuration information of the reference signal;
the transceiver is configured to send configuration information of reference signals to the terminal, where the configuration information of the reference signals indicates that the time-frequency domain configurations of the reference signals of all base stations are the same and/or indicates that the density of the reference signals is reduced.
Further, the processor is further configured to scramble the reference signal with the cell identity prior to transmitting the reference signal.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention provides a device for reducing the interference of a synchronous signal block, which is applied to a terminal and comprises a processor and a transceiver,
the transceiver is configured to receive configuration information of reference signals, where the configuration information of the reference signals indicates that time-frequency domain configurations of the reference signals of all base stations are the same and/or indicates to reduce density of the reference signals; and receiving the reference signal according to the configuration information of the reference signal.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention also provides a communication device, which comprises: a memory, a processor and a computer program stored on the memory and executable on the processor, which when executed by the processor performs the steps in a method of reducing synchronization signal block interference as described above.
Embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a method of reducing synchronization signal block interference as described above.
The embodiment of the invention has the following beneficial effects:
in the scheme, the same time-frequency domain resources are configured for the reference signals of all the base stations, or the density of the reference signals is reduced, so that the interference of other signals on the reference signals can be reduced, the demodulation performance of the reference signals is improved, and the SSB demodulation performance is further improved.
Drawings
FIG. 1 is a schematic diagram showing a specific configuration of SSB;
FIG. 2 is a flowchart illustrating a method for reducing synchronization signal block interference according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for reducing interference of a synchronization signal block according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a configuration position of a DMRS according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating an apparatus for reducing synchronization signal block interference according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an apparatus for reducing synchronization signal block interference according to another embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention more apparent, the following detailed description will be given with reference to the accompanying drawings and the specific embodiments.
The names and abbreviations of the terms involved in the present invention change correspondingly, and the technical scheme of the present invention is still applicable when the abbreviations change.
The embodiment of the invention provides a method and a device for reducing the interference of a synchronous signal block, which can reduce the interference of a reference signal of a PBCH.
An embodiment of the present invention provides a method for reducing interference of a synchronization signal block, as shown in fig. 2, including:
step 101: generating configuration information of a reference signal;
step 102: and sending configuration information of the reference signals to the terminal, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all the base stations is the same and/or indicates that the density of the reference signals is reduced.
In this embodiment, the same time-frequency domain resource is configured for the reference signals of all the base stations, or the density of the reference signals is reduced, so that the interference of other signals on the reference signals can be reduced, the demodulation performance of the reference signals is improved, and the SSB demodulation performance is further improved.
The technical scheme of the embodiment is applied to network side equipment.
Further, when the configuration information of the reference signals indicates that the time-frequency domain configurations of the reference signals of all the base stations are identical, the method further comprises:
the reference signal is scrambled with a cell identity before the reference signal is transmitted.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention also provides a method for reducing the interference of the synchronous signal blocks, as shown in fig. 3, comprising the following steps:
step 201: receiving configuration information of reference signals, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all base stations is the same and/or indicates that the density of the reference signals is reduced;
step 202: and receiving the reference signal according to the configuration information of the reference signal.
In this embodiment, the same time-frequency domain resource is configured for the reference signals of all the base stations, or the density of the reference signals is reduced, so that the interference of other signals on the reference signals can be reduced, the demodulation performance of the reference signals is improved, and the SSB demodulation performance is further improved.
The technical scheme of the embodiment is applied to the terminal.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The following description of the present invention is further provided with reference to the accompanying drawings and specific embodiments, where the purpose of the following embodiments is to reduce the interference of the DMRS of the reference signal of the PBCH.
First embodiment:
in this embodiment, the time domain and frequency domain configurations of DMRS of all cells are the same.
The reference signal DMRS adopts CELL-ID scrambling to meet orthogonality, so that SSB (single-layer interference) reception of each cell can avoid interference through the orthogonality of the reference signal on the premise of ensuring the orthogonality of the reference signal.
In this embodiment, under the condition of DMRS power boosting, the boosting of SINR (Signal to Interference plus Noise Ratio ) is not caused, because the DMRS of the neighboring cell also boosts power.
In this embodiment, the modified protocol parameters are shown in table 1:
TABLE 1
Where v= 0/1/2/3/4, which is the same for each cell.
In this embodiment, the orthogonality of DMRS design is adopted, SSB DMRS interference per cell is reduced,
specific embodiment II:
in this embodiment, the positions of the reference signal arrangements are staggered.
As shown in fig. 5, the reference PSS adopts the mode three interference, wherein 6, 7 and 8 are DMRS positions of the corresponding cells in the three sector directions, respectively, so that the DMRS interference in the same direction can be reduced.
The embodiment has the advantage that the effect of improving the power of the DMRS reference signal can be reflected. In this embodiment, the DMRS density is reduced, because if the cell adopts the DMRS of the location 6, the DMRS of the location 7 and the location 8 need to be free, i.e., the DMRS density increase can improve the demodulation performance of the PBCH, but can cause interference increase in the networking environment. Considering the reliability of PBCH, the DMRS density is reduced, the interference is reduced, and the performance is not reduced.
In this embodiment, the modified protocol parameters are shown in table 2:
TABLE 2
Wherein, the liquid crystal display device comprises a liquid crystal display device, for cell identification, n is a natural number, and v is the frequency domain position of the reference signal.
In this embodiment, a mode of reducing the DMRS density is adopted to reduce the interference of the DMRS, improve the demodulation performance of the DMRS, and improve the SSB demodulation performance
The embodiment of the invention also provides a device for reducing the interference of the synchronous signal block, as shown in fig. 5, comprising a processor 31 and a transceiver 32,
the processor 31 is configured to generate configuration information of a reference signal;
the transceiver 32 is configured to send configuration information of reference signals to the terminal, where the configuration information of reference signals indicates that the time-frequency domain configurations of reference signals of all base stations are the same and/or indicates that the density of reference signals is reduced.
In this embodiment, the same time-frequency domain resource is configured for the reference signals of all the base stations, or the density of the reference signals is reduced, so that the interference of other signals on the reference signals can be reduced, the demodulation performance of the reference signals is improved, and the SSB demodulation performance is further improved.
The technical scheme of the embodiment is applied to network side equipment.
Further, the processor 31 is further configured to scramble the reference signal with the cell identity before transmitting the reference signal.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention also provides a device for reducing the interference of the synchronous signal block, as shown in fig. 6, comprising a processor 41 and a transceiver 42,
the transceiver 42 is configured to receive configuration information of reference signals, where the configuration information of reference signals indicates that the time-frequency domain configurations of reference signals of all base stations are the same and/or indicates that the density of reference signals is reduced; and receiving the reference signal according to the configuration information of the reference signal.
In this embodiment, the same time-frequency domain resource is configured for the reference signals of all the base stations, or the density of the reference signals is reduced, so that the interference of other signals on the reference signals can be reduced, the demodulation performance of the reference signals is improved, and the SSB demodulation performance is further improved.
The technical scheme of the embodiment is applied to the terminal.
Further, the configuration information of the reference signal indicates that the frequency domain granularity of the reference signal is greater than a threshold.
Further, the threshold is 12.
Further, the reference signal is a DMRS.
The embodiment of the invention also provides a communication device, which comprises: a memory, a processor and a computer program stored on the memory and executable on the processor, which when executed by the processor performs the steps in a method of reducing synchronization signal block interference as described above.
The communication device may be a network side device or a terminal.
Embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of a method of reducing synchronization signal block interference as described above.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (Application Specific Integrated Circuits, ASIC), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP devices, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, user equipment (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing user equipment to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing user equipment, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing user equipment to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing user equipment to cause a series of operational steps to be performed on the computer or other programmable user equipment to produce a computer implemented process such that the instructions which execute on the computer or other programmable user equipment provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or user device that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or user device. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or user device comprising the element.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the principles of the present invention, and such modifications and changes are intended to be within the scope of the present invention.
Claims (16)
1. A method for reducing interference of a synchronization signal block, which is applied to a network side device, comprising:
generating configuration information of a reference signal;
transmitting configuration information of reference signals to a terminal, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all base stations is the same and/or indicates to reduce the density of the reference signals;
the configuration information of the reference signal indicates that a frequency domain granularity of the reference signal is greater than a threshold.
2. The method for reducing synchronization signal block interference according to claim 1, wherein when the configuration information of the reference signal indicates that the time-frequency domain configurations of the reference signals of all base stations are identical, the method further comprises:
the reference signal is scrambled with a cell identity before the reference signal is transmitted.
3. The method of reducing synchronization signal block interference according to claim 1, wherein the threshold is 12.
4. The method of reducing synchronization signal block interference according to claim 1, wherein the reference signal is a DMRS.
5. A method for reducing synchronization signal block interference, which is applied to a terminal, comprising:
receiving configuration information of reference signals, wherein the configuration information of the reference signals indicates that the time-frequency domain configuration of the reference signals of all base stations is the same and/or indicates that the density of the reference signals is reduced;
receiving a reference signal according to the configuration information of the reference signal;
the configuration information of the reference signal indicates that a frequency domain granularity of the reference signal is greater than a threshold.
6. The method of reducing synchronization signal block interference according to claim 5, wherein the threshold is 12.
7. The method of reducing synchronization signal block interference according to claim 5, wherein the reference signal is a DMRS.
8. An apparatus for reducing interference of synchronous signal blocks is characterized by being applied to network side equipment and comprising a processor and a transceiver,
the processor is used for generating configuration information of the reference signal;
the transceiver is configured to send configuration information of reference signals to the terminal, where the configuration information of the reference signals indicates that the time-frequency domain configurations of the reference signals of all the base stations are the same and/or indicates to reduce the density of the reference signals;
the configuration information of the reference signal indicates that a frequency domain granularity of the reference signal is greater than a threshold.
9. The apparatus for reducing synchronization signal block interference of claim 8 wherein the processor is further configured to scramble the reference signal with a cell identity prior to transmitting the reference signal.
10. The apparatus for reducing synchronization signal block interference according to claim 8, wherein the threshold is 12.
11. The apparatus for reducing synchronization signal block interference of claim 8 wherein the reference signal is a DMRS.
12. An apparatus for reducing interference of a synchronous signal block is characterized by being applied to a terminal and comprising a processor and a transceiver,
the transceiver is configured to receive configuration information of reference signals, where the configuration information of the reference signals indicates that time-frequency domain configurations of the reference signals of all base stations are the same and/or indicates to reduce density of the reference signals; receiving a reference signal according to the configuration information of the reference signal;
the configuration information of the reference signal indicates that a frequency domain granularity of the reference signal is greater than a threshold.
13. The apparatus for reducing synchronization signal block interference according to claim 12, wherein the threshold is 12.
14. The apparatus for reducing synchronization signal block interference of claim 12 wherein the reference signal is a DMRS.
15. A communication device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, which when executed by the processor realizes the steps in the method of reducing synchronization signal block interference as claimed in any one of claims 1 to 4 or the steps in the method of reducing synchronization signal block interference as claimed in any one of claims 5 to 7.
16. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the method of reducing synchronization signal block interference of any of claims 1 to 4 or the steps of the method of reducing synchronization signal block interference of any of claims 5 to 7.
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| MX2019014881A (en) * | 2017-06-15 | 2020-02-13 | Sharp Kk | Method and apparatus for generating and using reference signal for broadcast channel for radio system. |
| CN109150462B (en) * | 2017-06-16 | 2020-09-01 | 电信科学技术研究院 | PBCH (physical broadcast channel) dedicated demodulation reference signal transmission method and device |
| CN109451787B (en) * | 2017-07-11 | 2021-02-09 | 北京小米移动软件有限公司 | Inter-cell signal interference control method and device, user equipment and base station |
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