CN111491162B

CN111491162B - Detection driving circuit, driving method and detection device

Info

Publication number: CN111491162B
Application number: CN202010424896.1A
Authority: CN
Inventors: 唐大伟; 吴琼; 黄继景; 欧歌; 杨志明; 王志良
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-05-19
Filing date: 2020-05-19
Publication date: 2021-08-13
Anticipated expiration: 2040-05-19
Also published as: CN111491162A

Abstract

The invention discloses a detection driving circuit, a driving method and a detection device.A clock generating circuit, a state identification circuit and at least two driving generating circuits are arranged, wherein the clock generating circuit can generate a control clock signal according to a signal of a reference clock end; the state identification circuit can output state control signals corresponding to the state input ends one by one through the state output ends according to signals of the reference clock end and the state input ends; the drive generation circuit may generate the drive control signal according to the control clock signal and a state control signal output from the electrically connected state output terminal, and output the drive control signal through the drive output terminal. This enables the detection drive circuit to generate a drive control signal for driving the image sensor panel to operate.

Description

Detection driving circuit, driving method and detection device

Technical Field

The present invention relates to the field of detection technologies, and in particular, to a detection driving circuit, a driving method, and a detection device.

Background

With the rapid development of technology, image sensor panels are widely used. When the image sensor panel is manufactured, it needs to be detected and tested to determine the yield.

Disclosure of Invention

The embodiment of the invention provides a detection driving circuit, a driving method and a detection device, which are used for detecting and driving an image sensor panel.

An embodiment of the present invention provides a detection driving circuit, including: a clock generation circuit, a state identification circuit and at least two drive generation circuits;

the clock generation circuit is electrically connected with a reference clock terminal and is configured to generate a control clock signal according to a signal of the reference clock terminal;

the state identification circuit is respectively electrically connected with the reference clock end, at least two state input ends and at least two state output ends and is configured to output state control signals corresponding to the state input ends one by one through the state output ends according to signals of the reference clock end and the state input ends; wherein one of the status input terminals is configured to be electrically connected to an image sensor panel, one of the status output terminals is electrically connected to one of the driving generation circuits, and one of the status output terminals corresponds to one of the status input terminals;

the driving generation circuit is also electrically connected with the clock generation circuit, and is configured to generate a driving control signal according to the control clock signal and a state control signal output by the electrically connected state output end, and output the driving control signal through a driving output end; wherein the driving output terminal is configured to electrically connect the corresponding image sensor panel.

Optionally, in an embodiment of the present invention, the image sensor panel includes: an active pixel image sensor panel;

the drive generation circuit includes: a first drive generation circuit corresponding to the active pixel image sensor panel;

the drive output of the first drive generation circuit is configured to electrically connect the corresponding active pixel image sensor panel; and the first drive generation circuit is configured to generate a drive control signal corresponding to the active pixel image sensor panel according to the control clock signal and a state control signal corresponding to the active pixel image sensor panel.

Optionally, in an embodiment of the present invention, the driving output terminal of the first driving generation circuit includes: the driving device comprises a first driving end, a second driving end and a third driving end;

the first drive generation circuit includes: a first inverter, first to seventh selectors, first to fourth comparators, first to eighth and first to third D flip-flops;

the control end of the first selector is electrically connected with a first active control signal end, the first input end of the first selector is electrically connected with a grounding end, the second input end of the first selector is electrically connected with the grounding end, and the output end of the first selector is respectively electrically connected with the first input end of the first AND gate and the first input end of the second AND gate;

a first input end of the first comparator is electrically connected with a second active control signal end, a second input end of the first comparator is electrically connected with the grounding end, and an output end of the first comparator is electrically connected with a second input end of the first AND gate;

the first input end of the second comparator is electrically connected with a third active control signal end, the second input end of the third comparator is electrically connected with the grounding end, and the output end of the third comparator is electrically connected with the second input end of the second AND gate;

a first input end of the third comparator is electrically connected with a fourth active control signal end, a second input end of the third comparator is electrically connected with the grounding end, and an output end of the third comparator is respectively electrically connected with a second input end of the fifth and gate and a second input end of the sixth and gate;

the output end of the first AND gate is electrically connected with the first input end of the fourth AND gate, the first input end of the fifth AND gate and the first input end of the seventh AND gate respectively;

the output end of the second AND gate is electrically connected with the first input end of the third AND gate, the first input end of the sixth AND gate and the first input end of the eighth AND gate respectively;

a first input end of the fourth comparator is electrically connected with the fourth active control signal end, a second input end of the fourth comparator is electrically connected with the ground end, and an output end of the fourth comparator is electrically connected with a second input end of the seventh and gate and a second input end of the eighth and gate respectively;

the second input end of the third and gate is electrically connected with the fourth active control signal end, and the output end of the third and gate is electrically connected with the second input end of the second selector;

a second input end of the fourth and gate is electrically connected with the fourth active control signal end, and an output end of the fourth and gate is respectively electrically connected with a control end of the second selector and a preset end of the first D flip-flop;

the output end of the fifth and gate is electrically connected with the control end of the third selector and the preset end of the second D flip-flop respectively;

the output end of the sixth AND gate is electrically connected with the second input end of the third selector;

the output end of the seventh and gate is electrically connected with the control end of the fourth selector and the preset end of the third D flip-flop respectively;

the output end of the eighth and gate is electrically connected with the second input end of the fourth selector;

a first input end of the second selector is electrically connected with the ground end, and an output end of the second selector is electrically connected with a second input end of the fifth selector;

a first input end of the third selector is electrically connected with the ground end, and an output end of the third selector is electrically connected with a second input end of the sixth selector;

a first input end of the fourth selector is electrically connected with the ground end, and an output end of the fourth selector is electrically connected with a second input end of the seventh selector;

a first input end of the fifth selector is electrically connected with a first reference signal end, a control end of the fifth selector is electrically connected with the first active control signal end, and an output end of the fifth selector is electrically connected with a reset end of the first D trigger;

a first input end of the sixth selector is electrically connected with the first reference signal end, a control end of the sixth selector is electrically connected with the first active control signal end, and an output end of the sixth selector is electrically connected with a reset end of the second D flip-flop;

a first input end of the seventh selector is electrically connected with the first reference signal end, a control end of the seventh selector is electrically connected with the first active control signal end, and an output end of the seventh selector is electrically connected with a reset end of the third D flip-flop;

the clock end of the first D flip-flop is configured to receive the control clock signal, the input end of the first D flip-flop is electrically connected with the output end of the first inverter, and the output end of the first D flip-flop is electrically connected with the first active driving end;

the clock end of the second D flip-flop is configured to receive the control clock signal, the input end of the second D flip-flop is electrically connected with the output end of the first inverter, and the output end of the second D flip-flop is electrically connected with the second active driving end;

the clock end of the third D flip-flop is configured to receive the control clock signal, the input end of the third D flip-flop is electrically connected with the output end of the first inverter, and the output end of the third D flip-flop is electrically connected with the third active driving end;

an input terminal of the first inverter is electrically connected to a status output terminal corresponding to the active pixel image sensor panel.

Optionally, in an embodiment of the present invention, the image sensor panel includes: a passive pixel image sensor panel;

the drive generation circuit includes: a second drive generation circuit corresponding to the passive pixel image sensor panel;

the drive output of the second drive generation circuit is configured to electrically connect the corresponding passive pixel image sensor panel; and the second drive generation circuit is configured to generate a drive control signal corresponding to the passive pixel image sensor panel from the control clock signal and a state control signal corresponding to the passive pixel image sensor panel.

Optionally, in an embodiment of the present invention, the driving output terminal of the second driving generation circuit includes: a first passive driving end and a second passive driving end;

the second drive generation circuit includes: the comparator comprises a fifth comparator, a tenth comparator, a ninth AND gate, a twelfth AND gate, an eighth selector, an eleventh selector, a fourth D trigger, a fifth D trigger and a memory;

a first input end of the fifth comparator is electrically connected with the first passive control signal end, a second input end of the fifth comparator is electrically connected with a ground end, and an output end of the fifth comparator is electrically connected with a first input end of the ninth and-gate;

a first input end of the sixth comparator is electrically connected with a fourth passive control signal end, a second input end of the sixth comparator is electrically connected with the ground end, and an output end of the fifth comparator is electrically connected with a second input end of the ninth and-gate and a second input end of the eleventh and-gate respectively;

the output end of the ninth AND gate is electrically connected with the first input end of the tenth AND gate;

a first input end of the seventh comparator is electrically connected with a fifth passive control signal end, a second input end of the seventh comparator is electrically connected with the ground end, and an output end of the seventh comparator is electrically connected with a second input end of the tenth and gate;

a first input end of the eighth comparator is electrically connected with the first passive control signal end, a second input end of the eighth comparator is electrically connected with the ground end, and an output end of the eighth comparator is electrically connected with a first input end of the eleventh and gate;

a first input end of the ninth comparator is electrically connected with the first passive control signal end, a second input end of the ninth comparator is electrically connected with the ground end, and an output end of the ninth comparator is electrically connected with a first input end of the twelfth AND gate;

a first input end of the tenth comparator is electrically connected with a third passive control signal end, a second input end of the tenth comparator is electrically connected with the ground end, and an output end of the tenth comparator is electrically connected with a second input end of the twelfth AND gate;

the output end of the tenth and gate is electrically connected with the second input end of the eighth selector;

the output end of the eleventh and gate is electrically connected with the control end of the eighth selector and the preset end of the fifth D flip-flop respectively;

the output end of the twelfth AND gate is electrically connected with the second input end of the ninth selector;

a first input end of the eighth selector is electrically connected with the ground end, and an output end of the eighth selector is electrically connected with a second input end of the tenth selector;

a first input end of the ninth selector is electrically connected with the ground end, a control end of the ninth selector is electrically connected with the first passive control signal end, and an output end of the ninth selector is electrically connected with a second input end of the eleventh selector;

a first input end of the tenth selector is electrically connected with a second reference signal end, a control end of the tenth selector is electrically connected with the first passive control signal end, and an output end of the tenth selector is electrically connected with a reset end of the fifth D flip-flop;

a first input end of the eleventh selector is electrically connected with the second reference signal end, a control end of the eleventh selector is electrically connected with the first passive control signal end, and an output end of the eleventh selector is electrically connected with a reset end of the fourth D flip-flop;

a clock terminal of the fourth D flip-flop is configured to receive the control clock signal, an input terminal of the fourth D flip-flop is electrically connected to a status output terminal corresponding to the passive pixel image sensor panel, a preset terminal of the fourth D flip-flop is electrically connected to an output terminal of the memory, and an output terminal of the fourth D flip-flop is electrically connected to the first passive driving terminal;

a clock terminal of the fifth D flip-flop is configured to receive the control clock signal, an input terminal of the fourth D flip-flop is electrically connected with a status output terminal corresponding to the passive pixel image sensor panel, and an output terminal of the fourth D flip-flop is electrically connected with the second passive driving terminal;

the input end of the memory is electrically connected with the first passive driving end.

Optionally, in an embodiment of the present invention, the state identification circuit includes: sixth to ninth D flip-flops, an eleventh comparator, and a twelfth comparator;

a clock end of the sixth D flip-flop is electrically connected to the reference clock end, an input end of the sixth D flip-flop is electrically connected to a state input end corresponding to the active pixel image sensor panel, and an output end of the sixth D flip-flop is electrically connected to a first input end of the eleventh comparator;

a clock end of the seventh D flip-flop is electrically connected to the reference clock end, an input end of the seventh D flip-flop is electrically connected to a state input end corresponding to the passive pixel image sensor panel, and an output end of the seventh D flip-flop is electrically connected to a first input end of the twelfth comparator;

a second input end of the eleventh comparator is electrically connected with a ground end, and an output end of the eleventh comparator is electrically connected with an input end of the eighth D flip-flop;

a second input end of the twelfth comparator is electrically connected with the ground end, and an output end of the twelfth comparator is electrically connected with an input end of the ninth D flip-flop;

the clock end of the eighth D flip-flop is configured to receive the control clock signal, and the output end of the eighth D flip-flop is electrically connected with the state output end corresponding to the state input end electrically connected with the sixth D flip-flop;

the clock end of the ninth D flip-flop is configured to receive the control clock signal, and the output end of the ninth D flip-flop is electrically connected with the state output end corresponding to the state input end electrically connected with the seventh D flip-flop.

An embodiment of the present invention provides a driving method of the detection driving circuit, where the driving method includes:

the clock generating circuit generates a control clock signal according to the signal of the reference clock end;

the state identification circuit outputs state control signals corresponding to the state input ends one by one through the state output ends according to the signals of the reference clock end and the state input ends;

and the drive generation circuit generates a drive control signal according to the control clock signal and a state control signal output by the electrically connected state output end, and outputs the drive control signal through the drive output end.

Optionally, in an embodiment of the present invention, the image sensor panel includes: active pixel image sensor panels; the driving generation circuit generates a driving control signal according to the control clock signal and a state control signal output by the state output end and is electrically connected with the control clock signal, and outputs the driving control signal through the driving output end, and the driving generation circuit specifically comprises: the first drive generation circuit generates a drive control signal corresponding to the active pixel image sensor panel according to the control clock signal and a state control signal corresponding to the active pixel image sensor panel;

the image sensor panel includes: passive pixel image sensor panels; the driving generation circuit generates a driving control signal according to the control clock signal and a state control signal output by the state output end and is electrically connected with the control clock signal, and outputs the driving control signal through the driving output end, and the driving generation circuit specifically comprises: the second drive generation circuit generates a drive control signal corresponding to the passive pixel image sensor panel based on the control clock signal and a state control signal corresponding to the passive pixel image sensor panel.

Optionally, in an embodiment of the present invention, the state identification circuit outputs, according to the control clock signal and the signal of each state input terminal, a state control signal corresponding to each state input terminal one to one through each state output terminal, specifically including:

the state identification circuit respectively acquires a first state feedback signal corresponding to the active pixel image sensor panel and a second state feedback signal corresponding to the passive pixel image sensor panel through a state input end;

when the first state feedback signal is at a first level, a state control signal output by a state output end corresponding to the active pixel image sensor panel is at the first level;

when the first state feedback signal is at a second level, the state control signal output by the state output end corresponding to the active pixel image sensor panel is at the second level;

when the second state feedback signal is at a first level, the state control signal output by the state output end corresponding to the passive pixel image sensor panel is at the first level;

when the second state feedback signal is at a second level, the state control signal output by the state output end corresponding to the passive pixel image sensor panel is at the second level;

the first driving generation circuit generates a driving control signal corresponding to the active pixel image sensor panel according to the control clock signal and a state control signal corresponding to the active pixel image sensor panel, and specifically includes: the first drive generation circuit generates a drive control signal corresponding to the active pixel image sensor panel according to the control clock signal and a state control signal which corresponds to the active pixel image sensor panel and is at a first level;

the second driving generation circuit generates a driving control signal corresponding to the passive pixel image sensor panel according to the control clock signal and a state control signal corresponding to the passive pixel image sensor panel, and specifically includes: the second drive generation circuit generates a drive control signal corresponding to the passive pixel image sensor panel based on the control clock signal and a state control signal corresponding to the passive pixel image sensor panel and being at a first level.

The embodiment of the invention also provides a detection device which comprises the detection driving circuit.

The invention has the following beneficial effects:

according to the detection driving circuit, the driving method and the detection device provided by the embodiment of the invention, the clock generation circuit, the state identification circuit and the at least two driving generation circuits are arranged, wherein the clock generation circuit can generate a control clock signal according to a signal of a reference clock end; the state identification circuit can output state control signals corresponding to the state input ends one by one through the state output ends according to signals of the reference clock end and the state input ends; the drive generation circuit may generate the drive control signal according to the control clock signal and a state control signal output from the electrically connected state output terminal, and output the drive control signal through the drive output terminal. This enables the detection drive circuit to generate a drive control signal for driving the image sensor panel to operate. And, since the driving output terminal is configured to electrically connect the corresponding image sensor panel, the image sensor panel can be driven to operate to perform performance detection on the image sensor panel after the driving control signal is input to the image sensor panel.

Drawings

FIG. 1 is a schematic diagram of a detection driving circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a state identification circuit according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a first driving generation circuit according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a second driving generation circuit according to an embodiment of the present invention;

FIG. 5 is a flow chart of a driving method in an embodiment of the present invention;

FIG. 6 is a timing diagram of the status recognition circuit according to an embodiment of the present invention;

FIG. 7 is a timing diagram of the first driving circuit according to the embodiment of the present invention;

FIG. 8 is a timing diagram of the second driving circuit according to the embodiment of the present invention;

FIG. 9 is a timing diagram of the signals output by the detection driving circuit according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1, the detection driving circuit provided in an embodiment of the present invention may include: a clock generation circuit 110, a state identification circuit 120, and at least two drive generation circuits;

the clock generation circuit 110 is electrically connected to the reference clock terminal CLK0 and configured to generate a control clock signal CLKC according to a signal of the reference clock terminal CLK 0;

the state identification circuit 120 is electrically connected to the reference clock terminal CLK0, the at least two state input terminals, and the at least two state output terminals, respectively, and configured to output state control signals corresponding to the state input terminals one by one through the state output terminals according to signals of the reference clock terminal CLK0 and the state input terminals; one state input end is configured to be electrically connected with one image sensor panel, one state output end is electrically connected with one drive generation circuit, and one state output end corresponds to one state input end;

the driving generation circuit is further electrically connected to the clock generation circuit 110, configured to generate a driving control signal according to the control clock signal CLKC and a state control signal output from an electrically connected state output terminal, and output the driving control signal through the driving output terminal; wherein the driving output terminal is configured to electrically connect the corresponding image sensor panel.

In the detection driving circuit provided in the embodiment of the present invention, the clock generating circuit 110 may generate the control clock signal CLKC according to the signal of the reference clock terminal CLK 0; the state identification circuit 120 may output a state control signal corresponding to each state input terminal one by one through each state output terminal according to the reference clock terminal CLK0 and the signals of each state input terminal; the drive generation circuit may generate a drive control signal according to the control clock signal CLKC and a state control signal output from an electrically connected state output terminal, and output the drive control signal through the drive output terminal. This enables the detection drive circuit to generate a drive control signal for driving the image sensor panel to operate. And, since the driving output terminal is configured to electrically connect the corresponding image sensor panel, the image sensor panel can be driven to operate to perform performance detection on the image sensor panel after the driving control signal is input to the image sensor panel.

In specific implementation, in the embodiment of the present invention, the number of the driving generation circuits may be 2, or the number of the driving generation circuits may be 3, 4, 5, 6, or the like. In practical applications, the number of the driving generation circuits may be set according to application requirements, and is not limited herein.

Generally, an Active pixel image sensor (APS) panel and a Passive pixel image sensor (PPS) panel are widely used. In particular, in an embodiment of the present invention, an image sensor panel may include: at least one of an active pixel image sensor panel 141 and a passive pixel image sensor panel 142. Illustratively, the image sensor panel may include an active pixel image sensor panel 141. Alternatively, the image sensor panel may include a passive pixel image sensor panel 142. Alternatively, as shown in fig. 1, the image sensor panel may include: an active pixel image sensor panel 141 and a passive pixel image sensor panel 142. The following description will take an example in which the image sensor panel includes an active pixel image sensor panel 141 and a passive pixel image sensor panel 142.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1, the driving generation circuit may include: the first drive generation circuit 131 corresponding to the active pixel image sensor panel 141. Wherein the driving output of the first driving generation circuit 131 is configured to electrically connect the corresponding active pixel image sensor panel 141; and the first drive generation circuit 131 is configured to generate a drive control signal corresponding to the active pixel image sensor panel 141 according to the control clock signal CLKC and a state control signal corresponding to the active pixel image sensor panel 141.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1 to 3, the driving output terminal of the first driving generation circuit 131 may include: a first active drive end AOUT1, a second active drive end AOUT2 and a third active drive end AOUT 3. For example, the first active drive end AOUT1, the second active drive end AOUT2 and the third active drive end AOUT3 may be drive ends that output different signals. For example, the first active driving end AOUT1 and the second active driving end AOUT2 may output a clock signal that drives the active pixel image sensor panel 141, and the periods of the clock signals output by the first active driving end AOUT1 and the second active driving end AOUT2 are the same and the duty ratios are the same. The third active driving terminal AOUT3 may output a frame trigger signal so that the active pixel image sensor panel 141 may be driven for a frame scanning process. Of course, in practical application, the design may be determined according to the requirements of practical application, and is not limited herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1 and fig. 2, the first driving generation circuit 131 may include: a first inverter ND, first to seventh selectors M1 to M7, first to fourth comparators D1 to D4, first to eighth and gates Y1 to Y8, and first to third D flip-flops DT1 to DT 3;

a control terminal of the first selector M1 is electrically connected to the first active control signal terminal VCA1, a first input terminal M01 of the first selector M1 is electrically connected to the ground terminal GND, a second input terminal M02 of the first selector M1 is electrically connected to the ground terminal GND, and an output terminal of the first selector M1 is electrically connected to the first input terminal Y01 of the first and gate Y1 and the first input terminal Y01 of the second and gate Y2, respectively;

the first input end D01 of the first comparator D1 is electrically connected with the second active control signal terminal VCA2, the second input end D02 of the first comparator D1 is electrically connected with the ground GND, and the output end of the first comparator D1 is electrically connected with the second input end Y02 of the first and gate Y1;

the first input end D01 of the second comparator D2 is electrically connected with the third active control signal terminal VCA3, the second input end D02 of the second comparator D2 is electrically connected with the ground GND, and the output end of the second comparator D2 is electrically connected with the second input end Y02 of the second and gate Y2;

a first input end D01 of the third comparator D3 is electrically connected with the fourth active control signal terminal VCA4, a second input end D02 of the third comparator D3 is electrically connected with the ground terminal GND, and an output end of the third comparator D3 is electrically connected with a second input end Y02 of the fifth and gate Y5 and a second input end Y02 of the sixth and gate Y6, respectively;

the output end of the first and gate Y1 is electrically connected to the first input end Y01 of the fourth and gate Y4, the first input end Y01 of the fifth and gate Y5 and the first input end Y01 of the seventh and gate Y7, respectively;

the output end of the second and gate Y2 is electrically connected to the first input end Y01 of the third and gate Y3, the first input end Y01 of the sixth and gate Y6 and the first input end Y01 of the eighth and gate Y8, respectively;

a first input end D01 of the fourth comparator D4 is electrically connected with the fourth active control signal terminal VCA4, a second input end D02 of the fourth comparator D4 is electrically connected with the ground terminal GND, and an output end of the fourth comparator D4 is electrically connected with a second input end Y02 of the seventh and gate Y7 and a second input end Y02 of the eighth and gate Y8, respectively;

a second input terminal Y02 of the third and gate Y3 is electrically connected to the fourth active control signal terminal VCA4, and an output terminal of the third and gate Y3 is electrically connected to a second input terminal M02 of the second selector M2;

a second input end Y02 of the fourth and gate Y4 is electrically connected with a fourth active control signal end VCA4, and an output end of the fourth and gate Y4 is electrically connected with a control end of the second selector M2 and a preset end CE of the first D flip-flop DT1 respectively;

the output end of the fifth and gate Y5 is electrically connected to the control end of the third selector M3 and the preset end CE of the second D flip-flop DT2, respectively;

an output terminal of the sixth and gate Y6 is electrically connected to the second input terminal M02 of the third selector M3;

the output end of the seventh and gate Y7 is electrically connected to the control end of the fourth selector M4 and the preset end CE of the third D flip-flop DT3, respectively;

an output terminal of the eighth and gate Y8 is electrically connected to the second input terminal M02 of the fourth selector M4;

the first input M01 of the second selector M2 is electrically connected to the ground GND, and the output of the second selector M2 is electrically connected to the second input M02 of the fifth selector M5;

the first input M01 of the third selector M3 is electrically connected to the ground GND, and the output of the third selector M3 is electrically connected to the second input M02 of the sixth selector M6;

the first input M01 of the fourth selector M4 is electrically connected to the ground GND, and the output of the fourth selector M4 is electrically connected to the second input M02 of the seventh selector M7;

a first input end M01 of the fifth selector M5 is electrically connected with a first reference signal terminal VREF1, a control end of the fifth selector M5 is electrically connected with a first active control signal terminal VCA1, and an output end of the fifth selector M5 is electrically connected with a reset terminal SET of the first D flip-flop DT 1;

a first input end M01 of the sixth selector M6 is electrically connected with a first reference signal terminal VREF1, a control end of the sixth selector M6 is electrically connected with a first active control signal terminal VCA1, and an output end of the sixth selector M6 is electrically connected with a reset terminal SET of the second D flip-flop DT 2;

a first input end M01 of the seventh selector M7 is electrically connected with a first reference signal terminal VREF1, a control end of the seventh selector M7 is electrically connected with a first active control signal terminal VCA1, and an output end of the seventh selector M7 is electrically connected with a reset terminal SET of the third D flip-flop DT 3;

a clock terminal C of the first D flip-flop DT1 is configured to receive a control clock signal CLKC, an input terminal D of the first D flip-flop DT1 is electrically connected to an output terminal of the first inverter ND, an output terminal of the first D flip-flop DT1 is electrically connected to the first active driving terminal AOUT 1;

a clock terminal C of the second D flip-flop DT2 is configured to receive the control clock signal CLKC, an input terminal D of the second D flip-flop DT2 is electrically connected to an output terminal of the first inverter ND, and an output terminal of the second D flip-flop DT2 is electrically connected to the second active driving terminal AOUT 2;

the clock terminal C of the third D flip-flop DT3 is configured to receive the control clock signal CLKC, the input terminal D of the third D flip-flop DT3 is electrically connected to the output terminal of the first inverter ND, the output terminal of the third D flip-flop DT3 is electrically connected to the third active driving terminal AOUT 3;

an input terminal of the first inverter ND is electrically connected to the state output terminal OU-a corresponding to the active pimutexel image sensor panel 141.

The specific structure of the first driving generation circuit is only illustrated above, and in the specific implementation, the specific structure of the first driving generation circuit is not limited to the above structure provided in the embodiment of the present invention, and may be another structure known to those skilled in the art, and is not limited herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1, the driving generation circuit may include: a second drive generation circuit 132 corresponding to the passive pixel image sensor panel 142. Wherein the drive output of the second drive generation circuit 132 is configured to electrically connect the corresponding passive pixel image sensor panel 142; and the second drive generation circuit 132 is configured to generate a drive control signal corresponding to the passive pixel image sensor panel 142 according to the control clock signal CLKC and the state control signal corresponding to the passive pixel image sensor panel 142.

In practical implementation, in the embodiment of the present invention, as shown in fig. 1 to fig. 3, the driving output terminal of the second driving generation circuit 132 may include: a first passive drive terminal POUT1 and a second passive drive terminal POUT 2. For example, the first passive drive terminals POUT1 and the second passive drive terminals POUT2 may be drive terminals that output different signals. For example, the first passive driving terminal POUT1 may output a clock signal, and the second passive driving terminal POUT2 may output a driving start signal for driving the passive pixel image sensor panel 142 to perform a scanning process for one frame. Of course, in practical application, the design may be determined according to the requirements of practical application, and is not limited herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1 and fig. 3, the second driving generation circuit 132 may include: fifth to tenth comparators D5 to D10, ninth to twelfth and gates Y9 to Y12, eighth to eleventh selectors M8 to M11, fourth D flip-flop DT4, fifth D flip-flop DT5, and memory RM;

a first input end D01 of the fifth comparator D5 is electrically connected with the first passive control signal terminal VCP1, a second input end D02 of the fifth comparator D5 is electrically connected with the ground GND, and an output end of the fifth comparator D5 is electrically connected with a first input end Y01 of the ninth and gate Y9;

a first input end D01 of the sixth comparator D6 is electrically connected with the fourth passive control signal terminal VCP4, a second input end D02 of the sixth comparator D6 is electrically connected with the ground terminal GND, and an output end of the fifth comparator D5 is electrically connected with a second input end Y02 of the ninth and gate Y9 and a second input end Y01 of the eleventh and gate Y11, respectively;

the output terminal of the ninth and gate Y9 is electrically connected to the first input terminal Y01 of the tenth and gate Y10;

the first input terminal D01 of the seventh comparator D7 is electrically connected to the fifth passive control signal terminal VCP5, the second input terminal D02 of the seventh comparator D7 is electrically connected to the ground GND, and the output terminal of the seventh comparator D7 is electrically connected to the second input terminal Y02 of the tenth and gate Y10;

a first input terminal D01 of the eighth comparator D8 is electrically connected to the first passive control signal terminal VCP1, a second input terminal D02 of the eighth comparator D8 is electrically connected to the ground GND, and an output terminal of the eighth comparator D8 is electrically connected to a first input terminal Y01 of the eleventh and gate Y11;

the first input terminal D01 of the ninth comparator D9 is electrically connected to the first passive control signal terminal VCP1, the second input terminal D02 of the ninth comparator D9 is electrically connected to the ground GND, and the output terminal of the ninth comparator D9 is electrically connected to the first input terminal Y01 of the twelfth and gate Y12;

a first input terminal D01 of the tenth comparator D10 is electrically connected to the third passive control signal terminal VCP3, a second input terminal D02 of the tenth comparator D10 is electrically connected to the ground terminal GND, and an output terminal of the tenth comparator D10 is electrically connected to a second input terminal Y02 of the twelfth and gate Y12;

an output terminal of the tenth and gate Y10 is electrically connected to the second input terminal M02 of the eighth selector M8;

the output end of the eleventh and gate Y11 is electrically connected to the control end of the eighth selector M8 and the preset end CE of the fifth D flip-flop DT5, respectively;

an output terminal of the twelfth and gate Y12 is electrically connected to the second input terminal M02 of the ninth selector M9;

the first input M01 of the eighth selector M8 is electrically connected to the ground GND, and the output of the eighth selector M8 is electrically connected to the second input M02 of the tenth selector M10;

a first input end M01 of the ninth selector M9 is electrically connected to the ground GND, a control end of the ninth selector M9 is electrically connected to the first passive control signal end VCP1, and an output end of the ninth selector M9 is electrically connected to a second input end M02 of the eleventh selector M11;

a first input terminal M01 of the tenth selector M10 is electrically connected to the second reference signal terminal VREF2, a control terminal of the tenth selector M10 is electrically connected to the first passive control signal terminal VCP1, and an output terminal of the tenth selector M10 is electrically connected to the reset terminal SET of the fifth D flip-flop DT 5;

a first input terminal M01 of the eleventh selector M11 is electrically connected to the second reference signal terminal VREF2, a control terminal of the eleventh selector M11 is electrically connected to the first passive control signal terminal VCP1, and an output terminal of the eleventh selector M11 is electrically connected to the reset terminal SET of the fourth D flip-flop DT 4;

the clock terminal C of the fourth D flip-flop DT4 is configured to receive the control clock signal CLKC, the input terminal D of the fourth D flip-flop DT4 is electrically connected to the state output terminal OU-P corresponding to the passive pixel image sensor panel 142, the preset terminal CE of the fourth D flip-flop DT4 is electrically connected to the output terminal of the memory RM, and the output terminal of the fourth D flip-flop DT4 is electrically connected to the first passive driving terminal POUT 1;

the clock terminal C of the fifth D flip-flop DT5 is configured to receive the control clock signal CLKC, the input terminal D of the fourth D flip-flop DT4 is electrically connected to the state output terminal OU-P corresponding to the passive pixilated image sensor panel 142, and the output terminal of the fourth D flip-flop DT4 is electrically connected to the second passive driving terminal POUT 2;

the input end of the memory RM is electrically connected to the first passive driving end VCP 1.

The specific structure of the second driving generation circuit is only illustrated above, and in the specific implementation, the specific structure of the second driving generation circuit is not limited to the above structure provided in the embodiment of the present invention, and may be another structure known to those skilled in the art, and is not limited herein.

In specific implementation, in the embodiment of the present invention, as shown in fig. 1 to 3, the state identification circuit 120 includes: sixth to ninth D flip-flops DT6 to DT9, an eleventh comparator D11 and a twelfth comparator D12;

the clock terminal C of the sixth D flip-flop DT6 is electrically connected to the reference clock terminal CLK0, the input terminal D of the sixth D flip-flop DT6 is electrically connected to the state input terminal IN-A corresponding to the active pixel image sensor panel 141, and the output terminal of the sixth D flip-flop DT6 is electrically connected to the first input terminal D01 of the eleventh comparator D11;

the clock terminal C of the seventh D flip-flop DT7 is electrically connected to the reference clock terminal CLK0, the input terminal D of the seventh D flip-flop DT7 is electrically connected to the state input terminal IN-P corresponding to the passive pixel image sensor panel 142, and the output terminal of the seventh D flip-flop DT7 is electrically connected to the first input terminal D01 of the twelfth comparator D12;

the second input end D02 of the eleventh comparator D11 is electrically connected to the ground GND, and the output end of the eleventh comparator D11 is electrically connected to the input end D of the eighth D flip-flop DT 8;

a second input end D02 of the twelfth comparator D12 is electrically connected with the ground GND, and an output end of the twelfth comparator D12 is electrically connected with the input end D of the ninth D flip-flop DT 9;

a clock terminal C of the eighth D flip-flop DT8 is configured to receive the control clock signal CLKC, an output terminal of the eighth D flip-flop DT8 is electrically connected with a state output terminal corresponding to the state input terminal to which the sixth D flip-flop DT6 is electrically connected;

the clock terminal C of the ninth D flip-flop DT9 is configured to receive the control clock signal CLKC, and the output terminal of the ninth D flip-flop DT9 is electrically connected with the state output terminal corresponding to the state input terminal to which the seventh D flip-flop DT7 is electrically connected.

The above is merely an example of the specific structure of the state identification circuit, and in the implementation, the specific structure of the state identification circuit is not limited to the above structure provided by the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In practical implementation, in the embodiment of the present invention, for any one of the first to ninth D flip-flops DT1 to DT9, when the signal at the clock terminal of the D flip-flop is at the first level, the signal at the input terminal of the D flip-flop is provided to the output terminal of the D flip-flop. And resetting when the signal of the reset end is at the first level. It should be noted that the structure and the operation principle of any one of the first D flip-flop DT1 to the ninth D flip-flop DT9 may be substantially the same as those in the prior art, and detailed description thereof is omitted here.

In practical implementation, in the embodiment of the present invention, for any one of the first comparator D1 to the twelfth comparator D12, when the voltages of the first input terminal and the second input terminal of the comparator are the same, the output terminal of the comparator outputs the first level. When the voltages of the first input end and the second input end of the comparator are different, the output end of the comparator outputs a second level.

In specific implementation, in the embodiment of the present invention, any one of the first comparator D1 to the twelfth comparator D12 may be configured by using a Look-Up Table (LUT), or may be configured by using a logic circuit. Of course, in practical applications, the structure and the operation principle of any one of the first comparator D1 to the twelfth comparator D12 may be substantially the same as those in the prior art, and details thereof are not described herein.

In practical implementation, in the embodiment of the present invention, for any one of the first to twelfth and-gates Y1 to Y12, when both the first input terminal and the second input terminal of the and-gate are at the first level, the output terminal thereof outputs the first level. When any one of the first input terminal and the second input terminal of the AND gate is at the second level, the output terminal thereof outputs the second level. It should be noted that the structure and the operation principle of any one of the first to twelfth and-gates Y1 to Y12 may be substantially the same as those in the prior art, and detailed description thereof is omitted here.

In practical implementation, in the embodiment of the present invention, for any one of the first to eleventh selectors M1 to M11, the signal at the first terminal is output when the control terminal is at the first level, and the signal at the second terminal is output when the control terminal is at the second level. It should be noted that the structure and the operation principle of any one of the selectors M1 through M11 may be substantially the same as those in the prior art, and detailed description thereof is omitted here.

In specific implementation, in the embodiment of the present invention, the structure and the operation principle of the memory may be substantially the same as those in the prior art, and details are not described herein.

In practical implementation, in the embodiment of the present invention, the first level may be a high level, and the second level may be a low level. Alternatively, the first level may be a low level, and the second level may be a high level. Of course, in practical applications, these may be designed according to the requirements of practical applications, and are not limited herein.

In practical implementation, in the embodiment of the present invention, the signal loaded by the reference clock terminal CLK0 may be a clock pulse signal, so that the control clock signal CLKC may be generated according to the loaded clock pulse signal. For example, the reference clock terminal CLK0 may be loaded with a 50MHz clock signal, and the control clock signal CLKC may be a 200MHz clock signal, so that the 200MHz clock signal may be generated according to the 50MHz clock signal. It should be noted that the structure and the operation principle of the clock generation circuit 110 may be substantially the same as those in the prior art, and are not described herein in detail.

An embodiment of the present invention further provides a driving method of the detection driving circuit, as shown in fig. 5, the driving method may include the following steps:

s510, the clock generation circuit 110 generates a control clock signal CLKC according to a signal of a reference clock end CLK 0;

s520, the state identification circuit 120 outputs state control signals corresponding to the state input ends one by one through the state output ends according to the reference clock end CLK0 and signals of the state input ends;

s530, the driving generation circuit generates a driving control signal according to the control clock signal CLKC and the state control signal output by the electrically connected state output terminal, and outputs the driving control signal through the driving output terminal.

In the above driving method provided in the embodiment of the present invention, the clock generating circuit 110 may generate the control clock signal CLKC according to the signal of the reference clock terminal CLK 0; the state identification circuit 120 may output a state control signal corresponding to each state input terminal one by one through each state output terminal according to the reference clock terminal CLK0 and the signals of each state input terminal; the drive generation circuit may generate a drive control signal according to the control clock signal CLKC and a state control signal output from an electrically connected state output terminal, and output the drive control signal through the drive output terminal. This enables the detection drive circuit to generate a drive control signal for driving the image sensor panel to operate.

And, since the driving output terminal is configured to electrically connect the corresponding image sensor panel, the image sensor panel can be driven to operate to perform performance detection on the image sensor panel after the driving control signal is input to the image sensor panel.

In specific implementation, in an embodiment of the present invention, an image sensor panel includes: active pixel image sensor panel 141; the driving generation circuit generates a driving control signal according to the control clock signal CLKC and a state control signal output by an electrically connected state output terminal, and outputs the driving control signal through the driving output terminal, which may specifically include: the first drive generation circuit 131 generates a drive control signal corresponding to the active pixel image sensor panel 141 based on the control clock signal CLKC and a state control signal corresponding to the active pixel image sensor panel 141.

In specific implementation, in an embodiment of the present invention, an image sensor panel includes: passive pixel image sensor panel 142; the driving generation circuit generates a driving control signal according to the control clock signal CLKC and a state control signal output by an electrically connected state output terminal, and outputs the driving control signal through the driving output terminal, which may specifically include: the second drive generation circuit 132 generates a drive control signal corresponding to the passive pixel image sensor panel 142 according to the control clock signal CLKC and a state control signal corresponding to the passive pixel image sensor panel 142.

In a specific implementation, in the embodiment of the present invention, the state identification circuit 120 outputs the state control signals corresponding to the state input terminals one by one through the state output terminals according to the control clock signal CLKC and the signals of the state input terminals, which may specifically include:

the state recognition circuit 120 acquires a first state feedback signal corresponding to the active pixel image sensor panel 141 and a second state feedback signal corresponding to the passive pixel image sensor panel 142 through the state input terminals, respectively;

when the first state feedback signal is at the first level, the state control signal output by the state output end OU-a corresponding to the active pimutexel image sensor panel 141 is at the first level;

when the first state feedback signal is at the second level, the state control signal output by the state output end OU-a corresponding to the active pimutexel image sensor panel 141 is at the second level;

when the second state feedback signal is at the first level, the state control signal output by the state output end OU-P corresponding to the passive pixel image sensor panel 142 is at the first level;

the state control signal output by the state output terminal OU-P corresponding to the passive pixel image sensor panel 142 is at the second level when the second state feedback signal is at the second level.

In a specific implementation, in an embodiment of the present invention, the first driving generation circuit 131 generates the driving control signal corresponding to the active pixel image sensor panel 141 according to the control clock signal CLKC and the state control signal corresponding to the active pixel image sensor panel 141, and specifically may include: the first drive generation circuit 131 generates a drive control signal corresponding to the active pixel image sensor panel 141 based on the control clock signal CLKC and a state control signal corresponding to the active pixel image sensor panel 141 and being at a first level.

In a specific implementation, in an embodiment of the present invention, the second driving generation circuit 132 generates the driving control signal corresponding to the passive pixel image sensor panel 142 according to the control clock signal CLKC and the state control signal corresponding to the passive pixel image sensor panel 142, and specifically includes: the second drive generation circuit 132 generates a drive control signal corresponding to the passive pixel image sensor panel 142 according to the control clock signal CLKC and the state control signal corresponding to the passive pixel image sensor panel 142 and being at the first level.

The present invention will be described in detail with reference to the specific embodiments according to the structures shown in fig. 1 to 4 and the signal timing diagrams shown in fig. 6 to 9. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

Specifically, fig. 6 shows a signal timing diagram of the state identification circuit 120 in the embodiment of the present invention. Wherein CLK0 represents the signal of the reference clock terminal CLK0 (e.g., the signal of the reference clock terminal CLK0 may be a 50MHz clock pulse signal). IN-A represents the signal corresponding to the status input IN-A of the active pixel image sensor panel 141. IN-P represents the signal corresponding to the status input IN-P of the passive pixel image sensor panel 142. OU-a represents the signal corresponding to the status output OU-a of the active pimutexel image sensor panel 141. OU-P represents a signal corresponding to the status output OU-P of the passive pixel image sensor panel 142.

Fig. 7 shows a signal timing chart of the first drive generation circuit 131 in the embodiment of the present invention. Where CLKC represents a control clock signal CLKC generated by clock generation circuit 110 (e.g., the control clock signal CLKC may be a 200MHz clock pulse signal). vcal represents the signal loaded by the first active control signal terminal VCA 1. VCA2, represents the signal carried by the second active control signal terminal VCA 2. VCA3, represents the signal carried by the third active control signal terminal VCA 3. VCA4, represents the signal carried by the fourth active control signal terminal VCA 4. ap-en represents the state control signal corresponding to the state output OU-a of the active pimutexel image sensor panel 141. AOUT1 represents the signal of the first active drive end AOUT 1. AOUT2 represents a signal of the second active driving end AOUT 2. AOUT3 represents a signal of the third active driving end AOUT 3.

Fig. 8 shows a signal timing chart of the second drive generation circuit 132 in the embodiment of the present invention. Where CLKC represents a control clock signal CLKC generated by clock generation circuit 110 (e.g., the control clock signal CLKC may be a 200MHz clock pulse signal). vcpl represents a signal loaded by the first passive control signal terminal VCP 1. VCP3, represents the signal carried by the third passive control signal terminal VCP 3. VCP4, represents the signal carried by the fourth passive control signal terminal VCP 4. VCP5, represents the signal carried by the fifth passive control signal terminal VCP 5. pp-en represents the state control signal corresponding to the state output OU-P output of the passive pixel image sensor panel 142. POUT1 represents the signal of the first passive drive terminal POUT 1. POUT2 represents the signal of the second passive drive terminal POUT 2.

Fig. 9 shows a timing chart of signals output by the detection driving circuit according to the embodiment of the present invention. Here, AOUT1 represents a signal output by the first active driving end AOUT 1. AOUT2 represents the signal output by the second active driving terminal AOUT 2. AOUT3 represents the signal output by the third active driving end AOUT 3. POUT1 represents the signal output by the first passive drive terminal POUT 1. POUT2 represents the signal output by the second passive drive terminal POUT 2.

Specifically, the clock generation circuit 110 may generate a control clock signal CLKC of 200MHz from a clock pulse signal of 50MHz loaded by the reference clock terminal CLK0, and supply the generated control clock signal CLKC to the first drive generation circuit 131 and the second drive generation circuit 132, respectively.

The simutexth D flip-flop DT6, the eleventh comparator D11, and the eighth D flip-flop DT8 of the state recognition circuit 120 work IN conjunction with each other, and can cause the output terminal of the eighth D flip-flop DT8 to output A signal OU-A corresponding to the state output terminal OU-A of the active pimutexel image sensor panel 141, based on the 50MHz clock pulse signal applied from the reference clock terminal CLK0, the signal IN-A corresponding to the state input terminal IN-A of the active pimutexel image sensor panel 141, and the signal of the ground terminal GND.

The seventh D flip-flop DT7, the twelfth comparator D12, and the ninth D flip-flop DT9 of the state recognition circuit 120 work IN conjunction with each other, and may cause the output terminal of the ninth D flip-flop DT9 to output a signal OU-P corresponding to the state output terminal OU-P of the passive pixel image sensor panel 142 according to the 50MHz clock pulse signal loaded from the reference clock terminal CLK0, the signal IN-P corresponding to the state input terminal IN-P of the passive pixel image sensor panel 142, and the signal of the ground terminal GND.

The first inverter ND, the first to seventh selectors M1 to M7, the first to fourth comparators D1 to D4, the first to eighth and gates Y1 to Y8, and the first to third flip-flops DT1 to DT3 in the first drive generation circuit 131 work in conjunction with each other, and may be operated according to the control clock signal CLKC of 200MHz, the signal vcal loaded to the first active control signal terminal VCA1, the signal VCA2 loaded to the second active control signal terminal VCA2, and the signal VCA3 loaded to the third active control signal terminal VCA 3. The signal VCA4 loaded at the fourth active control signal terminal VCA4, the signal of the value of the first reference signal terminal VREF1, and the state control signal ap-en output corresponding to the state output terminal OU-a of the active pimutexel image sensor panel 141 may cause the output terminal of the first D flip-flop DT1 to output the signal AOUT1 (i.e., the signal of the first active driving terminal AOUT 1), may cause the output terminal of the second D flip-flop DT2 to output the signal AOUT2 (i.e., the signal of the second active driving terminal AOUT 2), and may cause the output terminal of the third D flip-flop DT3 to output the signal AOUT3 (i.e., the signal of the third active driving terminal AOUT 3).

The fifth to tenth comparators D5 to D10, the ninth to twelfth and gate Y9 to Y12, the eighth to eleventh selectors M8 to M11, the fourth D flip-flop DT4, the fifth D flip-flop DT5, and the memory RM in the second drive generation circuit 132 work in combination with each other, and may cause the output terminal of the fourth D flip-flop 4 to output the signal pout1, and the output terminal of the fifth D flip-flop DT5 to output the signal pout5, depending on the control clock signal CLKC of 200MHz, the signal VCP1 of the first passive control signal terminal VCP1, the signal VCP3 of the third passive control signal terminal VCP3, the signal VCP4 of the fourth passive control signal terminal VCP4, the signal VCP5 of the fifth passive control signal terminal vcdt 5, the signal of the value of the second reference signal terminal 2, and the state control signal pp-en corresponding to the state output terminal OU-P output of the passive pixel image sensor panel 142.

It should be noted that the signal IN-A corresponding to the status input terminal IN-A of the active pixel image sensor panel 141 is provided by A driving IC (Integrated Circuit) IN the active pixel image sensor panel 141. Also, the signal AOUT1 of the first active driving terminal AOUT1, the signal AOUT2 of the second active driving terminal AOUT2, and the signal AOUT3 of the third active driving terminal AOUT3 are respectively provided to the driving ICs in the active pixel image sensor panel 141, so that the driving ICs in the active pixel image sensor panel 141 drive the active pixel image sensor panel 141 to operate.

Also, the signal IN-P corresponding to the status input terminal IN-P of the passive pixel image sensor panel 142 is provided by a driver IC (Integrated Circuit) IN the passive pixel image sensor panel 142. Also, the signal POUT1 of the first passive driving terminal POUT1 and the signal POUT2 of the second passive driving terminal POUT2 are respectively supplied to the driving ICs in the passive pixel image sensor panel 142, so that the driving ICs in the passive pixel image sensor panel 142 drive the passive pixel image sensor panel 142 to operate.

It should be noted that the voltages and frequencies of the signals in the signal timing diagrams shown in fig. 6 to 9 are for illustrative purposes only, and are not specific voltages and frequencies applied during actual operation. In practical applications, the voltages and frequencies in the signal timing diagrams shown in fig. 6 to 9 may be designed and determined according to requirements of practical applications, and are not limited herein.

Based on the same inventive concept, the embodiment of the invention also provides a detection device, which comprises the detection driving circuit provided by the embodiment of the invention. The principle of the detection device for solving the problems is similar to that of the detection driving circuit, so the implementation of the detection device can be referred to the implementation of the detection driving circuit, and repeated parts are not described herein again.

According to the detection driving circuit, the driving method and the detection device provided by the embodiment of the invention, the clock generation circuit 110, the state identification circuit 120 and at least two driving generation circuits are arranged, wherein the clock generation circuit 110 can generate a control clock signal CLKC according to a signal of a reference clock end CLK 0; the state identification circuit 120 may output a state control signal corresponding to each state input terminal one by one through each state output terminal according to the reference clock terminal CLK0 and the signals of each state input terminal; the drive generation circuit may generate a drive control signal according to the control clock signal CLKC and a state control signal output from an electrically connected state output terminal, and output the drive control signal through the drive output terminal. This enables the detection drive circuit to generate a drive control signal for driving the image sensor panel to operate. And, since the driving output terminal is configured to electrically connect the corresponding image sensor panel, the image sensor panel can be driven to operate to perform performance detection on the image sensor panel after the driving control signal is input to the image sensor panel.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A detection drive circuit, comprising: a clock generation circuit, a state identification circuit and at least two drive generation circuits;

2. The detection drive circuit according to claim 1, wherein the image sensor panel comprises: an active pixel image sensor panel;

3. The detection drive circuit of claim 2, wherein the drive output of the first drive generation circuit comprises: the driving device comprises a first driving end, a second driving end and a third driving end;

4. The detection drive circuit according to claim 2 or 3, wherein the image sensor panel includes: a passive pixel image sensor panel;

5. The detection drive circuit of claim 4, wherein the drive output of the second drive generation circuit comprises: a first passive driving end and a second passive driving end;

6. The detection drive circuit according to claim 4, wherein the state recognition circuit includes: sixth to ninth D flip-flops, an eleventh comparator, and a twelfth comparator;

7. A driving method of the detection driving circuit according to any one of claims 4 to 6, wherein the driving method comprises:

8. The driving method of a detection driving circuit according to claim 7, wherein the image sensor panel comprises: active pixel image sensor panels; the driving generation circuit generates a driving control signal according to the control clock signal and a state control signal output by the state output end and is electrically connected with the control clock signal, and outputs the driving control signal through the driving output end, and the driving generation circuit specifically comprises: the first drive generation circuit generates a drive control signal corresponding to the active pixel image sensor panel according to the control clock signal and a state control signal corresponding to the active pixel image sensor panel;

9. The driving method of the detection driving circuit according to claim 8, wherein the state identification circuit outputs the state control signal corresponding to each of the state input terminals one-to-one through each of the state output terminals according to the control clock signal and the signal of each of the state input terminals, and specifically includes:

10. A detection device comprising a detection drive circuit according to any one of claims 1 to 6.