CN111491100A - Method for reducing image processing power consumption on embedded platform - Google Patents
Method for reducing image processing power consumption on embedded platform Download PDFInfo
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- CN111491100A CN111491100A CN202010311926.8A CN202010311926A CN111491100A CN 111491100 A CN111491100 A CN 111491100A CN 202010311926 A CN202010311926 A CN 202010311926A CN 111491100 A CN111491100 A CN 111491100A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
Abstract
The invention provides a method for reducing image processing power consumption on an embedded platform, which comprises the steps of 1) converting Cameralink image data into parallel port data by adopting an L VDS decoding chip, 2) converting the parallel port data into MIPI-CSI data by adopting a bridge chip, 3) outputting the MIPI-DSI data after image processing is carried out on the data, 4) converting the MIPI-DSI data into parallel port data by adopting the bridge chip, and 5) converting the parallel port data into Cameralink image data by adopting a L VDS coding chip.
Description
Technical Field
The invention relates to the field of application of a special image platform, in particular to a method for reducing image processing power consumption on an embedded platform.
Background
The Cameralink protocol is a serial communication protocol specially aiming at the field of machine vision application, and uses low voltage differential signals (L VDS) to carry out data transmission and communication, the Cameralink interface is a video data interface in the physical layer of the Cameralink transmission protocol, the video data interface mainly comprises 5 pairs of differential signals, wherein 4 pairs are video data, and 1 pair is a synchronous clock signal, a video data part sending terminal converts 28 bit parallel data signals into 4 pairs of differential signals according to the ratio of 7:1, wherein the 28 bit parallel data comprises 24 bit image data and 4 bit video control signals.
In military early warning and reconnaissance, portable or handheld optoelectronic devices in the field of civil security and protection generally use industrial-grade visible light cameras, thermal infrared imagers and the like as image sources, and the image sources often send video signals through a Cameralink interface. Such devices are usually powered by batteries, and need to perform corresponding image processing on video signals according to different application scenes, and have high requirements on power consumption of a processing platform in order to achieve long endurance time. With the development of embedded processing chips, the advantages of the embedded processing platform in the aspects of performance, power consumption and algorithm transplantation become more and more obvious, the trend of image processing software is towards the trend, and the embedded processing platform adopted in the equipment becomes a mainstream design as an image processing core. The interface type of an embedded chip has certain limitation, the embedded chip which is not used in the field of image processing at present has an MIPI (mobile industry processor interface), the conversion from a Cameralink interface to the MIPI interface is still an industry pain point, the mainstream design idea is that an FPGA (field programmable gate array) is generally adopted for interface conversion, the hardware programming is complex and the cost is high when the video parameters of the MIPI interface are configured, and the FPGA chip has high power consumption and is not suitable in an application scene with strict power consumption requirement.
Disclosure of Invention
The purpose of the invention is as follows: the technical problem to be solved by the invention is to provide a method for reducing the power consumption of image processing on an embedded platform, which can be applied to portable or handheld photoelectric equipment, aiming at the defects of the prior art. The method comprises the following steps: establishing a Cameralink to MIPI-CSI conversion unit, an image processing unit and an MIPI-DSI to Cameralink conversion unit;
the Cameralink-to-MIPI-CSI conversion unit is used for converting image data input by an image source through a Cameralink interface into MIPI-CSI image data;
the image processing unit is used for processing the MIPI-CSI image data and outputting the processed image into MIPI-DSI data;
the MIPI-DSI to Cameralink conversion unit is used for converting MIPI-DSI data into image data output through a Cameralink interface.
The method comprises the steps of firstly converting a Camera alink image signal into an MIPI (Mobile industry processor Interface including a display command Interface DCS, a display bus Interface DBI, a display pixel Interface DPI, a camera serial Interface CSI and a display serial Interface DSI) signal through a circuit, then finishing specific image processing in an image processing unit (the core is an embedded processor), and finally converting the Camera alink image signal back to the Camera alink signal through the circuit.
The Camera L ink transmission protocol is a communication protocol specially aiming at the machine vision field, and uses L VDS (low voltage differential signal) to transmit, and the video data signal is the core of Camera L ink, and comprises 5 pairs of differential signals, wherein 4 pairs are data signals, 1 pair is clock synchronization signals.
The Cameralink-to-MIPI-CSI conversion unit is formed by serially connecting a low-voltage differential signal L VDS-to-Parallel signal Parallel decoding module and a Parallel signal-to-MIPI-CSI bridging module in sequence;
the low-voltage differential signal L VDS-to-Parallel signal Parallel decoding module comprises a L VDS decoding chip, wherein the L VDS decoding chip is used for converting the Cameralink differential signal into a 28-bit Parallel data signal, the voltage of an output signal is 3.3V, the core is a L VDS 28-bit channel decoding chip, and a typical model conforming to the characteristics is DS90CR 288A;
the parallel signal and MIPI-CSI bridge module comprises a bridge chip for converting a 28-bit parallel data signal into a 4-channel MIPI-CSI (second edition of MIPI-CSI) signal, and the invention adopts a specific bridge chip TC358746 or TC 358748.
The image processing unit comprises an embedded processor, the embedded processor is provided with an MIPI-CSI input interface, an MIPI-DSI output interface and an IIC communication interface, and one characteristic-conforming embedded processor model is RK 3399.
An embedded processor in the image processing unit firstly calls an image signal processing ISP framework of the image processing unit to capture a video stream input by the MIPI-CSI interface, then carries out UI interface increasing, image zooming, image enhancing and pseudo-color display processing on MIPI-CSI image data according to use requirements, and finally calls the image signal processing ISP framework to configure the processed image into an RGB888 format and send the RGB888 format through the MIPI-DSI interface.
In step 3, the MIPI-DSI-to-Cameralink conversion unit is formed by serially connecting an MIPI-DSI-to-Parallel module and a Parallel-to-L VDS coding module in sequence;
the MIPI-DSI to parallell module comprises an MIPI-DSI to RGB chip and is used for converting MIPI-DSI signals in an RGB888 format into Parallel signals in an RGB888 format, and the model of the MIPI-DSI to RGB chip is ICN 6211;
the parallell-to-L VDS coding module comprises a L VDS coding chip for converting Parallel signals in RGB888 format into low-voltage differential signals, the core is a L VDS28 bit channel coding chip, and a typical model conforming to the characteristics is DS90CR 287.
The TC358746 or TC358748 chip is configured through the IIC interface of the embedded processor.
The MIPI-DSI to Cameralink conversion unit is configured to convert MIPI-DSI data into image data output through a Cameralink interface, and specifically includes:
MIPI-DSI data is accessed to a conversion chip in an MIPI-to-RGB module, and the MIPI-DSI data is decoded into RGB888 parallel data through the conversion chip, wherein a specific conversion chip ICN6211 is adopted;
through a parallell-to-L VDS encoding module in the MIPI-DSI-to-Cameralink conversion unit, RGB888 Parallel data is converted into Cameralink image data and output to a back-end device, specifically:
the RGB888 parallel data is accessed into an L VDS 28-bit channel coding chip according to the corresponding relation in a coder chip manual, and the image data output after the conversion of the coding chip is high-speed serial Cameralink data.
The invention converts a Cameralink image source into an MIPI-CSI signal, performs image processing on the embedded processor, and converts the processed signal back into a Cameralink signal.
The embedded processor sets the value of an internal register of a bridge chip through an IIC communication interface, because Camera L ink has no fixed communication specification, the difference exists in transmission time sequence and definition, and the interface compatibility of different devices is not high.
The embedded processor sets the value of an internal register of a conversion chip through an IIC communication interface, and the value of the register is set through the embedded processor, so that the value of the internal register of the conversion chip is not fixed, the difference exists in transmission time sequence and definition due to the fact that Camera L ink does not have fixed communication specifications, and interface compatibility of different devices is not high.
The invention indirectly adds a first-stage parallel signal in the signal conversion process, and solves the problems of high power consumption and self-development of a protocol in the traditional method for directly converting a camera link signal into an MIPI-CSI signal through FPGA (field programmable gate array) programming.
Has the advantages that: the invention provides a low-power consumption method for realizing image processing through the mutual conversion between a Cameralink interface and an MIPI interface, which adopts an embedded chip to complete the configuration of the MIPI interface on the basis of realizing the mutual conversion between the Cameralink interface and the MIPI interface; the ISP frame in the embedded chip can adapt to video signals of various formats sent by different image sources when interface conversion is carried out, and can convert the video signals into video output with specific frame frequency and resolution. The method provided by the invention has the advantages of obvious power consumption and cost, and low engineering implementation difficulty.
Drawings
The foregoing and/or other advantages of the invention will become further apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.
FIG. 1 is a schematic flow diagram of a process according to the present invention.
Fig. 2 is a schematic diagram illustrating a correspondence relationship between a Cameralink protocol transmission signal and a video signal.
Fig. 3 is a schematic diagram of an implementation structure of the camera link to MIPI-CSI converting unit and the image processing unit.
Fig. 4 is a schematic diagram of an implementation structure of the MIPI-DSI to Cameralink conversion unit.
Detailed Description
Referring to fig. 1, according to an embodiment of the present invention, a low power consumption method for implementing image processing by interworking a Cameralink interface and a MIPI interface includes the following steps:
1. cameralink to MIPI-CSI conversion
Step 1, converting image data input by an image source through a Cameralink interface into MIPI-CSI image data through a Cameralink to MIPI-CSI conversion unit, specifically:
image data input by an image source through a Cameralink interface is high-speed serial data, comprising 5 pairs of differential signal lines, of which 4 pairs are video data lines and 1 pair is a synchronous clock signal, and a L VDS 28-bit channel receiving decoder (typical chip DS90CR288A) decodes the parallel data into 1.8V or 3.3V, wherein the 28-bit parallel data comprises 24-bit image data and 4-bit video control signals.
Step 2, converting the parallel data (intermediate data) into MIPI-CSI image data through a parallel signal and MIPI-CSI bridge module in a Cameralink to MIPI-CSI conversion unit, specifically:
the currently applicable bridge chip is Toshiba TC358746 or TC358748, the chip data interface is an MIPI-CSI2 interface and a Parallel interface respectively, the configuration interface is IIC or SPI, the Parallel interface comprises 24-bit data, line effective signals and field effective signals and can be accessed into Parallel signals of 1.8V or 3.3V, the Parallel interface is set to be a Parallel to Mipi-CSI2 TX mode and an IIC interface configuration mode which are applicable to the invention by setting MSE L and CS pin level of the bridge chip, FIG. 2 shows the corresponding relation defined by Cameralink protocol transmission signals and video signals, the converted Parallel data (intermediate data) is accessed into the Parallel port of the bridge chip according to the corresponding relation, TX/RX26 in the Parallel data is data effective signals, no butt signals are available in the bridge chip and the bridge chip is suspended, and then according to the line field timing sequence of the accessed image, the register configuration in the bridge chip is completed by an image processing unit through the IIC interface.
2. Image processing
An ISP framework of an embedded chip is called to capture a video stream input by an MIPI-CSI interface, a proper software program is run on an image according to use requirements, for example, a UI interface, image scaling, image enhancement, pseudo color display and the like are added (without limitation to the algorithm), then the ISP framework is called to configure the processed image into an RGB888 format according to a certain SWAP mode (more than 8-bit gray level images can be respectively filled into corresponding RED, GREEN and B L UE channels according to a SWAP table) and output from the MIPI-DSI interface.
MIPI-DSI to Cameralink transition
Step 1, converting the processed image from the MIPI-DSI image data to Parallel data (intermediate data) by an MIPI-DSI to Parallel module in an MIPI-DSI to Cameralink conversion unit, specifically:
the processed MIPI-DSI image data is accessed to a conversion chip (a typical chip ICN6211) in the MIPI-DSI to parallell module, the embedded processor completes the register configuration in the conversion chip through an IIC interface according to the SWAP mode, and the image data is decoded into RGB888 Parallel data according to the SWAP mode through the conversion chip.
Step 2, converting Parallel data (intermediate data) into Cameralink image data and outputting the Cameralink image data to a back-end device through a Parallel to L VDS coding module in the MIPI-DSI to Cameralink conversion unit, specifically:
the parallel data is accessed into an L VDS 28-bit channel transmitting encoder (a typical chip DS90CR287) according to the corresponding relation shown in FIG. 2, and the image data output after the conversion of the transmitting encoder is high-speed serial Cameralink data, which comprises 5 pairs of differential signal lines, wherein 4 pairs are video data lines, and 1 pair is a synchronous clock signal.
The invention provides a low-power-consumption method for realizing image processing through the interconversion between a Cameralink interface and an MIPI interface, which is further detailed in the following steps by combining specific scenes. The method is implemented on an embedded platform RK3399 and a software platform linux, an implementation structure of a Cameralink-to-MIPI-CSI conversion unit and an image processing unit in the method is shown in FIG. 3, and two image input sources are adopted, namely an infrared detector with 640 x 512@50 frames and a visible light camera with 1920 x 1080@25 frames; the RK3399 core board is adopted to realize image processing, functions of UI interface increasing, image zooming, image enhancement, pseudo color display, visible light image and infrared image switching and the like are completed, and the output frame frequency and resolution can be configured at will; fig. 4 shows an implementation structure of the MIPI-DSI to Cameralink conversion unit in this example, and an image acquisition card is used to detect the converted image.
The present invention provides a method for reducing power consumption of image processing in an embedded platform, and a plurality of methods and approaches for implementing the technical solution, and the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and embellishments can be made without departing from the principle of the present invention, and these modifications and embellishments should also be regarded as the protection scope of the present invention. All the components not specified in the present embodiment can be realized by the prior art.
Claims (9)
1. A method for reducing power consumption of image processing in an embedded platform, comprising: establishing a Cameralink to MIPI-CSI conversion unit, an image processing unit and an MIPI-DSI to Cameralink conversion unit;
the Cameralink-to-MIPI-CSI conversion unit is used for converting image data input by an image source through a Cameralink interface into MIPI-CSI image data;
the image processing unit is used for processing the MIPI-CSI image data and outputting the processed image into MIPI-DSI data;
the MIPI-DSI to Cameralink conversion unit is used for converting MIPI-DSI data into image data output through a Cameralink interface.
2. The method of claim 1, wherein the Cameralink interface is a video data interface in a Cameralink transport protocol physical layer.
3. The method of claim 2, wherein the Cameralink to MIPI-CSI conversion unit is composed of a low voltage differential signal L VDS to parallel signal decoding module and a parallel signal to MIPI-CSI bridge module in series in sequence;
the low-voltage differential signal L VDS-to-Parallel signal Parallel decoding module comprises a L VDS decoding chip, and is used for converting a Cameralink differential signal into a 28-bit Parallel data signal, and the output signal voltage is 3.3V;
the parallel signal and MIPI-CSI bridge module comprises a bridge chip and is used for converting a 28-bit parallel data signal into a 4-channel MIPI-CSI signal.
4. The method of claim 3, wherein the image processing unit includes an embedded processor having a MIPI-CSI input interface, a MIPI-DSI output interface, and an IIC communication interface.
5. The method of claim 4, wherein an embedded processor in the image processing unit first calls an onboard image signal processing ISP framework to capture a video stream input by the MIPI-CSI interface, then performs UI interface addition, image scaling, image enhancement and pseudo-color display processing on MIPI-CSI image data according to use requirements, and finally calls the image signal processing ISP framework to configure the processed image into an RGB888 format and transmit the RGB888 image through the MIPI-DSI interface.
6. The method of claim 5, wherein in step 3, the MIPI-DSI to Cameralink conversion unit is composed of a MIPI-DSI to parallell module and a parallell to L VDS encoding module in series in sequence;
the MIPI-DSI to parallell module comprises an MIPI-DSI to RGB chip and is used for converting MIPI-DSI signals in an RGB888 format into Parallel signals in an RGB888 format;
the parallell-to-L VDS coding module comprises a L VDS coding chip and is used for converting Parallel signals in an RGB888 format into low-voltage differential signals.
7. The method of claim 6, wherein the MIPI-DSI to Cameralink conversion unit is configured to convert MIPI-DSI data into image data output via a Cameralink interface, and specifically includes:
the MIPI-DSI data is accessed to a conversion chip in the MIPI-to-RGB module, and the MIPI-DSI data is decoded into RGB888 parallel data through the conversion chip;
the Parallel RGB888 data is converted into Cameralink image data through a Parallel to L VDS coding module in the MIPI-DSI to Cameralink conversion unit and output to the back-end device.
8. The method of claim 7, wherein the embedded processor sets the value of the bridge chip internal register via the IIC communication interface.
9. The method of claim 8, wherein the embedded processor sets the value of the translation chip internal register via the IIC communication interface.
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