CN111490770A - Circuit and method for realizing multi-system symbol logic and operation - Google Patents
Circuit and method for realizing multi-system symbol logic and operation Download PDFInfo
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Abstract
The invention discloses a circuit and a method for realizing multi-system symbol logic and operation, wherein the circuit comprises: the logic line and circuit is used for performing logical AND operation on the input multilevel symbols and outputting a multilevel logic level with the minimum voltage value; a threshold circuit for a threshold voltage; a regeneration circuit for generating a logic level; and the output circuit is used for generating the standard voltage corresponding to the multi-system symbol. The method comprises the following steps: carrying out logical AND operation on the input multilevel symbols; comparing with a threshold voltage; generating a logic level; and converting into standard voltage corresponding to multiple logic levels. The circuit and the method for realizing the multi-system symbol logic and operation are suitable for the multi-system symbol logic and operation, and improve the information transmission efficiency, thereby improving the data transmission efficiency.
Description
Technical Field
The invention relates to the technical field of logic and circuits, in particular to a circuit and a method for realizing multi-system symbolic logic and operation.
Background
Logic operations are the basis for digital signal processing, and logic and operations are the basis in the basis.
The existing logic operation is generally based on binary logic, and the logic value of the existing logic operation only has two states of 0 and 1. This binary logic algebra was proposed by g.boole in 1854, and is hereinafter referred to as boolean algebra, and is widely applied to the fields of logic design of digital systems and the like. In such binary logic, the logical and operation is defined as: if one of the input parameters is 0, the output is 0 regardless of the other parameters; the output is 1 only if all inputs are 1.
The logic problem itself has more than two logic states. For example, the motor state logically includes at least three states of "forward rotation", "stop", and "reverse rotation", and can be further distinguished as follows: the five states of "forward rotation at maximum speed", "forward rotation", "stop", "reverse rotation" and "reverse rotation at maximum speed". At this time, if binary logic is used to describe the logic state, a multi-bit logic value is required to describe the logic state, for example, three states of "forward rotation", "stop" and "reverse rotation" require at least two-bit logic values to describe the logic state, that is, three states are selected from "00, 01, 10 and 11" to describe the logic state. It is known that the efficiency of binary logic description information is relatively low, and therefore, multi-valued logic is required to improve the efficiency of description information.
Multi-valued logic, i.e. logic values with more than two states, for example, three-valued logic includes three states of 0, 1, and 2, and four-valued logic includes four states of 0, 1, 2, and 3. If the logic states are described by multi-valued logic, for example, three states of "forward rotation", "stop", and "reverse rotation" are described by three-valued logic, only one logical value is needed to describe, namely "0, 1, 2". Therefore, the multi-value logic has higher information description efficiency compared with the binary logic.
In digital circuits, binary logic is typically represented by binary symbols, i.e., the symbol "0" and the symbol "1", and the same multi-valued logic can be represented by multi-binary symbols, e.g., the symbols "0, 1, 2, 3 …". Binary symbols are typically represented by the amplitude, frequency or phase of an electrical signal, while multilevel symbols may likewise be represented by the amplitude, frequency or phase of an electrical signal.
As digital integrated circuits are increasingly complex in design, increasingly powerful in function and smaller in area, the contradiction between the demands for fewer and fewer unit interconnection lines is more and more prominent. Because the stronger the function, the more the internal units are, the more the interconnection lines are required, and the larger the area occupied by the interconnection lines is; but the reduction of the total area naturally requires that the area occupied by the interconnect lines also be reduced. This conflict can be resolved if the information transfer rate of the interconnection lines can be effectively increased and the number of interconnection lines can be reduced. And multi-value logic is used for replacing binary logic, namely, the logic state transmitted on the interconnection line does not have two states of 0 and 1, but can contain more than two logic values, so that the data transmission efficiency can be greatly improved.
Disclosure of Invention
The invention aims to provide a circuit and a method for realizing multi-system symbol logic and operation, which are suitable for multi-system symbol logic and operation and improve the information transmission efficiency so as to improve the data transmission efficiency.
The invention discloses a circuit and a method for realizing multi-system symbolic logic and operation, which adopt the technical scheme that:
an implementation circuit of a multi-ary symbolic logical and operation, comprising:
the logic wire and circuit comprises at least two input circuits and a pull-up resistor, each input circuit comprises a first comparator and a field effect tube, the source electrode of the field effect tube is used as an input end, the grid electrode of the field effect tube is connected with the output end of the first comparator, the drain electrode of the field effect tube is connected with a power supply after being connected with the pull-up resistor in series as an output end, the inverting input end of the first comparator is connected with the source electrode of the field effect tube, the non-inverting input end of the first comparator is connected with the drain electrode of the field effect tube, each input end obtains input multilevel symbols, the multilevel symbols are represented by multiple levels, the multilevel symbols comprise different voltage amplitude states separated by multiple thresholds, and when the voltage of the non-inverting input end of the first comparator is greater than the voltage of the inverting input end of the first comparator, the first comparator outputs high level to drive the field effect tube to be conducted and output, otherwise, the field effect tube is cut off when a low level is output, and when at least two input ends obtain the input multilevel symbol, the logic line and the circuit output the multilevel symbol with the minimum voltage value.
A threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish states of the different voltage amplitudes;
the regenerative circuit comprises a plurality of second comparators corresponding to a threshold voltage, the non-inverting input end of each second comparator is connected with the output end of the circuit through a logic line, the input end of each second comparator inputs different threshold voltages, and the second comparators compare the threshold voltages with multilevel symbols to generate logic levels; and the number of the first and second groups,
and the output circuit is used for generating the standard voltage corresponding to the multilevel symbol, and the plurality of logic levels generate the standard voltage corresponding to the multilevel symbol after passing through the output circuit.
Preferably, the output circuit includes a plurality of voltage dividing resistors corresponding to the second comparators, an output end of each second comparator is connected in series with one voltage dividing resistor, the voltage dividing resistors are connected in parallel, and the plurality of logic levels generate the standard voltage after being divided by the voltage dividing resistors.
Preferably, the output circuit includes:
the driving circuit comprises reverse buffers, a plurality of third comparators and a plurality of resistors, wherein one of the third comparators is less than the second comparators, the output end of each second comparator is connected with a resistor in series, the input end of each reverse buffer is connected with a resistor in series and then is grounded and is also connected with a resistor in series with the output end of one of the second comparators, the threshold voltage with the lowest voltage value is input at the reverse phase input end of one of the second comparators, the input end of each buffer is connected with a resistor in series and then is connected with a power supply and is also connected with a resistor in series with the output end of the other second comparator, the threshold voltage with the highest voltage value is input at the reverse phase input end of the other second comparator, a resistor is connected in parallel between the non-phase input end and the reverse phase input end of the third comparator, and the adjacent third comparators are connected by connecting a resistor in series between the non-phase input end and the reverse phase input, the connected third comparators are connected in parallel between the reverse buffer and the buffer, the inverting input end of each third comparator is connected with the resistor connected with the output end of each second comparator in series, and the plurality of logic levels drive the third comparators, the buffer or the reverse buffer to output low levels or high levels after being subjected to resistor voltage division;
the standard voltage circuit comprises a plurality of standard voltage sources and a plurality of switch devices, wherein the standard voltage sources are used for providing standard voltages corresponding to multi-system symbols, the input ends of the switch devices are connected with the standard voltage sources, the driving ends of the switch devices are connected with the output end of the driving circuit, and high levels output by the driving circuit drive the switch devices to be conducted and output the corresponding standard voltages.
Preferably, the device further comprises an output buffer circuit, and the standard voltage is output after passing through the buffer circuit.
Preferably, the circuit further comprises an input buffer circuit, and the input multi-system symbol is output to the logic line and circuit after passing through the buffer circuit.
Based on the circuit, the method for realizing the multi-system symbolic logic AND operation comprises the following steps:
inputting at least two multilevel symbols and outputting the multilevel symbol with the minimum voltage value;
respectively comparing the multi-system symbol with a plurality of corresponding threshold voltages to generate a plurality of logic levels;
and the plurality of logic levels generate standard voltages corresponding to the multilevel symbols after passing through the output circuit.
The circuit and the method for realizing the multi-system symbolic logic and operation have the beneficial effects that: only when the voltage at the output end of the field effect transistor is greater than the voltage at the input end of the field effect transistor, the comparator outputs high level to enable the field effect transistor to be conducted, and therefore the logic line and the circuit can select the multi-system symbol corresponding to the multi-system symbol with the minimum output voltage value. After the multi-system symbol passes through the regeneration circuit, a plurality of logic levels are generated, and the transmission noise and errors of the multi-system symbol are eliminated. Furthermore, because the plurality of logic levels are generated by comparing the multilevel symbol with the threshold voltage, the generated plurality of logic levels have the information and the characteristics of the multilevel symbol, and the plurality of logic levels are converted into the standard voltage corresponding to the multilevel symbol through the output circuit according to the information and the characteristics, so that the standard voltage can ensure the accuracy of the logic judgment of the digital circuit. The multi-system symbol is used for representing the multi-system symbol, meanwhile, the transmission error of the multi-system symbol is eliminated, and the accuracy of the state judgment of the multi-system symbol is improved. The circuit is essentially suitable for multi-system symbol logic and operation, so that the multi-system symbol logic and circuit can be practically applied, and the multi-system symbols are transmitted by using the multi-system symbols, so that the transmission efficiency of information is improved, and the data transmission efficiency is improved.
Drawings
Fig. 1 is a schematic diagram of a circuit for implementing the multi-ary sign and operation according to a first embodiment of the present invention.
FIG. 2 is a schematic signal flow diagram of a circuit for implementing the multi-ary symbolic AND operation according to the present invention.
Fig. 3 is a schematic diagram of a circuit for implementing the multi-ary sign and operation according to the second embodiment of the present invention.
FIG. 4 is a flow chart of a method for implementing the multi-ary symbolic logical AND operation of the present invention.
Detailed Description
The invention will be further elucidated and described with reference to the embodiments and drawings of the specification:
example one
Referring to fig. 1, fig. 2 and fig. 4, the circuit for implementing the multilevel symbolic logical and operation includes a logical line and circuit, a threshold circuit, a regeneration circuit and an output circuit.
The logic wired-and circuit includes at least two input circuits 100 and pull-up resistors. Each input circuit 100 includes a first comparator and a field effect transistor, the source of the field effect transistor is used as the input terminal, the gate of the field effect transistor is connected with the output terminal of the first comparator, the drain of the field effect transistor is connected with the power supply after being connected with a pull-up resistor in series as the output terminal, the inverting input terminal of the first comparator is connected with the source of the field effect transistor, and the non-inverting input terminal of the first comparator is connected with the drain of the field effect transistor.
Each input terminal obtains an input multilevel symbol, the multilevel symbol being represented by a plurality of levels, the multilevel symbol comprising states of different voltage magnitudes separated by a plurality of thresholds. When the voltage of the same-phase input end of the first comparator is greater than that of the reverse-phase input end thereof, the first comparator outputs high level to drive the field effect tube to conduct and output, the voltage of the output end of the field effect tube is clamped to be slightly greater than that of the input end thereof, when the field effect tube is used as a switch, the conduction voltage drop is negligible, otherwise, low level is output, and the field effect tube is cut off. Due to the action of the comparator, only the field effect tube with the lowest input voltage can be conducted and output, and the operation of multi-system symbol logical AND is realized. When at least two input ends obtain the input multi-system symbol, the logic line and the circuit output the multi-system symbol with the minimum voltage value.
And the threshold circuit is used for providing a plurality of threshold voltages corresponding to the multi-system symbols, and the threshold voltages are used for distinguishing states with different voltage amplitudes.
The regeneration circuit comprises a plurality of second comparators corresponding to the threshold voltage, the non-inverting input end of each second comparator is connected with the output end of the circuit through a logic line, the inverting input end of each second comparator inputs different threshold voltages, and the second comparator compares the threshold voltages with the multi-system symbols to generate logic levels.
The output circuit comprises a plurality of divider resistors corresponding to the second comparators, the output end of each second comparator is connected with one divider resistor in series, the divider resistors are connected in parallel, and the plurality of logic levels generate the standard voltage after being divided by the divider resistors.
The circuit also comprises an input buffer circuit, wherein the input buffer circuit comprises a buffer, and the input multi-system symbols are output to the logic line AND circuit after passing through the buffer.
The output buffer circuit comprises a zero-gain operational amplifier, and the standard voltage is output after passing through the zero-gain operational amplifier.
Only when the voltage at the output end of the field effect transistor is greater than the voltage at the input end of the field effect transistor, the comparator outputs high level to enable the field effect transistor to be conducted, and therefore the logic line and the circuit can select the multi-system symbol corresponding to the multi-system symbol with the minimum output voltage value. After the multi-system symbol passes through the regeneration circuit, a plurality of logic levels are generated, and the transmission noise and errors of the multi-system symbol are eliminated. Furthermore, because the plurality of logic levels are generated by comparing the multilevel symbol with the threshold voltage, the generated plurality of logic levels have the information and the characteristics of the multilevel symbol, and the plurality of logic levels are converted into the standard voltage corresponding to the multilevel symbol through the output circuit according to the information and the characteristics, so that the standard voltage can ensure the accuracy of the logic judgment of the digital circuit. The multi-system symbol is used for representing the multi-system symbol, meanwhile, the transmission error of the multi-system symbol is eliminated, and the accuracy of the state judgment of the multi-system symbol is improved. The circuit is essentially suitable for multi-system symbol logic and operation, so that the multi-system symbol logic and circuit can be practically applied, and the multi-system symbols are transmitted by using the multi-system symbols, so that the transmission efficiency of information is improved, and the data transmission efficiency is improved.
In this embodiment, a 5V logic system will be described. The multilevel symbol comprises five states, wherein the level 0 is defined below 1V, and the standard voltage is 0.5V; the level 1 is between 1.1V and 1.9V, and the standard voltage is 1.5V; the level 2 is between 2.1V and 2.9V, and the standard voltage is 2.5V; the level 3 is between 3.1V and 3.9V, and the standard voltage is 3.5V; the voltage of 4.1V or more is level 4, and the standard voltage thereof is 4.5V. Other voltage values are level transition voltages, requiring the nearest level to be rounded up. When all the input ports are not connected and present a high impedance state, the operation module outputs a default level 0.
The circuit of this embodiment can be used for a logical and operation of a five symbol. Level 0 represents the symbol "0", level 1 represents the symbol "1", and so on.
As can be seen from the above, the multilevel symbol includes four threshold voltages, which are 1V, 2V, 3V and 4V respectively. Correspondingly, the threshold circuit comprises 5 resistors connected in series, and each resistor is divided into 1V voltage, so that the threshold voltages corresponding to the five-value logic are respectively 4V, 3V, 2V and 1V, and respectively correspond to nodes 10-13 in FIG. 1. Each of which may also be provided by a standard power supply.
Correspondingly, the regeneration circuit comprises 4 second comparators, wherein the non-inverting input end of each second comparator is connected with the logic line and the circuit output end, and the inverting input end of each second comparator is connected with different threshold voltages. When the voltage of the non-inverting input terminal of the second comparator is larger than that of the inverting input terminal, a logic high level is output, otherwise, a logic low level is output.
Correspondingly, the output circuit comprises 4 divider resistors, one divider resistor is connected with the output end of the second comparator in series, and the divider resistors are connected in parallel. And the logic high level or the logic low level output by all the second comparators generates standard voltage corresponding to the multilevel symbol after being subjected to voltage division by the voltage division resistors.
It can be known from the circuit of this embodiment that, when deriving the circuit for other multi-system sign logical and operations, only the number of the threshold voltages needs to be changed, and the second comparator and the voltage dividing resistor perform the corresponding number change.
In this embodiment, for convenience of understanding, the high level and the low level output by the second comparator are 4.5V and 0.5V, and the resistance values of the voltage dividing resistors connected in series with the output end of the second comparator are all equal to each other, so that the resistance value is R. It should be noted that, in practice, the high level amplitude, the low level amplitude and the resistance of the divider resistor output by the second comparator can be calculated according to the required result.
The circuit of the present embodiment will be described by taking three inputs as an example. The corresponding logic and circuit includes three input circuits 100.
Assume that node 1 inputs level 1, the reference voltage is 1.5V, node 2 inputs level 2, the reference voltage is 2.5V, node 3 inputs level 3, and the reference voltage is 3.5V.
From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly larger than 1.5V. Since 1.5V is only greater than the threshold voltage of 1V, node 9 outputs a high level of 4.5V and nodes 6, 7 and 8 all output a low level of 0.5V. The voltage of the output out at this time is:
exactly the standard voltage for level 1.
Assume that node 1 inputs level 2, the reference voltage is 2.5V, node 2 inputs level 2, the reference voltage is 2.5V, node 3 inputs level 3, and the reference voltage is 3.5V. Assume that the level is disturbed during transmission and becomes 2.2V at node 1, 2.7V at node 2 and 3.3V at node 3.
From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly larger than 2.2V. Since 2.2V is greater than 2V and less than 3V, nodes 9 and 8 output 4.5V high and nodes 6 and 7 both output 0.5V low. The voltage of the output out at this time is:
exactly the standard voltage for level 2.
The level 0 is input to the node 1, the standard voltage is 0.5V, the level 2 is input to the node 2, the standard voltage is 2.5V, the level 3 is input to the node 3, and the standard voltage is 3.5V. From the above analysis, the node 4 is a high level output, and the output voltage of the node 5 is slightly larger than 0.5V. Assuming interference during transmission, 0.5V becomes 0.8V.
Since 0.8V is less than all threshold voltages, nodes 9, 8, 7 and 6 all output a low level of 0.5V. The voltage of the output out at this time is 0.5V, which is exactly the standard voltage corresponding to the level 0.
According to the embodiment, the logic line and the circuit can select the multilevel symbol corresponding to the multilevel symbol with the minimum output voltage value, the multilevel symbol generates a plurality of logic levels after passing through the regeneration circuit, and the plurality of logic levels generate the standard voltage corresponding to the multilevel symbol through the divider resistor, namely the multilevel symbol, so that the accuracy of the logic judgment of the digital circuit is ensured. Meanwhile, the conducting voltage of the logic line and the circuit is reduced, and more levels in different states can be divided under the same voltage amplitude. The multi-system symbol is compared with the threshold voltage to generate a logic level, and the transmission noise and the error of the multi-system symbol are eliminated firstly. Further, since the multilevel symbol is compared with the threshold voltage, the generated logic level carries the information and characteristics of the multilevel symbol, and the logic level is converted into the standard voltage corresponding to the multilevel symbol according to the information and characteristics.
As can be seen from the conventional knowledge, the more levels are divided within the same voltage amplitude, the smaller the voltage difference between the levels of the adjacent states is, which easily causes the logic judgment of the digital circuit to be misplaced. The circuit uses multilevel to represent the multilevel symbol, and simultaneously eliminates the transmission error of the multilevel symbol through the regeneration circuit, thereby improving the accuracy of the judgment of the multilevel symbol state.
The method for realizing the multi-system symbolic logic AND operation is based on the circuit and comprises the following steps:
s100, inputting at least two multilevel symbols and outputting the multilevel symbol with the minimum voltage value;
s110, comparing the multi-system symbol with a plurality of corresponding threshold voltages respectively to generate a plurality of logic levels;
and S120, generating standard voltages corresponding to the multilevel symbols after the logic levels pass through the output circuit.
Example two
Referring to fig. 3, the difference between the present embodiment and the first embodiment is:
the output circuit comprises a driving circuit A110, the driving circuit comprises a reverse buffer, a buffer and a plurality of resistors of a plurality of third comparators, one of the third comparators is less than the second comparator, the output end of each second comparator is connected with a resistor in series, the input end of the reverse buffer is connected with a resistor in series and then grounded and is also connected with a resistor in series with the output end of one of the second comparators, the threshold voltage with the lowest voltage value is input at the reverse phase input end of the second comparator, the input end of the buffer is connected with a resistor in series and then connected with a power supply and is also connected with a resistor in series with the output end of the other second comparator, the threshold voltage with the highest voltage value is input at the reverse phase input end of the second comparator, a resistor is connected in parallel between the non-phase input end and the reverse phase input end of the third comparator, and the adjacent third comparator is connected by connecting a resistor in series between the non, the connected plurality of third comparators are connected in parallel between the reverse buffer and the buffer, the inverting input end of each third comparator is connected with the resistor connected in series with the output end of each second comparator,
and after the plurality of logic levels are subjected to resistance voltage division, the third comparator, the buffer or the reverse buffer is driven to output low level or high level.
The standard voltage circuit A120 is further included, the standard voltage circuit comprises a plurality of resistors and a plurality of field effect transistors corresponding to the multilevel symbols, a power supply is connected between the resistors after the resistors are connected in series, the resistors after the resistors are connected in series are used for providing the standard voltage corresponding to the multilevel symbols, different standard voltages are input into drain electrodes of the field effect transistors, grid electrodes of the field effect transistors are connected with the output end of the regeneration circuit, and source electrodes of the field effect transistors serve as the output end of the standard voltage circuit. The high level output by the driving circuit controls the conduction of the corresponding field effect tube, and the field effect tube outputs the corresponding standard voltage after being conducted. The standard voltage is provided by dividing voltage with resistors, and the standard voltage can also be provided by a standard power supply. When the field effect transistor is used as a switch, the conduction voltage drop of the field effect transistor is negligible.
In this embodiment, a 5V logic system will be described. The multilevel symbol comprises five states, wherein the level 0 is defined below 1V, and the standard voltage is 0.5V; the level 1 is between 1.1V and 1.9V, and the standard voltage is 1.5V; the level 2 is between 2.1V and 2.9V, and the standard voltage is 2.5V; the level 3 is between 3.1V and 3.9V, and the standard voltage is 3.5V; the voltage of 4.1V or more is level 4, and the standard voltage thereof is 4.5. Other voltage values are level transition voltages, requiring the nearest level to be rounded up. When all the input ports are not connected and present a high impedance state, the operation module outputs a default level 0.
The circuit of this embodiment can be used for a logical and operation of a five symbol. Level 0 represents the symbol "0", level 1 represents the symbol "1", and so on.
Correspondingly, the driving circuit a110 includes 3 third comparators, buffers, inverting buffers, and 11 resistors. When the voltage of the non-inverting input end of the third comparator is greater than that of the inverting input end, the third comparator outputs a logic high level, otherwise, the third comparator outputs a logic low level.
Correspondingly, the standard voltage circuit a120 includes 6 resistors and 5 fets, and the standard voltages provided by the 6 resistors are 0.5V, 1.5V, 2.5V, 3.5V, and 4.5V. When the grid of the field effect transistor is at high level, the field effect transistor is conducted to output corresponding standard voltage, otherwise, when the grid is at low level, the field effect transistor is cut off. Because the conduction voltage drop of the field effect transistor as a switch can be ignored, the output voltage of the field effect transistor is equivalent to the input voltage, namely the standard voltage.
The circuit of the present embodiment will be described by taking three inputs as an example.
Assume that the node a1 inputs level 1, the standard voltage is 1.5V, the node a2 inputs level 2, the standard voltage is 2.5V, the node A3 inputs level 3, and the standard voltage is 3.5V.
From the above analysis, the node A4 is high output, and the output voltage of the node A5 is slightly larger than 1.5V. Since 1.5V is only greater than the threshold voltage of 1V, the node a9 outputs a high level and the nodes a6, a7, and A8 all output a low level. The nodes a10, a13, a14 and a15 output low level, the node a12 outputs high level, the fet connected to the node a12 conducts output, and the voltage of the output out is 1.5V, which is just the standard voltage corresponding to level 1.
Assume that the node a1 inputs level 2, the standard voltage is 2.5V, the node a2 inputs level 3, the standard voltage is 3.5V, the node A3 inputs level 3, and the standard voltage is 3.5V. Assume that the level is disturbed during transmission, becoming node a1 input 2.2V, node a2 input 2.7V, and node A3 input 3.3V.
From the above analysis, the node A4 is high output, and the output voltage of the node A5 is slightly larger than 2.2V. Since 2.2V is greater than 2V and less than 3V in threshold voltage, the nodes a9 and A8 output high level, and the nodes a6 and a7 both output low level. The nodes a10, a12, a14, and a15 output a low level, the node a13 outputs a high level, the fet connected to the node a13 conducts the output, and the voltage of the output out at this time is 2.5V, which is just the standard voltage corresponding to the level 2.
The node a1 receives a level 0, a reference voltage of 0.5V, the node a2 receives a level 2, a reference voltage of 2.5V, the node A3 receives a level 3, and a reference voltage of 3.5V. From the above analysis, the node A4 is high output, and the output voltage of the node A5 is slightly larger than 0.5V. Assuming interference during transmission, 0.5V becomes 0.8V.
Since 0.8V is less than all the threshold voltages, the nodes a9, A8, a7, and a6 all output a low level. The nodes a12, a13, a14, and a15 output a low level, the node a10 outputs a high level, the fet connected to the node a10 conducts the output, and the voltage of the output out at this time is 0.5V, which is exactly the standard voltage corresponding to the level 0.
According to the above example, the multiple input multilevel symbols output the multilevel symbol with the minimum voltage value after passing through the logic line and the circuit, the multilevel symbol generates a plurality of logic levels after passing through the regeneration circuit, the plurality of logic levels drive the output circuit to output the standard voltage, and the standard voltage can ensure the accuracy of the logic judgment of the digital circuit.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the protection scope of the present invention, although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (6)
1. An implementation circuit for a multi-ary symbolic logical and operation, comprising:
the logic wire and circuit comprises at least two input circuits and a pull-up resistor, each input circuit comprises a first comparator and a field effect tube, the source electrode of the field effect tube is used as an input end, the grid electrode of the field effect tube is connected with the output end of the first comparator, the drain electrode of the field effect tube is connected with a power supply after being connected with the pull-up resistor in series as an output end, the inverting input end of the first comparator is connected with the source electrode of the field effect tube, the non-inverting input end of the first comparator is connected with the drain electrode of the field effect tube, each input end obtains input multilevel symbols, the multilevel symbols are represented by multiple levels, the multilevel symbols comprise different voltage amplitude states separated by multiple thresholds, and when the voltage of the non-inverting input end of the first comparator is greater than the voltage of the inverting input end of the first comparator, the first comparator outputs high level to drive the field effect tube to be conducted and output, otherwise, a low level is output, the field effect tube is cut off, and when at least two input ends obtain input multilevel symbols, the logic line and the circuit output the multilevel symbol with the minimum voltage value;
a threshold circuit for providing a plurality of threshold voltages corresponding to the multilevel symbols, the threshold voltages being used to distinguish states of the different voltage amplitudes;
the regenerative circuit comprises a plurality of second comparators corresponding to a threshold voltage, the non-inverting input end of each second comparator is connected with the output end of the circuit through a logic line, the input end of each second comparator inputs different threshold voltages, and the second comparators compare the threshold voltages with multilevel symbols to generate logic levels; and the number of the first and second groups,
and the output circuit is used for generating the standard voltage corresponding to the multilevel symbol, and the plurality of logic levels generate the standard voltage corresponding to the multilevel symbol after passing through the output circuit.
2. The circuit for implementing m-ary symbolic logic and operation according to claim 1, wherein the output circuit comprises a plurality of voltage dividing resistors corresponding to the second comparators, an output terminal of each second comparator is connected in series with one voltage dividing resistor, the voltage dividing resistors are connected in parallel, and the plurality of logic levels are divided by the voltage dividing resistors to generate the standard voltage.
3. The circuitry for implementing a multi-ary symbolic logical and operation of claim 1, wherein the output circuitry comprises:
the driving circuit comprises reverse buffers, a plurality of third comparators and a plurality of resistors, wherein one of the third comparators is less than the second comparators, the output end of each second comparator is connected with a resistor in series, the input end of each reverse buffer is connected with a resistor in series and then is grounded and is also connected with a resistor in series with the output end of one of the second comparators, the threshold voltage with the lowest voltage value is input at the reverse phase input end of one of the second comparators, the input end of each buffer is connected with a resistor in series and then is connected with a power supply and is also connected with a resistor in series with the output end of the other second comparator, the threshold voltage with the highest voltage value is input at the reverse phase input end of the other second comparator, a resistor is connected in parallel between the non-phase input end and the reverse phase input end of the third comparator, and the adjacent third comparators are connected by connecting a resistor in series between the non-phase input end and the reverse phase input, the connected third comparators are connected in parallel between the reverse buffer and the buffer, the inverting input end of each third comparator is connected with the resistor connected with the output end of each second comparator in series, and the plurality of logic levels drive the third comparators, the buffer or the reverse buffer to output low levels or high levels after being subjected to resistor voltage division;
the standard voltage circuit comprises a plurality of standard voltage sources and a plurality of switch devices, wherein the standard voltage sources are used for providing standard voltages corresponding to multi-system symbols, the input ends of the switch devices are connected with the standard voltage sources, the driving ends of the switch devices are connected with the output end of the driving circuit, and high levels output by the driving circuit drive the switch devices to be conducted and output the corresponding standard voltages.
4. The circuitry for implementing a multi-ary symbolic logical and operation of claim 1, further comprising an output buffer circuit, wherein the standard voltage is output after passing through the buffer circuit.
5. The circuitry for implementing a multi-ary symbolic logical and operation of claim 1, further comprising an input buffer circuit, wherein the input multi-ary symbol is output to the logical and circuit after passing through the buffer circuit.
6. A method for implementing a multilevel symbolic logical and operation, based on a circuit according to any of claims 1-5, the method comprising the steps of:
inputting at least two multilevel symbols and outputting the multilevel symbol with the minimum voltage value;
respectively comparing the multi-system symbol with a plurality of corresponding threshold voltages to generate a plurality of logic levels;
and the plurality of logic levels generate standard voltages corresponding to the multilevel symbols after passing through the output circuit.
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