CN111488720B - Method, device and equipment for acquiring circuit connection topology information - Google Patents
Method, device and equipment for acquiring circuit connection topology information Download PDFInfo
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Abstract
The invention discloses a method for acquiring circuit connection topology information, which comprises the following steps: s1, obtaining a circuit layout pattern; s2, acquiring all edges of the layout pattern according to the circuit layout pattern; s3, obtaining edges in a corresponding relation among the parallel edges; wherein the corresponding side is that two line segments have projection between each other and the central lines of the two line segments are in the polygon; s4, obtaining mutually corresponding edges from the non-parallel edges; s5, acquiring a central line segment according to the mutually corresponding edges; and S6, acquiring the circuit connection topology information according to the center line segment. The invention obtains the topological information of the circuit connecting line corresponding to the circuit layout by obtaining the layout pattern and solving the center line segment of the edge according to the information of the edge of the circuit layout pattern.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a method for acquiring circuit connection topology information.
Background
Given an integrated circuit layout, it is necessary to extract a center line including a layout wiring pattern in order to reverse a circuit wiring and perform analysis. Referring to fig. 1, the layout pattern may be regarded as a pattern formed by a series of polygons, and each layout polygon is centered to represent the direction and shape of the polygon.
In addition to the regular right-angled polygons of FIG. 1, some layouts may become less regular after Optical Proximity Correction (OPC), as shown in FIG. 2. If the given layout reticle is a post-OPC pattern (fig. 2 (b)), it is necessary to calculate the center line of the layout pattern before OPC (fig. 2 (a)).
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the material described in this section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section.
Disclosure of Invention
Aiming at the technical problems in the related art, the invention provides a method for acquiring circuit connection topology information, which can acquire the circuit connection topology information from a circuit layout.
To achieve the above technical object, an embodiment of the present invention provides a method for obtaining circuit connection topology information, which includes the following steps:
s1, obtaining a circuit layout pattern;
s2, acquiring all edges of the layout pattern according to the circuit layout pattern;
s3, obtaining edges in a mutual corresponding relation among the parallel edges; wherein, the corresponding side is that two line segments have projection between each other and the central lines of the two line segments are in the polygon;
s4, obtaining mutually corresponding edges from the non-parallel edges;
s5, acquiring a central line segment according to the mutually corresponding edges;
and S6, acquiring the topological information of the circuit connection line according to the central line segment.
Further, step S3 specifically includes:
s31, judging whether the two edges are parallel or not; if not parallel, the return is not corresponding to each other; if the two are parallel, continuing;
s32, judging whether the two parallel edges have an overlapping interval or not; if not, returning to be not corresponding to each other; if yes, continuing;
s33, judging whether the central lines of the two edges which are parallel and have the overlapped interval are in the polygon; if not, returning; and if so, returning that the two edges correspond to each other.
Further, step S4 specifically includes:
s41, judging whether the two edges have an overlapping interval; if not, returning to the state of not corresponding to each other; if yes, continuing;
s42, whether a central line formed by the two sides is in the polygon or not; and if so, returning that the two edges correspond to each other.
Further, step S5 specifically includes:
s51, directly solving a central line segment when one side only corresponds to the other side;
s52, when one edge and a plurality of edges correspond to each other, the edges are merged into one edge, and then a central line segment is obtained.
Further, step S6 is followed by one or more of the following steps:
s7, deleting the miscellaneous edges: deleting the central line segments with the distances from other central line segments larger than the length of the central line segments;
or/and
s8, combining parallel lines: merging central line segments which are parallel to each other and have projection superposition and the distance of which is less than a threshold value;
or/and
s9, crossing: removing the intersection part of two line segments with intersection points;
or/and
s10, elongation and stretching of the centerline: extending and stretching the line segments to intersect;
or/and
s11, connecting the connected subsets, and finding the end points closest to the connected subsets for connection, so that the connected subsets are combined pairwise until all the connected subsets are combined into one.
To achieve the object of the present invention, an embodiment of the present invention further provides an apparatus for acquiring topology information of circuit connection, which includes the following units:
a circuit layout obtaining unit for obtaining a circuit layout pattern;
the side acquisition unit is used for acquiring all sides of the layout pattern according to the circuit layout pattern;
a first corresponding edge acquiring unit configured to acquire edges in a mutually corresponding relationship among mutually parallel edges; wherein, the corresponding side is that two line segments have projection between each other and the central lines of the two line segments are in the polygon;
a second corresponding edge acquiring unit for acquiring mutually corresponding edges from the non-parallel edges;
the central line segment acquisition unit is used for acquiring a central line segment according to the mutually corresponding edges;
and the circuit connection topology information acquisition unit is used for acquiring the topology information of the circuit connection according to the central line segment.
Further, the first corresponding edge obtaining unit of the apparatus further includes:
the parallel edge judging unit is used for judging whether the two edges are parallel or not; if not parallel, the signals return to be not corresponding to each other; if the two are parallel, continuing;
the first coincidence interval judging unit is used for judging whether the two parallel edges have coincidence intervals or not; if not, returning to be not corresponding to each other; if yes, continuing;
the first polygon judging unit is used for judging whether the central lines of two edges which are parallel and have an overlapped interval are in the polygon; if not, returning; and if so, returning that the two edges correspond to each other.
Further, the second corresponding edge obtaining unit of the apparatus further includes:
a second overlap interval determination unit for determining whether there is an overlap interval between the two edges; if not, returning to be not corresponding to each other; if yes, continuing;
the second polygon judging unit is used for judging whether a central line formed by the two edges is in the polygon or not; and if so, returning that the two edges correspond to each other.
Further, the center line segment obtaining unit of the apparatus further includes:
the first acquisition unit is used for directly solving a central line segment when one side only corresponds to the other side;
and the second obtaining unit is used for combining the edges into one line and then solving the central line segment when one edge and the edges correspond to each other.
Further, the device further comprises one or more of the following units:
the edge deletion unit is used for deleting the central line segments with the distances from other central line segments larger than the length of the central line segments;
or/and
the parallel line combination unit is used for combining central line segments which are parallel and have projection superposition and the distance of which is less than a threshold value;
or/and
a cross line processing unit for removing the cross part of two line segments with cross points;
or/and
an elongation and stretch centerline processing unit for elongating and stretching the line segment to intersect;
or/and
and the connected subset processing unit is used for finding the end points closest to the connected subsets to carry out connection, so that the connected subsets are combined pairwise until all the connected subsets are combined into one.
To achieve the object of the present invention, this embodiment further provides an apparatus for acquiring circuit connection topology information, where the apparatus includes a processor, and a non-volatile storage medium, where codes are stored on the non-volatile storage medium, and when the codes are executed by the processor, the codes are used to implement the method in steps S1 to S6.
According to the invention, the topological information of the circuit connecting line corresponding to the circuit layout is obtained by obtaining the layout pattern and solving the center line segment of the edge according to the edge information of the circuit layout file. Furthermore, the embodiment of the invention can also perform optimization processing on the acquired center line segment, such as edge deletion, combination and the like, so as to acquire the center line segment more accurately, and particularly can effectively restore the original layout center line before processing for the mask pattern of the circuit layout processed by Optical Proximity Correction (OPC), so as to acquire the topological information of the circuit connecting line more accurately.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a circuit layout polygon pattern example;
FIG. 2 is a layout reticle pattern after OPC;
fig. 3 is a schematic flowchart of a method for obtaining circuit connection topology information according to an embodiment of the present invention;
FIG. 4 is a schematic projection of line segments on a straight line in an embodiment of the present invention;
FIG. 5 is a schematic diagram of computing a projection between two segments in an embodiment of the invention;
FIG. 6 is a diagram illustrating the calculation of a centerline segment from parallel segments according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a non-parallel line segment centering line segment in an embodiment of the present invention;
FIG. 8 is a schematic view of an optimization center line segment in an embodiment of the present invention;
FIG. 9 is a schematic diagram of an apparatus for obtaining topology information of circuit traces according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a topology information device for acquiring circuit connection according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
Example one
Referring to fig. 1, the embodiment implements a method for obtaining circuit connection topology information, which includes the following steps:
s1, obtaining a circuit layout pattern;
the circuit layout pattern in this embodiment may be a GDSII file, or may be another file representing the circuit layout pattern, for example, a formatted file, where the formatted file stores information of an edge of the circuit layout file, and the like.
S2, acquiring all edges of the layout pattern according to the circuit layout pattern;
specifically, if the GDSII file is obtained, the GDSII file needs to be converted into a formatted file, the formatted file stores side information, the side information is represented in a side data structure, and a data structure stores basic information of a line segment, including two end points of the line segment, and parameters, such as a slope, of a straight line corresponding to the line segment. And then all the edges of the layout pattern can be obtained from the formatted file.
S3, obtaining edges in a corresponding relation among the parallel edges; wherein, the corresponding side is that two line segments have projection between each other and the central lines of the two line segments are in the polygon;
when obtaining the centerline segment in this embodiment, a corresponding edge is obtained first, and the corresponding edge in this embodiment is defined as: if the two edges are corresponding to each other, the obtained central line segment is close to or coincident with a certain section of the standard central line.
Specifically, the following two edges may be used to determine whether the two edges correspond to each other: 1) The two line segments have projections with each other; 2) The central line segment of the two parallel line segments is within this polygon.
The projection of one line segment on the other line segment is the projection of the line on the other line segment. The projection of the line segment on the straight line is shown in fig. 4, wherein the thick line region is the projection region.
In order to find the corresponding edge, it is first determined whether there is a projection overlap between two line segments. For example, there are two segments AB and CD, and the projection line segment of AB on the straight line of CD is denoted as EF. If there is coincidence between segments EF and CD, it indicates that segment AB has a projected overlap region on segment CD. And two segments are only said to have a projection on each other if segment AB has a projection on segment CD, while segment CD has a projection on segment AB.
In this embodiment, step S3 further includes:
s31, judging whether the two edges are parallel or not; if not parallel, the signals return to be not corresponding to each other; if the two are parallel, continuing;
s32, judging whether the two parallel edges have a coincidence interval or not; if not, returning to the state of not corresponding to each other; if yes, continuing;
s33, judging whether the central lines of the two sides which are parallel and have the overlapped interval are in the polygon; if not, returning; and if so, returning that the two edges correspond to each other.
In this embodiment, all edges are obtained first, and a combination of two parallel edges and projections is found as an alternative mutually corresponding edge according to the method with reference to fig. 5 (a).
In addition to determining whether there is a projection between every two pixels, it is further determined whether two edges form a corresponding edge, and whether the central line segment is located inside the polygon, specifically, a scanning line may be used to mark all pixels in the polygon first, and then determine whether the trajectory of the current central line is within the polygon range. Only if its central line segment is inside the polygon, the two edges can finally constitute the corresponding edge.
S4, not matching edges, and obtaining corresponding edges from the non-parallel edges;
after the step S3, when some edges in the layout file are not parallel, referring to fig. 5 (b), for other edges for which no corresponding edge is found in the step S3, the following steps are further adopted to determine whether the corresponding edge exists:
s41, judging whether the two edges have a superposition section; if not, returning to the state of not corresponding to each other; if yes, continuing;
s42, whether a central line formed by the two sides is in the polygon or not; and if so, returning that the two edges correspond to each other.
And S3 and S4, finding out the conditions of all corresponding edges in the layout file.
And S5, acquiring a center line segment according to the mutually corresponding edges, and acquiring topology information of the circuit connecting line according to the center line segment.
According to the obtained central line segment, the circuit connection information can be obtained by connecting the central line segment, so that the topological information of the circuit connection can be obtained from the layout file.
Specifically, it further includes:
s51, when one side only corresponds to the other side, directly solving a central line segment;
s52, when one edge and a plurality of edges correspond to each other, the edges are merged into one edge, and then the central line segment is obtained.
And (3) solving a central line segment of the corresponding edge, and dividing the central line segment into two conditions of parallel corresponding edge and non-parallel corresponding edge:
1. center line segment when corresponding edges are parallel
Under the condition that the corresponding edges are parallel, one edge may correspond to a plurality of parallel edges or only one parallel edge. When it only corresponds to one side, the central line segment is directly obtained. When the distance between the two long edges is equal to the distance between the two long edges, the distance between the two long edges is equal to the distance between the two long edges (the distance is less than a threshold value).
See fig. 6 for the following process:
s521: and firstly taking out the parallel edge closest to the corresponding multiple edges. Then other parallel edges are fetched which are not more than a given threshold from this edge, and if not, fetching is not continued.
S522: if only one parallel corresponding edge is taken out, the central line segment is directly solved.
S533: if a plurality of parallel corresponding edges are taken out, the length of each edge is taken as weight, a long edge is calculated to represent the plurality of parallel edges, and then the central line segments of the long edge are summed. Supposing that n parallel short line segments need to be merged, the slope is k, and the formula of the straight line corresponding to the ith line segment is y i ＝k×x i +b i The length of the line segment is l i Then, after the line segments are merged, the corresponding straight line y is shown in formula (1).
2. Center line segment when corresponding sides are not parallel
In the case where the corresponding sides are not parallel, one side may correspond to a plurality of non-parallel sides, or may correspond to one side. And directly solving the central line segment corresponding to one condition. Corresponding to the condition of a plurality of unparallel edges, respectively solving the unparallel edges and the central line segment of each corresponding edge.
The method for directly solving the center line segment and each corresponding edge comprises the following steps: the angular bisector of a straight line where the two line segments are located is firstly solved, and then the intersection part of the angular bisector and the overlapped area is solved and used as a central line segment. Figure 7 shows a centerline segment for two non-parallel edges.
The result of the centerline segment obtained in step S5 is similar to the actual centerline, but is still a series of unordered, disconnected or partially overlapped segments. There is also a need for an integration process that includes: 1) Removing impurity edges; 2) Merging overlapped line segments; 3) Removing the crossed part of the crossed line segment; 4) And connecting the front and rear central line segments. And finally, combining all the central line segments into a whole, and converting the whole into points to be output in sequence.
The method specifically comprises the following steps:
s6, deleting impurity and removing side: if the current centerline segment is further away from all other centerline segments, such as: the minimum of its distances from all centerline segments is greater than its length, then the current segment may be removed.
S7, combining overlapped line segments: if multiple line segments are parallel to each other with the projections coincident and are spaced from each other by less than a threshold, then the line segments can be merged as shown in FIG. 8 (a), and the calculation is shown in equation (1).
S8, removing the crossed part of the crossed line segments: if two line segments are crossed, the self-crossing point is the boundary point of each line segment, each line segment is divided into two parts, and the shorter part of the overlapped part is removed respectively. As shown in fig. 8 (b), when line segments intersect, the segments are divided by the intersection point, and then the longer portions of the segments are combined.
S9, communicating front and rear central line segments: and respectively solving the line segment closest to the end points of the two end points of each line segment, and if the distance is less than a certain threshold, and the threshold can be 1 time of the length of the current line segment, performing connection processing. If the adjacent line segments are not parallel to the current line segment, lengthening the adjacent line segments when the adjacent line segments are connected; if parallel, stretching treatment is carried out during connection.
After the above steps are processed, all line segments may not be connected. And S9, calling the connected line segments as connected subsets. And finding the end points with the shortest distance among the connected subsets to connect, and combining the connected subsets pairwise until all the connected subsets are combined into one. Fig. 8 (c) (d) (e) give examples of extending, stretching and merging connected subsets, respectively.
And (4) converting into an output format: and finally, traversing all the line segments and outputting points in sequence. Of course, in order to control the number of output points, it is also possible to perform a de-dotting operation, i.e. determine whether each end point falls on a connection line formed by the front and rear end points when traversing a line segment. If true, this endpoint may not use the output.
In the embodiment, the obtained center line segment is optimized, so that the center line segment can be obtained more accurately, and the topology information of the circuit connection line can be obtained more accurately.
Example two
Referring to fig. 9, the present embodiment provides a topology information apparatus for acquiring circuit wiring, which includes the following units:
a circuit layout obtaining unit for obtaining a circuit layout pattern;
the side acquisition unit is used for acquiring all sides of the layout pattern according to the circuit layout pattern;
a first corresponding edge acquiring unit configured to acquire edges in a mutually corresponding relationship among mutually parallel edges; wherein, the corresponding side is that two line segments have projection between each other and the central lines of the two line segments are in the polygon;
a second corresponding edge acquiring unit for acquiring mutually corresponding edges from the non-parallel edges;
the central line segment acquisition unit is used for acquiring a central line segment according to the mutually corresponding edges;
and the circuit connection topology information acquisition unit is used for acquiring the topology information of the circuit connection according to the central line segment.
Further, the first corresponding edge obtaining unit of the apparatus further includes:
the parallel edge judging unit is used for judging whether the two edges are parallel or not; if not parallel, the signals return to be not corresponding to each other; if the two are parallel, continuing;
the first coincidence interval judging unit is used for judging whether the two parallel edges have coincidence intervals or not; if not, returning to be not corresponding to each other; if yes, continuing;
the first polygon judging unit is used for judging whether the central lines of two edges which are parallel and have an overlapped interval are in the polygon; if not, returning; and if so, returning that the two edges correspond to each other.
Further, the second corresponding edge obtaining unit of the apparatus further includes:
a second overlapping section judging unit, configured to judge whether there is an overlapping section on the two edges; if not, returning to be not corresponding to each other; if yes, continuing;
the second polygon judging unit is used for judging whether a central line formed by the two edges is in the polygon or not; and if so, returning that the two edges correspond to each other.
Further, the center line segment obtaining unit of the apparatus further includes:
the first acquisition unit is used for directly solving a central line segment when one side only corresponds to the other side;
and the second obtaining unit is used for combining the edges into one line and then solving the central line segment when one edge and the edges correspond to each other.
Further, the device further comprises one or more of the following units:
the edge deletion unit is used for deleting the central line segments with the distances from other central line segments larger than the length of the central line segments;
or/and
the parallel line combining unit is used for combining the central line segments which are parallel to each other and have projection superposition and the distance of which is less than a threshold value;
or/and
the cross line processing unit is used for removing the cross part of two line segments with intersection points;
or/and
an elongation and stretch centerline processing unit for elongating and stretching the line segment to intersect;
or/and
and the connecting subset processing unit is used for finding the end points closest to each other for connection so that the connecting subsets are combined pairwise until all the connecting subsets are combined into one.
EXAMPLE III
Referring to fig. 10, the present embodiment provides a schematic structural diagram of a topology information device 20 that acquires circuit wiring. The topology information acquiring apparatus 20 of the embodiment includes a processor 21, a memory 22, and a computer program stored in the memory 22 and executable on the processor 21. The processor 21 implements the steps in the above-mentioned method for obtaining topology information of circuit connection when executing the computer program, for example, step S1 shown in fig. 2. Alternatively, the processor 21, when executing the computer program, implements the functions of the modules/units in the above-mentioned device embodiments, such as the first obtaining module 11.
Illustratively, the computer program may be divided into one or more modules/units, which are stored in the memory 22 and executed by the processor 21 to accomplish the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution process of the computer program in the topology information device 20 of the acquisition circuit connection.
The topology information device 20 of the acquisition circuit may include, but is not limited to, a processor 21 and a memory 22. It will be understood by those skilled in the art that the schematic diagram is merely an example of the topology information device 20 for acquiring circuit wiring, and does not constitute a limitation of the topology information device 20 for acquiring circuit wiring, and may include more or less components than those shown, or combine some components, or different components, for example, the topology information device 20 for acquiring circuit wiring may further include an input-output device, a network access device, a bus, etc.
The Processor 21 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, and the processor 21 is a control center of the topology information device 20 of the acquisition circuit wiring, and various interfaces and lines are used to connect various parts of the topology information device 20 of the entire acquisition circuit wiring.
The memory 22 may be used to store the computer programs and/or modules, and the processor 21 implements various functions of the topology information device 20 by running or executing the computer programs and/or modules stored in the memory 22 and calling data stored in the memory 22. The memory 22 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
The module/unit integrated by the topology information device 20 for obtaining circuit connection can be stored in a computer readable storage medium if it is implemented in the form of software functional unit and sold or used as a stand-alone product. Based on such understanding, all or part of the flow of the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium and used by the processor 21 to implement the steps of the above embodiments of the method. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U.S. disk, removable hard disk, magnetic diskette, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signal, telecommunications signal, and software distribution medium, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (7)
1. A method for obtaining circuit connection topology information comprises the following steps:
s1, obtaining a circuit layout pattern;
s2, acquiring all edges of the layout pattern according to the circuit layout pattern;
s3, obtaining edges in a mutual corresponding relation among the parallel edges; wherein, the mutually corresponding sides are that two line segments have projection with each other and the central lines of the two line segments are in the polygon;
s4, obtaining mutually corresponding edges from the non-parallel edges;
s5, acquiring a central line segment according to the mutually corresponding edges;
when the mutually corresponding sides are parallel, one side corresponds to at least one parallel side;
s51, directly solving a central line segment when one side only corresponds to one parallel side;
s52, when one edge and a plurality of parallel edges correspond to each other, combining the parallel edges into one edge, and then solving a central line segment;
firstly, taking out a parallel edge closest to one edge from the corresponding parallel edges, and then taking out other parallel edges with the distance from the parallel edge not exceeding a given threshold value;
when only one parallel corresponding side is taken out, directly solving a central line segment;
when a plurality of parallel corresponding edges are taken out, taking the respective lengths of the plurality of parallel corresponding edges as weights, calculating a long edge to represent the plurality of parallel edges, and then summing the central line segments of the long edge;
suppose there is
The parallel short lines of the strips need to be merged, and the slopes are all
First, of
The linear formula of the line segment corresponding to the straight line is
The length of the line segment is
After the line segments are merged, the corresponding straight line
The calculation formula is as follows:
wherein, the first and the second end of the pipe are connected with each other,
to be the equation of a straight line that merges the line segments,
is a slope of the light beam emitted from the light source,
is the number of parallel stubs and is,
is the length of the line segment;
when the mutually corresponding sides are not parallel, one side corresponds to at least one non-parallel side;
s53, when one edge corresponds to one non-parallel edge, directly solving a central line segment;
s54, when one edge corresponds to a plurality of nonparallel edges, respectively solving a central line segment of the one edge and each nonparallel edge;
the method for finding the central line segment of one edge and each non-parallel edge comprises the following steps:
firstly, solving an angular bisector of a straight line where one edge and one non-parallel edge are located;
then, the intersected part of the angle bisector and the overlapping area is solved and used as a central line segment;
s6, deleting the miscellaneous edges: deleting the central line segments with the distances from other central line segments larger than the length of the central line segments;
or/and
s7, merging parallel lines: merging central line segments which are parallel and have projection superposition and the distance of which is less than a threshold value;
or/and
s8, crossing: removing the cross part of two line segments with intersection points;
or/and
s9, elongation and stretching of the centerline: extending and stretching the line segments to intersect;
or/and
s10, connecting the subsets, and finding the end points closest to the subsets for connection, so that every two of the connected subsets are combined until all the connected subsets are combined into one;
and S11, acquiring the topological information of the circuit connection line according to the central line segment.
2. The method according to claim 1, wherein step S3 comprises in particular:
s31, judging whether the two edges are parallel or not; if not parallel, the signals return to be not corresponding to each other; if the two are parallel, continuing;
s32, judging whether the two parallel edges have a coincidence interval or not; if not, returning to be not corresponding to each other; if yes, continuing;
s33, judging whether the central lines of the two edges which are parallel and have the overlapped interval are in the polygon; if not, returning; and if so, returning that the two edges correspond to each other.
3. The method according to claim 1, wherein step S4 comprises in particular:
s41, judging whether the two edges have an overlapping interval; if not, returning to be not corresponding to each other; if yes, continuing;
s42, whether a central line formed by the two sides is in the polygon or not; and if so, returning that the two edges correspond to each other.
4. An apparatus for acquiring circuit connection topology information, comprising the following units:
a circuit layout obtaining unit for obtaining a circuit layout pattern;
the side acquisition unit is used for acquiring all sides of the layout pattern according to the circuit layout pattern;
a first corresponding edge acquiring unit configured to acquire edges in a mutually corresponding relationship among mutually parallel edges; wherein the mutually corresponding sides are that two line segments have projections with each other and the central lines of the two line segments are in the polygon;
a second corresponding edge acquiring unit for acquiring mutually corresponding edges from the non-parallel edges;
a central line segment obtaining unit, configured to obtain a central line segment according to the mutually corresponding edges;
when the corresponding sides are parallel, one side corresponds to at least one parallel side, when one side only corresponds to one parallel side, a central line segment is directly solved, when one side corresponds to a plurality of parallel sides, the plurality of parallel sides are combined into one side, and then the central line segment is solved;
firstly, taking out a parallel edge closest to one edge from the corresponding parallel edges, and then taking out other parallel edges with the distance from the parallel edge not exceeding a given threshold value;
when only one parallel corresponding side is taken out, directly solving a central line segment;
when a plurality of parallel corresponding edges are taken out, taking the respective lengths of the plurality of parallel corresponding edges as weights, calculating a long edge to represent the plurality of parallel edges, and then summing the central line segments of the long edge;
suppose there is
The parallel short lines of the strips need to be merged, and the slopes are all
Of 1 at
The linear formula of the line segment corresponding to the straight line is
The length of the line segment is
After the line segments are merged, the corresponding straight line
The calculation formula is as follows:
wherein the content of the first and second substances,
to be the equation of a straight line that merges the line segments,
is a slope of the light beam emitted from the light source,
is the number of parallel stubs and is,
is the length of the line segment;
when the mutually corresponding sides are not parallel, one side at least corresponds to one non-parallel side, when one side corresponds to one non-parallel side, a central line segment is directly obtained, and when one side corresponds to a plurality of non-parallel sides, central line segments of one side and each non-parallel side are respectively obtained;
the method for finding the central line segment of one edge and each non-parallel edge comprises the following steps:
firstly, solving an angular bisector of a straight line where one edge and one non-parallel edge are located;
then, the intersection part of the angle bisector and the overlapping area is solved and used as a central line segment;
the edge deletion unit is used for deleting the central line segments with the distances from other central line segments larger than the length of the central line segments;
or/and
the parallel line combination unit is used for combining central line segments which are parallel and have projection superposition and the distance of which is less than a threshold value;
or/and
the cross line processing unit is used for removing the cross part of two line segments with intersection points;
or/and
an elongation and stretch centerline processing unit for elongating and stretching the line segment to intersect;
or/and
a connected subset processing unit, which is used for finding the end point with the nearest distance to connect, so that the connected subsets are combined pairwise until all the connected subsets are combined into one;
and the circuit connection topology information acquisition unit is used for acquiring the topology information of the circuit connection according to the central line segment.
5. The apparatus of claim 4, wherein the first obtaining unit further comprises:
the parallel edge judging unit is used for judging whether the two edges are parallel or not; if not parallel, the signals return to be not corresponding to each other; if the two are parallel, continuing;
the first overlapping section judging unit is used for judging whether the two parallel edges have overlapping sections or not; if not, returning to the state of not corresponding to each other; if yes, continuing;
the first polygon judging unit is used for judging whether the central lines of two edges which are parallel and have an overlapped interval are in the polygon; if not, returning; and if so, returning that the two edges correspond to each other.
6. The apparatus of claim 4, the second corresponding edge obtaining unit further comprising:
a second overlapping section judging unit, configured to judge whether there is an overlapping section on the two edges; if not, returning to the state of not corresponding to each other; if yes, continuing;
the second polygon judging unit is used for judging whether a central line formed by the two edges is in the polygon or not; and if so, returning that the two edges correspond to each other.
7. The apparatus of claim 4, the center line segment obtaining unit further comprising:
the first acquisition unit is used for directly calculating a central line segment when one side only corresponds to the other side;
and the second obtaining unit is used for combining the edges into one line and then solving the central line segment when one edge and the edges correspond to each other.
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